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Experiment No.

CHARACTERISTICS OF OPERATIONAL AMPLIFIERS Objective: The objective of this experiment is to observe and measure several important operational amplifier characteristics. These characteristics are mostly a product of the bipolar transistor construction of the actual amplifier. They are especially attributable to the pair of differentially oriented transistors at the amplifier input. Two of the characteristics can be attributed to the internal compensation capacitor of the 741 Op amp. In this experiment, the input bias current, output offset voltage, slew rate and power bandwidth will be measured or calculated and compared to the rated values in the manufacturer's data sheets. The power bandwidth and slew rate will be measured on breadboard circuits. Introduction: Basic Characteristics: a) Input Bias Current and Input Offset Current The 741 contains a differential amplifier input stage. The BJTs that form this differential amplifier require bias currents through their bases. The current is quite small in the 741; the worst-case input bias current in the 741 is 500nA. Figure 1 shows the symbol and pin designations of the 741 Op amp. The input bias currents flow through the bases of T1 and T2. Both currents should be equal because both T1 and T2 are identical and their emitter currents are the same. However, if they are

Figure 1 Symbol and pin designation for the 741 Op-amp (Top View).

not, then there will be an input offset current. The input offset current is the difference between the two currents. This difference may exist as a direct result of internal differences within the BJTs of the Op amp. b) Input Offset Voltage: The 741 OP amp has been designed so that the final stage produces an output voltage of 0 Volts, when the two inputs are at the same potential level. Internal defects can lead to a DC offset at the output. The DC offset can be nulled by one of the following two ways. A DC voltage can be placed in one input terminal when the Op amp is wired as a negative feedback amplifier. The voltage placed on the input is the input offset voltage. In addition, the 741 has nulling terminals where a potentiometer can be connected. The external connections pins 1 and 5 are to the emitters of some internal transistors. c) Common Mode Rejection Ratio: The common mode rejection ratio is the measure of a differential amplifier's ability to reject signals that applied simultaneously to both inputs. Practical operational amplifiers have a finite nonzero common-mode gain. If the two input terminals of the op-amp are tied together and a signal Vcm is applied, the output voltage will be proportional to the input voltage by some constant. This constant will be the common-mode gain Acm. Figure 2 illustrates this definition.

cm

V V

icm

Figure 2 Illustration of the definition of the common mode gain. The output voltage can be expressed as: Vo = A Vid + Acm Vicm A is the differential gain. Acm is the common mode gain. The difference between the two input signals is the differential mode or, in other words, the differential input signal Vid. Vid = V2 V1 The average of the two input signals is the common mode input signal Vicm

The ability of an op-amp to reject common mode signals is specified in terms of the common mode rejection ratio (CMRR) that is defined as:

Usually the CMRR is expressed in dB's.

d) Slew Rate and Power Bandwidth: Slew rate limiting is one of the phenomenons that can cause non-linear distortion of large output signals. The slew rate limitation is present in every modern IC op-amp. It appears as an inability of the op-amp's output stage to follow the input signal presented to the input stage. For example, large step voltages on the input will appear as linearly ramping signals at the output. The slope of the ramping signal is the slew rate. The slew rate is defined as the maximum possible rate of change of the op-amp output voltage. The origin of the slew rate limitation is rooted in complications of the large signal model, transconductance amplifier theory, and internal frequency compensation considerations. However, it is well known that the slew rate of the 741 op-amp is inversely dependent on the value of the internal frequency compensation capacitor of the second stage. No further explanation of the slew rate will be presented here, for it is outside the scope of this report. The power bandwidth is related to slew rate in that it is the maximum frequency before which the slew rate distortion becomes prominent. In practice, signals of a frequency greater than the power bandwidth will appear to rise in a ramp like fashion. The slope of the ramp will be the slew rate. The power bandwidth maximum frequency is related to the slew rate and the peak output voltage by the following equation.

Where Vp is the peak voltage of the output signal and SR is the slew rate. Decreasing the amplitude of the output signal can extend the power bandwidth maximum frequency.

Lab work: 1) Measurement of the input bias current: The circuit of Figure 3 shall be formed on the breadboard. DC voltages at pins 2 and 3 shall be measured with a DC voltmeter. The voltages at pins 2 and 3 are called V(2) and V(3) respectively. The currents ib+ and ib- can be calculated with Ohms Law. The equations in Figure 3 can be used to calculate ib+ and ib- The average of the two currents is called the input bias current. It can be calculated with the equation given on the right hand side of Figure 3. The input offset current is the magnitude of the difference of the two bias currents. It is calculated with the equation given as part of Figure 3. This value of the input bias current should be recorded in Table (I). Throughout this lab, the procedures should be applied to two samples of 741; hence the use of (I) and (II).

Figure 3 Circuit to measure input bias current. The DC voltages measured at pins 2 and 3 were used in Ohms Law to calculate the input bias current. The equations for this task are shown on the side. 2) Measurement of the output offset voltage: The circuit of Figure 4 shall be formed on the breadboard, with both inputs connected to ground through l k resistors. A DC voltage shall be measured at pin 6 (the output). With an output voltage, it is assumed that there is also an input voltage; however, there is no need to measure it. Instead, it should be calculated with the equation given below. This equation was derived from the output equation for the resistive negative feedback operational amplifier. Input offset voltage

( InputOffsetVoltage) : V in =

1k 10k V out

Figure 4 Breadboard circuit used to measure the input offset voltage. The DC voltage at pin 6 is substituted in the equation for Vout. The DC voltage Vin is taken to be the voltage at pin 2 (which could not be measured). The voltage should be recorded in Table (II). Later, a 5 k potentiometer can be connected across pins 1 and 5. It is to be adjusted until the output voltage is 0 Volts. This is done only to illustrate the output offset nulling facility of the 741 Op-amp. No further action should be taken concerning the nulling facility. 3) Measurement of the slew rate and Op amp bandwidth: The inverting amplifier of Figure 5 shall be formed on the breadboard. A square wave of low frequency is to be applied. The input amplitude is to be adjusted until the output is 20volts peak to peak. The frequency is then to be adjusted until the output becomes triangular. Note that at this point (when the output became triangular), the op-amp has reached its maximum output voltage rate of change. The rising edge slope of the triangle-wave was taken to be the slew rate that was being sought. (See Figure 6). The oscilloscope measurements and the slew rate are to be recorded in Table (III). The procedure to measure the power bandwidth is as follows. A sinusoidal signal is applied to the circuit of Figure 5. The frequency is increased until the output waveform begins to appear triangular and its magnitude falls to 70.7% of its original low frequency value. The output signal will appear to show the effects of the slew rate limitation; thats perfectly normal. In

this experiment, the low frequency output signal magnitude is 20 volts peak to peak. At the full power bandwidth, the output signal magnitude should be 14 Volts peak to peak. The data from this part of the experiment is to be recorded in Table (IV).

Figure 5 Slew rate test circuit, this circuit is to be built on the breadboard to evaluate the slew rate. The distorted output signal appears on the oscilloscope as a triangle wave. The slew rate can be measured and calculated directly off the display of the oscilloscop

Report and Error Analysis

1) Input Bias Current: Compare both measured values of the input bias current to the rated value given in the LM741 data sheet. Compare both average input bias and input offset currents to the rated values. In addition, also compare the measured values of Voffset, Gain (dB), and CMRR (dB) to the rated values. Explain any large errors. 2) Input Offset Voltage: Compare the measured input offset voltage to the rated values. Give a percent difference in the report. 3) Slew Rate and Bandwidth: Compare the measured slew rate and bandwidth to the rated values given in the data sheets. Give a percent error. Remember to use the correct data sheets for the ICs of each of the many manufacturers.
Required Materials: Bipolar power supply Function Generator Oscilloscope

100 Resistor (1/4 watt) lk Resistor 10k Resistor 100k Resistor 200k Resistor lM Resistor
1F Capacitor

2 2 2 2 2 3 2 2 1 1 2

10F Cap. 5k Pot 10k Pot


LM741 Op Amp

Measurements:

V(3) (mV) V(2) (mV) ib+ (nA) A741(I) A741(II)

ib- (nA)

iB+ (nA)

ioff (nA)

Table (I) Input Bias Current and Input Offset Current measurements taken from the breadboard test circuit.

Ri () A741(I) A741(II)

Rfb ()

Vout (mV)

Vin (cal offset)(V)

Table (II) Offset Voltage Measurements taken from the breadboard test circuit.

Frequency (Hz) A741(I) A741(II)

V (mV)

t (s)

Slew Rate (calc)

Table (III) Slew Rates measured with the breadboard test circuit

Vin (V) A741(I) A741(II)

Vout (V)

Frequency (Hz)

Table (IV) Power Bandwidth measurements taken from the breadboard test circuit.