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You are here: Home Programming VHDL Code for 2 x 1 Multiplexer January 10, 2014 11:03 am

VHDL Code for 2 x 1 Multiplexer

Posted by Coding Talks on July 27, 2012

VHDL Code for 2 x 1 Multiplexer :

Following code will work like 2:1 MUX in simulator. It very simple and easy to understand.

See Code :

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library ieee; use ieee.std_logic_1164.all; entity bejoy_2x1 is port(d0,d1,s:in std_logic; z:out std_logic; z1,z2: inout std_logic); end bejoy_2x1; architecture arc of bejoy_2x1 is begin z1 <= d0 and (not s); z2 <= (d1 and s); z <= z1 or z2; end arc;

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Filed in: Programming, VHDL Tags: 2 x 1 Multiplexer, code, tutorial, vhdl

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