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VHDL Bsico

I. Introduction Section Questions

(The slides for these questions start at Slide 18.) I.1. VHDL is a hardware description language that can be used to describe designs at various levels of abstractions. Which of the following system descriptions (from the a!s"i and #uhn $%&hart' are directly supported by VHDL( a' b' c' d' e' )ehavioral *odel +tructural *odel ,hysical- eometry *odel .ll the above a and b only

I./. 0he VHDL language was developed under an Institute of 1lectrical and 1lectronic 1ngineers (I111' committee initiative as a standardi2ed language for describing hardware and software. a' 0rue b' 3alse

II. Desi n !"a#$le Section Questions

(The slides for these questions start at Slide %&.) II.1. . VHDL *odel which instantiates components and then interconnects them with each other (and with the outside world' by attaching signals using ,450 *.,+ most li"ely represents which of the following styles of VHDL model( a' )ehavioral +pecification b' Data 3low +pecification c' +tructural +pecification II./. . VHDL *odel which uses abstracts constructs (such as If%0hen%1lse' most li"ely represents which of the following styles of VHDL model( a. b. c. )ehavioral +pecification Data 3low +pecification +tructural +pecification

II.6. . VHDL *odel that e7clusively uses concurrent signal assignment statements to describe the functionality of the design most li"ely represents which of the following styles of VHDL model(


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11. )ehavioral +pecification 1/. Data 3low +pecification 16. +tructural +pecification II.<. 0he time re=uired to perform hardware simulation is directly proportional to the level of hardware fidelity in the model. 0hat is> detailed models of physical hardware ta"e much longer to simulate than abstract or algorithmic models. Which of the following VHDL modeling styles will result in the shortest simulation times( 1. +tructural model /. Dataflow (50L' model 6. )ehavioral model II.?. Which style of VHDL *odel is most appropriate for use during the early stages of a design( c' +tructural model (because components can be easily added and removed' d' Dataflow (50L' model (because logic e=uations can be easily manipulated for design modifications' e' )ehavioral model (because it is implementation independent' f' *i7ture of all three methods (because the appropriate level of abstraction can be chosen which is best suited for our design'

III. 'odel (o#$onents Section Questions

(The slides for these questions start at Slide )).)

III.1. Which of the following is the most accurate statement about VHDL entities and architectures( 1. /. 6. <. . component can have many entity declarations and many architectures. . component can have many entity declarations but only one architecture. . component can have only one entity declaration and many alternative architectures. . component can have only one entity declaration and only one architecture.

III./. Which VHDL statement is used to create parameters which are passed on to the architectures of an entity( 1. /. 6. <. generate statement generic statement guard e7pression globally static%e7pression

III.6. Logic gates may have a minimum input pulse width specification (whereby shorter input pulses are not reproduced at the output'. If a VHDL model must duplicate this logic behavior> then which of the following delay models should be used( a' b' c' d' inertial delay model transport delay model delta delay model any one would produce the desired result


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III.<. Which of the following delay models should be used to simulate !ust the effect of logic propagation delays. 11. inertial delay model 1/. transport delay model 16. delta delay model 1<. any one of them would serve the purpose III.?. Which of the following statements accurately describe @delta delayA( 11. It is an infinitesimal VHDL time unit. 1/. It is used so that all signal assignments can result in signals assuming their values at a future time. 16. It is the default signal assignment if no e7plicit delay model is used 1<. .ll of the above


B*SI( VHDL (onstructs Section Questions

IV.1. Which of the following statements about subtypes is false or inaccurate( 1. /. 6. <. +ubtypes are a constrained form of types +ubtypes define new types +B)0$,1 assignments out of the 0$,1 range are illegal +B)0$,1 negative I+ integer 5.C 1 D/1<:<96E<: to 1.

IV./. Which of the following VHDL statements is an incorrect e7ample of the specified data type( a' .n e7ample use of subtype 0$,1 allFnumbers I+ ( G1G> G1/G> G1/6G> G1/6<G> G1/6<?G'H +B)0$,1 favoriteFnumbers I+ allFnumbers 5.C 1 I1/G 04 I1/6<?GH b' .n e7ample of access type 0$,1 switch I+ .&&1++ switchFinfoH c' .n e7ample of enumeration type 0$,1 operations I+ (.DD> +B)> *BL> DIV'H d' .n e7ample of array type 0$,1 myFrange I+ 5.C 1 /; to 6;H IV.6. Which of the following is not a VHDL data ob!ect 1. signal /. variable


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6. wire <. constant IV.<. Which of the following statements is true( a' b' c' d' constants> signals> and variables are data ob!ects enumeration> integer> physical and floating point are scalar types arrays and record types are composite types the "ey difference between variables and signals is the assignment delay

IV.?. Which of the following statements about ob!ects is incorrect or inaccurate( a. b. c. d. 4b!ects declared in a pac"age are available to all VHDL descriptions that use that pac"age 4b!ects declared in an entity are available to all architectures associated with that entity 4b!ects declared in an architecture body are available to all statements in that architecture 4b!ects declared in a process are available to all processes in the architecture body

IV.E. Which of the following is not a correct or accurate statement about constants( 1. &4C+0.C0 perfectFscoreJ C.0B5.L JK 1;;H is an e7ample of a constant declaration /. 0he assignment of the value to a constant can be done in a pac"age 6. 0he value of a constant must be assigned at the time the constant is declared <. 0he declaration of a constant can appear in a process IV.:. Which of the following VHDL 4b!ects provides a convenient mechanism for local storage by limiting scope to the process where they are declared. a' b' c' d' signals variables constants files

IV.9. VHDL ob!ects of the FFFFFFF class are analogous to wires in a design schematic. 0hey have a history of past> present and future values and their assignment is done after a certain delay. ?. E. :. 9. signals variables constants files
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IV.8. VHDL FFFFFFFF ob!ects are used for te7t input and output> and provide a way for the design to communicate with the host environment. a' b' c' d' signal variable file constant

IV.1;. Which of the following statements are true( a' b' c' d' .ll VHDL processes e7ecute concurrently &oncurrent signal assignment statements are one%line processes +tatements in a process e7ecute se=uentially .ll of the above

IV.11. Which of the following statements are true( 1?. ,ac"ages and libraries provide the ability to reuse constructs in multiple entities and architectures 1E. Items declared in pac"ages can be used (i.e. included' in other VHDL components 1:. ,ac"ages consist of two parts> namely the pac"age declaration and the pac"age body 19. .ll of the above IV.1/. 0he following fragment of VHDL code illustrates the use of what construct( I3 cloc"Gevent .CD cloc" K I1G 0H1C output LK input M1 1CD I3H a' b' c' d' attributes cloc"s comments identifiers

IV.16 Logical operators have FFFFFFFFF compared to other operators 1. /. 6. <. lowest precedence highest precedence medium precedence no precedence


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IV.1<. Which of the following is an incorrect VHDL enumerated data type declaration a' b' c' d' e' 0$,1 weatherFcondition I+ (good> sunny> cloudy> rainy> storm'H 0$,1 currency I+ (dollar> =uarter> dime> nic"el> penny' +B)0$,1 myFcurrency I+ currency 5.C 1 =uarter 04 nic"elH 0$,1 peripherals I+ ( monitor> "eyboard> dis"Fdrive> printer'H none of the above

IV.1?. Which of the following is a correct VHDL integer type declaration( a. b. c. d. &4C+0.C0 temp J integer JK 1;;H +I C.L 7 J integer JK ?H V.5I.)L1 var J integer JK /;H .ll of the above

IV.1E. 0he VHDL 5ecord composite data type is used to group elements of FFFFFFFFF types into a single VHDL ob!ect. a' b' c' d' e' similar different identical integer floating point

V. VHDL !"a#$les Section Questions

1;V.1. With reference to the VHDL code segment> which of the following statements is most accurate( .5&HI01&0B51 testFbehav 43 test I+ V.5I.)L1 7 J )I0 JK I1G H )1 IC ,54&1++ ( inFsig> y' +I C.L y J )I0 JK I;GH )1 IC N JK inFsig N45 yH $ LK inFsig N45 7 H 1CD ,54&1++H 1CD testFbehavH a' . variable (7' is incorrectly declared in the process declaration section
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b' . signal (y' is incorrectly defined in the architecture declaration section c' )oth the Variable and +ignal declarations are incorrect. d' 0he code segment is error free 1;.V./. 3ill in the blan" line identified in the VHDL code fragment below with the appropriate command that will assign a value of one to the variable temp. .5&HI01&0B51 test 43 test I+ +I C.L temp/J IC01 15H )1 IC ,54&1++ (temp/' V.5I.)L1 tempJ IC01 15H )1 IC +ill in the ,lan- here temp/ LK temp M 1H out LK temp/H 1CD ,54&1++H 1CD 01+0H a' temp JK I1GH b' temp JK 1H c' temp JK 1.; H


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