General Purpose Input/Output (GPIO)

Sasang Balachandran 11/08/2009 ECE 480 Design team 3

Keywords
GPIO !C" CP" #DC 89$2

Executive Summary
#%%licati&ns that 'se micr&c&ntr&llers are ra%idl( gr&)ing as c&ts &* %r&d'cti&n l&)er and %er*&rmance &* em+edded s(stems increase the need t& %r&,ide *le-i+ilit( in terms &* data in%'t and &'t%'t is a necessit( t& create ada%ta+ilit( in micr&%r&cess&r c&mm'nicati&n. /he 'se &* General P'r%&se In%'t/O't%'ts is a reali0ati&n &* &%en ended transmissi&n +et)een de,ices &n an em+edded le,el. /hese %ins a,aila+le &n a %r&cess&r can +e %r&grammed t& +e 'sed t& either acce%t in%'t &r %r&,ide &'t%'t t& e-ternal de,ices de%ending &n 'ser desires and a%%licati&ns re1'irements. /he ,aria+le meth&ds &* data handling im%lemented in these %ins s'ch as #DC c&n,ersi&n and interr'%t handling %r&,ide alternati,e 'ses that are ideal *&r m'lti2in%'t a%%licati&ns.

Introduction
# General P'r%&se In%'t/&'t%'t 3GPIO4 is an inter*ace a,aila+le &n m&st m&dern micr&c&ntr&llers 3!C"4 t& %r&,ide an ease &* access t& the de,ices internal %r&%erties. Generall( there are m'lti%le GPIO %ins &n a single !C" *&r the 'se &* m'lti%le interacti&n s& sim'ltane&'s a%%licati&n. /he %ins can +e %r&grammed as in%'t )here data *r&m s&me e-ternal s&'rce is +eing *ed int& the s(stem t& +e mani%'lated at a desired time and l&cati&n. O't%'t can als& +e %er*&rmed &n GPIOs )here *&rmatted date can +e transmitted e**icientl( t& &'tside de,ices this %r&,ides a sim%le mechanism t& %r&gram

and retransmit data de%ending &n 'ser desires thr&'gh a single %&rt inter*ace. /he %ins are 's'all( arranged int& gr&'%s &* 8 %ins )here signals can +e sent &r recei,ed t& and *r&m &ther de,ices. In man( a%%licati&ns the GPIOs can +e c&n*ig'red as interr'%t lines *&r a CP" t& signal immediate %r&cessing &* in%'t lines. In man( ne)er designs the( als& ha,e the a+ilit( t& c&ntr&l and 'se Direct !em&r( #ccess 3D!#4 t& trans*er +l&c5s &* data in a m&re e**icient manner. Essentiall( all %&rts can +e tail&red t& *it s%eci*ic design g&als and %r&,ide re'sa+ilit( )ithin a%%licati&ns.

Objectives
General P'r%&se I/O 3GPIO4 %ins are single need t& +e %r&,ided t& +e ,ersatile t& digital and anal&g signals *&r #DC c&n,ersi&ns. /& %r&,ide e**icienc( the signals m'st +e signals indi,id'all( c&ntr&lla+le &n a %artic'lar chi% +&ard. Each GPIO sh&'ld +e a+le t& de*ine either an in%'t m&de &r an &'t%'t m&de *&r indi,id'al %ins &n the chi%. 6inall( the %ins m'st +e e-tenda+le *&r a )ide arra( &* a%%licati&ns and *'ncti&nal 'ses that de*ine its generalit( in 'se.

GPIO on the LM3S8962

On the 7!3S89$2 the GPIO m&d'les c&nsist &* se,en se%arate +l&c5s each &* these +l&c5s )ill c&rres%&nding t& indi,id'al %&rts &n the GPIO inter*ace the %&rts in &rder are8 3P&rt # P&rt B P&rt C P&rt D P&rt E P&rt 6 P&rt G4. /he GPIO m&d'le &n this +&ard s'%%&rts '% t& 42 %r&gramma+le in%'t &r &'t%'t %ins de%ending &n the s%eci*ic c&n*ig'rati&n +eing ch&sen.

S&me &* the *eat'res &* the %&rts incl'de8 a standard l&gic t&lerance &* '% t& 92: &n +&th in%'t and &'t%'t s%eci*ic %r&gramma+le c&ntr&l *&r GPIO interr'%ts )hich incl'de interr'%t generati&n mas5ing #DC sam%ling %r&gramma+le c&ntr&l *&r GPIO %ad digital in%'t ena+les and &%en drain ena+les. On the 89$2 the data c&ntr&l registers all&) s&*t)are t& c&n*ig're the se%arate %r&gramma+le m&des &n the GPIOs. /his is d&ne +( c&n*ig'ring the data directi&n registers &n the %ins as either in%'t &r &'t%'t *&r the lines. /he data registers themsel,es )ill c&ntain in*&rmati&n t& +e dri,en &'t &* the s(stem &r ne) data that;s entered the s(stem. #n e-am%le &* the se,en %h(sical +l&c5s &* the GPIO is ill'strated +el&)8

Interrupt Handling
In general the interr'%t ca%a+ilities &* each &* the %&rts are maintained +( se,en &* the a,aila+le registers. /hese registers de*ine the s&'rce &* the interr'%ts the t(%e &* interr'%t signal and e,en the edge %r&%ert( &* the signal. In the case )here &ne &* m&re &* the in%'t %ins triggers an interr'%t the signals are &%timi0ed )here &nl( a single interr'%t &'t%'t is sent *&r the entire +l&c5. 6&r the 89$2 s%eci*ic in%'t/&'t%'t %ins can +e assigned t& +e )atched *&r interr'%ts )here the interr'%t handling *'ncti&n can trigger a *'ncti&n &r certain acti&ns t& ta5e %lace &n the micr&c&ntr&ller. #n e-am%le &* an interr'%t handling *'ncti&n is reading acti,e and %ending interr'%ts and dis%la(ing them t& an O7ED 'sing &'t%'t GPIO %&rts. /his is an e-am%le &* s'ch a c&de )ritten in C<<8

Debugging
=hen )riting c&de t& %er*&rm desired &%erati&n &n a micr&c&ntr&ller the need t& de+'g &n a s(stematic +asis in essential t& e**icient c&de design. /he GPIO %ins can +e an e**ecti,e )a( t& m&nit&r and dis%la( in*&rmati&n a+&'t the s(stem in a real time +asis. GPIO %ins can +e 'sed at an( time in test e-ec'ti&n t& dis%la( an( %ertinent in*&rmati&n a+&'t the %r&gram. B( %r&,iding di**erent messages at di**erent stages t& the

GPIO %&rts a %r&gram &r se1'ence &* &%erati&ns can +e easil( *&ll&)ed &n the hard)are le,el.

Register Controls
/& dem&nstrate the *'ncti&n and 'se &* the registers &n a micr&c&ntr&ller the im%lementati&n &n the 89$2 )ill +e 'sed as an e-am%le. /he t)& registers that )ill +e disc'ssed are the data registers and the data directi&n registers. /he data register &n the 7!3S89$2 is re*erred t& as the GPIOD#/# register. =hen )riting c&de t& mani%'late the ,al'es in them ,al'es sh&'ld +e )ritten t& GPIOD#/#. /hese ,al'es )ill +e trans*erred thr&'gh the GPIO %&rts de%ending &n the directi&nalit( &* the %&rt )hich )ill +e disc'ssed ne-t. In &rder t& )rite t& GPIOD#/# the c&rres%&nding +its in the mas5 m'st +e set t& >igh. I* this is n&t the case the +it ,al'es )ill n&t change +( a )rite se1'ence. /his is in,ersel( tr'e *&r ,al'es read *r&m a register. Bits that are 1 in the address mas5 ca'se the c&rres%&nding +its in GPIOD#/# t& +e read and +its that are 0 in the address mas5 ca'se the c&rres%&nding +its in GPIOD#/# t& +e read as 0.6inall( all +its in the registers are cleared in the e,ent &* a reset. # sim%le ma%%ing &* the registers can +e seen *r&m the details &n the 7!3S89$2 datasheet8

Conclusion
/he reas&n )e need %ins that %r&,ide general %'r%&se 'se is t& %r&,ide an inter*ace that can +e c&ntr&lled +( ,ari&'s de,ices and similarl( +e 'sed t& c&ntr&l the +eha,i&r &* &ther de,ices. #s an e-am%le a "SB &r Serial I/ O inter*ace can +e %r&grammed t& c&ntr&l lines &n the GPIO th&'gh register set'% these in t'rn can +e %r&grammed t& c&ntr&l 7EDs &r s)itches &n e-ternal de,ices thr&'gh limited rearrangement &* the %ins &n the +&ard. /he a+ilit( t& %r&gram directi&nalit( *&r indi,id'al a%%licati&ns and the *'ncti&nalit( t& handle interr'%ts and anal&g signals ma5e a%%licati&n c&de de,el&%ed *&r &ne %'r%&se easil( e-tenda+le t& &ther a%%licati&ns

thr&'gh limited editing. /ime and e**icienc( *&r re%etiti,e m&des are the highest %ri&rit( )hen 'sing GPIOs and ,aria+ilit( &* m&dern %r&cess&rs certainl( %r&,ide these re1'ired res%&nsi+ilities.

References
?1@ 7'minar( !icr& EK-LM3S811 Firmware Development Package, #,aila+le at8 htt%8//))).l'minar(micr&.c&m/%r&d'cts/s&*t)areA'%dates.html ?2@ 7'minar( !icr& /echnical Sta** LM3S896 Eval!ation "oar#, $%er&% Man!al /e-as Instr'ments 2009. #,aila+le at8 htt%8//))).l'minar(micr&.c&m/inde-.%h%B &%ti&nCc&mArem&sit&r(D*'ncCd&)nl&ad DidC923Dch5C2229E9d0Ed3e13*deE4ae411E49ae30eDItemidC991