EXP NO: 5 MODELLING OF SEQUENTIAL DIGITAL SYSTEM

DATE: USING VHDL

AIM:
To synthesis and simulate the VHDL code for the Flip flops logic circuits.

APPRATUS REQUIRED:
ISE 9.1 Simulator.
THEORY:
FLIP FLOPS:

A flip-flop is a circuit that has two stable states and can be used to store state
information. Flip flop is a bistable multivibrator. The circuit can be made to change state by
signals applied to one or more control inputs and will have one or two outputs. It is the basic
storage element in sequential logic. Flip-flops is a fundamental building block of digital
electronics systems used in computers, communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. Such data storage can be
used for storage of state, and such a circuit is described as sequential logic. When used in
a finite-state machine, the output and next state depend not only on its current input, but also
on its current state (and hence, previous inputs). It can also be used for counting of pulses,
and for synchronizing variably-timed input signals to some reference timing signal.











PROCEDURE:
1. Design the given flip-flops logic circuit.
2. Write the vhdl code for the design circuit.
3. Create a new project in ISE simulator and select synthesis/Implementation is source
window to synthesis the program.
4. In the source window, right click on project name and click create new source
(a) In the new source wizard select verilog module and type file name and click
next.
(b) Enter the input, output ports and set their directions according in the define
module window.
(c) Enter finish.
5. File name .v window appears, type the program and save it.
6. Go to process window and double click synthesis XST and view RTL model.
CREATING TEST BENCH WAVEFORM:
7. In the source window select behavior simulation.
8. Right click on the project and select new source.
9. Select source type as test bench waveform and give a filename. (filename should not
be the same as the project name).
10. Enter next and click finish.
11. Timing and clock wizard window appears. Set the clock information as combinational
and click finish.
12. Set the input wave form and save.
13. In the process window, choose Xilinx ISE simulator and in that select, .tbw file,
simulate behavioral model.
14. Verify the simulator output with truth table.

RESULT:





(i) D-FLIPFLOP

PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port(d:in STD_LOGIC;
clk:in STD_LOGIC;
rst:in STD_LOGIC;
q:out STD_LOGIC;
qbar:out STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
process(clk,rst)
begin
if(rst==1)then
q<=0;
else if(clkevent and clk=1)then
q<=d;
end if;
end if;
qbar<=not d;
end process;
end Behavioral;


RTL SCHEMATIC:








clk q
d
reset



OUTPUT:





















D FLIPFLOP
DIAGRAM:












CHARACTRISTIC TABLE:
Q D Q(t+1)
0 0 0
0 1 1
1 0 0
1 1 1










(ii) T-FLIPFLOP
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port(t:in STD_LOGIC;
clk:in STD_LOGIC;
rst:in STD_LOGIC;
q:out STD_LOGIC;
qbar:out STD_LOGIC);
end tff;
architecture Behavioral of tff is
signal qt,qbart:STD_LOGIC;
begin
process(clk)
begin
if(rst==0)then
qt<=0;
else if(clkevent and clk=1)then
qt<=(t xor qt);
end if;
end if;
end process;
q<=qt;
qbar<=not qt;
end Behavioral;


RTL SCHEMATIC:







clk q
t
reset qbar





OUTPUT:



























T FLIPFLOP
DIAGRAM:












CHARACTRISTIC TABLE:
Q T Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0








(iii)JK FLIPFLOP
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff is
Port(j:in STD_LOGIC;
k:in STD_LOGIC;
clk:in STD_LOGIC;
rst:in STD_LOGIC;
q:out STD_LOGIC;
qbar:out STD_LOGIC);
end jkff;
architecture Behavioral of jkff is
signal qt,qbart:STD_LOGIC;
begin
process(clk,rst)
begin
if(rst==0)then
qt<=0;
else if(clkevent and clk=1)then
qt<=((not qt) and j)or(qt and (not k));
else
end if;
end if;
end process;
q<=qt;
qbar<=not qt;
end Behavioral;


RTL SCHEMATIC:






clk q
j
k qb
reset



OUTPUT:






















JK FLIPFLOP
DIAGRAM:










CHARACTRISTIC TABLE:

J K Q(t+1)
0 0 Q
0 1 1
1 0 0
1 1 Q











(iv)SR FLIPFLOP
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srff is
Port(s:in STD_LOGIC;
r:in STD_LOGIC;
clk:in STD_LOGIC;
rst:in STD_LOGIC;
q:out STD_LOGIC;
qbar:out STD_LOGIC);
end srff;
architecture Behavioral of srff is
signal qt,qbart:STD_LOGIC;
begin
process(clk,rst)
begin
if(rst==0)then
qt<=0;
else if(clkevent and clk=1)then
qt<= s or ((not r) and qt);
else
end if;
end if;
end process;
q<=qt;
qbar<=not qt;
end Behavioral;


RTL SCHEMATIC:





clk q
r
s qbar
reset




OUTPUT:



























SR FLIPFLOP
DIAGRAM:











CHARACTRISTIC TABLE:
S R Q(t+1)
0 0 Q
0 1 0
1 0 1
1 1 *