1.

1 Basics
We will cover some topics in this section to deal with multiple basic things whi
ch are needed to understand physical design. These will include file types, some
terminologies etc. If you are familiar with this, you can skip this section.
1.1.1 Multiple file/database types
Milkyway library: Also referred as MW library is a Synopsyss internal database to
hold design or library information. Every company has its own database format w
hich is used to store extensive design information. It is all binary and you can
not make anything out of except for maybe directory names. For ICC all design da
ta can be saved as milkway which is on hard disk only. I am not aware of anyway
to save a design in physical memory of your machine. This makes it different and
interesting to handle. Since this internal you dont need to know much about it e
xcept for its directory structure, which you will know very easily once you star
t using ICC.
Netlist: It holds your design circuit in terms of standard cells. You can view t
erminology section for what standard cells mean. Netlist will have input and out
put ports defined. It will have internal nets defined. Then it will use standard
cells to create instances. The instantiation statement will tell about its uniq
ue instance name, which standard cell it uses and connectivity of ports to the n
ets. So netlist is just a collection of cells and nets connecting ports of these
cells. Netlist can be written hierarchically. That is you can define a module (
or design) in netlist and then use (instantiate) it. See a small netlist example
below:
module dummy_design ( i0, i1, i2, out);
input [1:0] i0;
input i1;
input i2;
output o;
wire net1, net2, net3;
AND2X2 u0 ( a.(i0[0]), .b(i1), .o(net1) );
AND2X2 u1 ( .a(net1), .b(i2), .o(net3) );
NOR3X5 u2 ( .a(i0[1]), .b(net2), .c(i1), .o(net3) );
MUX2X4 u3 ( .d0(net1), .d1(net3), .s(i2), .o(out);
endmodule
Liberty: Liberty is known more as .lib file format. These files contain timing,
power and noise numbers for standard cells or macros. All these numbers (timing/
power/noise) depends on operating conditions (or PVT). See terminology section f
or more on PVT. Hence you will see different liberty files for different operati
ng conditions. You will see all standard cells in a single liberty file.
FRAM: FRAM is abstract physical view of a cell or a macro. FRAM is Synopsys inte
rnal binary format. It will contain information about pins (layer and location).
It contains information about blocked areas for layers. FRAM view is needed by
routers to know where to connect to pins and which areas not to route so that i
t does not short or create DRC with cells internal geometries.
LEF: LEF (Library Exchange Format) contain two types of information. One is abst
ract physical view of a cell and other is technology related routing rules. LEF
is a text file. It will contain information about pins (layer and location). It
contains information about blocked areas for layers. FRAM view is needed by rou
ters to know where to connect to pins and which areas not to route so that it do
es not short or create DRC with cells internal geometries. Technology related da
ta will contain definition of various grids, layers and routing rules (width and
spacing atleast). Usually these two different data will have two different LEF

files. The technology related part is provided by foundry.

DEF: DEF (Design Exchange Format) is a text file format, containing netlist and
a physical information. It contains almost all information to recreate a design.
It contains netlist, floorplan, powerplan, pin geometries, cell placement and r
outing. It contains even more data representing PnR tools like regions (placemen
t regions), routing rules etc.
SDC: SDC stands for Synopsys Design Constraints. This is a text file. It contai
ns timing constraints needed for timing the design. It contains following inform
ation:
Clock definition: Clocks defined on pins with waveform (time period and duty cyc
le).
IO constraints: Defines input and output delays on input and output ports respec
tively. These are needed to tell STA engine at what time wrt clock the data will
be arriving at input ports. For output ports it tells how much time delay shoul
d signal reach the port wrt the clock. IO constraints also defines boundary cond
itions. Like slew and driving cell on input ports. Like load on output ports.
Timing exceptions: There are exceptions defined in terms of false timing path, m
ulticycled paths, asynchronous clocks etc.
Constants: Defines constants 1 b1 or 1 b0 on pins in the design.
Techfile: Techfile in Synopsys internal format contains technology related data
to represent layers and routing rules. Technology related data will contain defi
nition of various grids, layers and routing rules (width and spacing atleast). I
t also contains basic RC estimation values (on per um basis). This is a text fil
e and usually provided by foundry.

TLUplus: TLU+ files are Synopsys internal binary format file. It contains data n
eeded for parasitic (RC) extractions. If this file is missing tool can still do
placement optimization based on RC estimation data present in techfile.
1.1.2 Terminology:
Standard cells: These are small size circuit which performs basic digital functi
ons like inverter, buffer, NOR, NAND XOR, AND, OR, ADDER, MUX, AOI, OAI, LATCH,
FLIP-FLOP etc. There can be some complex functionality cells as well. The import
ant thing about designing them are:
They should be of same height. Widths can vary to accommodate multiple functiona
lities or drive strength.
They should be able to abut next to each other in such a way that there power li
nes form a continuous line where vias can be dropped.
There width should be multiple of placement grid.
Standard cells are usually provided by foundry. But there are other IP vendors w
hich provide standard cell libraries.
Standard cell drive strength: Standard cells represent some basic circuits. Depe
nding on under what part of circuit this cell will be used you might need a smal
l or large drive strength standard cell. For example a cell driving a large net
will need to have a large driving strength. You cannot just have large drive str
ength cells in your library because higher drive takes higher area and power.

Standard cell fillers: These are dummy cells without any functionalities. These
are filled in the empty areas where there are no standard cells. Filler addition
up can be used for multiple reasons. Primary reason till now has been avoiding
DRCs on sub-metal layers (non routing layers like diffusion, well etc). These ar
eas added for continuity of standard cell power rails. In very advanced technolo
gies these can be used to take care of sub-metal layer density.
IO buffers: IO buffers provides interface between outside world signals and core
digital cells. Different type of protection exists inside IO buffer like ESD, l
evel shifting etc. On one side, it has a big pad opening where package bonding w
ires land. On other side it interface with your designs signals. IO buffers are m
ost of the times placed on boundary of your chip.
Flipchip: Flip chip, also known as Controlled Collapse Chip Connection or its ac
ronym, C4, is a method for interconnecting semiconductor devices, such as IC chi
ps and Microelectromechanical systems (MEMS), to external circuitry with solder
bumps that have been deposited onto the chip pads. The solder bumps are deposite
d on the chip pads on the top side of the wafer during the final wafer processin
g step. In order to mount the chip to external circuitry (e.g., a circuit board
or another chip or wafer), it is flipped over so that its top side faces down, a
nd aligned so that its pads align with matching pads on the external circuit, an
d then the solder is flowed to complete the interconnect. This is in contrast to
wire bonding, in which the chip is mounted upright and wires are used to interc
onnect the chip pads to external circuitry. See http://en.wikipedia.org/wiki/Fli
p_chip for more.
Grids: There are multiple grids defined in your techfile (.tf or .LEF). There ar
e mainly 3 kinds of grids you should know of:
Manufacturing grid: This is the minimum grid on which anything can be done. It r
epresent resolution. All layout geometry edges should align on manufacturing gri
d. Usually it is 5nm or lower for latest technologies (90nm and below).
Placement grid: This is horizontal grid specifying where left edge of a standard
cell should be aligned. ICC makes sure that all cells are aligned to placement
grid.
IO grid: This is grid for IO buffer placement. This is not a mandatory grid and
have many times done away with this.
Routing grids: These are most important grid in latest technologies. Usually rou
ter routes almost all wires on these grids to get best results possible. Leaving
a few exception, it is not a must to have routes on grids. Tool usually routes
off-grid to tap pins or to fix some DRCs. Routing grids can be different for all
routing layers.
Fullchip or Top level: Fullchip is top-most level of hierarchy for your product.
This will be the complete product and will contain all IPs (macros). It will co
ntain IO buffers.
Macro: Macro or block is a pre-designed module (IP). We also call it hardened IP
. Hardened means that it has completed implementation. Other than standard cell
s and IOs, almost everything else falls in this category. These could include me
mory, PLL, DLL and other analog IPs. Macros also include other design which are
already implemented using standard cells flow. For example when you will finish
implementing your design (if it is not full chip), it will become a macro at hig
her level of hierarchy. Macros will not contain any IO buffers ideally.
Operating condition: Actual silicon chip can work under different environmental
conditions which we term as operating conditions. Different corners of chip also

operate under different operating conditions. So it becomes challenging to mode

l that on tools so that you can verify that your design indeed meets expected pe
rformance. Operating conditions are often referred to as PVT conditions which me
ans Process (P), Voltage (V) and Temperature (T). Process covers variations in t
erms of manufacturing accuracy. While drawing a geometry in nanometers, the edge
s will not be straight lines and hence you will see that rectangles are either w
ider or thinner. Changes in width or lengths or geometries have effect on perfor
mance. For metal layers, this does not effect that much, but transistor drawn ge
ometries have significant impact on their performance. You will have to design y
our chip in atleast two operating conditions:
Worst case PVT: This will have slowest process corner, lowest voltage and highes
t temperature (can be lowest temperature due to temperature inversion in 65nm an
d below). You want to make sure that your design meets setup and hold times in t
his corner.
Best case PVT: This will have fastest process corner, highest voltage and lowest
temperature.
Preferred direction routing: Routing in design is done via multiple layers. The
way routers are written is such that routing is orthogonal. That is metal is eit
her routed in horizontal direction or vertical direction. To make design easily
routable it is important that tools route successive layers in alternate directi
on. There are two topologies followed, VHV or HVH. VHV means metal1 (bottom most
) layer is vertical, then metal2 is horizontal, then metal3 is vertical and so o
n. HVH means metal1 is horizontal, then metal2 is vertical, then metal3 is horiz
ontal and so on. So each metal layer will have its preferred routing direction.
Tools route more than 99% of the routes in preferred routing directions. Except
for a few exceptions, today all tools allow minor non-preferred direction routin
g to meet DRCs. These are usually done at pin tapings or some congestions areas.
DRC: DRC stand for Design Rule Checks. DRCs can be of two types:
Routing DRCs: These are spacing or width rule checks for layout geometries which
are not met. There are specific routing rules which are defined for router in t
echfile. ICC has to route keeping in mind these rules. Any violations of these r
ules will be flagged as DRC violations. When DRC is mentioned, it is often being
referred as routing DRC. You cannot tapeout a chip with routing DRCs. All needs
to be fixed. If your chip does not meet performance you can still run it at low
er frequency, but if it has routing DRCs, it cannot be manufactured.
Logical DRCs: These are Design Rule Check violations for maximum slew, maximum c
apacitance and maximum fanout. While doing PnR, tool is given constraints of max
imum cap (capacitance), slew and fanout. If these values for above the limit, it
becomes a logical DRC violations. Logical DRC violations are not hard violation
s as you can still tapeout with
STA or Timing: Static timing analysis is predicting performance without doing si
mulations. Whole design is divided into 4 types of paths. A path in STA is a seq
uence of connected cells. You estimate how much time a signal will take to reach
from startpoint to endpoint in a path. A path can start from a flop output or a
n input port which becomes startpoints. Similarly a path can end in flop data in
put or an output port. Given this you can have 4 types of paths, input to output
, input to flop data in, flop out to flop data in and flop out to output. Signal
launched on a clock-edge from a startpoint should reach the end point before ne
xt clock-edge else it will violate setup requirements for endpoint flop. There i

s also a minimum requirement on the delay else it will violate hold requirements
of endpoint flop. STA analysis the whole design performance in terms of setup a
nd hold time. Any violation in setup and hold time results in setup and hold vio
lation which are known as slack. Slack represents the time delay by which setup
or hold violates the requirements.
Timing term can be used in place of STA or performance.
WNS: Worst negative slack is maximum negative slack across all STA paths in desi
gn.
TNS: Total negative slack is sum of all negative slacks across all STA paths in
the design.
1.1.3 Abbreviations
WNS:
TNS:
STA:
DRC:
SDC:

Worst Negative Slack

Total Negative Slack
Static Timing Analysis
Design Rule Constraints
Synopsys Design Constraints

1.2 Physical Design Flow

There are multiple implementation flows namely:
Block level flat implementation flow.
Top level Flat implementation flow.
Top level Hierarchical implementation flow.
Top level hierarchical flow is complex then block level, but in a way uses block
level flat flow for implementation of blocks. Usually people getting into physi
cal design start with block level flat implementation flow and then move on to h
ierarchical flow. That is one of the motivations to treat them separately. We wi
ll also be going through the flow in similar manner, to make it easier to unders
tand.
To best of my knowledge all physical design suites are based on TCL and hence it
becomes very important for the people aspiring to be PD engineers to be very we
ll conversant with TCL. You can find many TCL tutorials on the web. Though tools
TCL wouldbe a superset comprising of more commands then TCL. These will include t
he tools commands and some more added commands to interface with tools data mode
l. We will not be covering any tools data model in detail in this tutorial as th
ey vary a lot with tools and can change anytime.