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AN2592
Application note
How to achieve 32-bit timer resolution using the link system
in STM32F101xx and STM32F103xx microcontrollers
Introduction
In many applications, 32-bit resolution is required to measure external signal periods of up
to several hundreds of seconds or, to generate delays or periodic signals with large periods.
The STM32F101xx and STM32F103xx microcontrollers offer the possibility of chaining two
16-bit timers to obtain a 32-bit resolution based on a specific configuration of the timers and
on the use of the timer link system.
This application note gives general guidelines to emulate a 32-bit timer. The two basic
operating modes, that is the input capture mode and the output compare mode, are
presented. Each mode is treated independently and, each time, examples of applications
are provided.
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Contents AN2592 - Application note
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Contents
1 STM32F10xxx timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Timer link system presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 How to synchronize two timers using the link system . . . . . . . . . . . . . . . . 4
2 32-bit input capture timer resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 TIM3 master configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.2 TIM2 slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.3 Master and slave synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 32-bit output compare timer resolution . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Principle and timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Output compare mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.1 Output compare active mode example . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.2 Output compare toggle mode example . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AN2592 - Application note List of figures
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List of figures
Figure 1. Simplified TIM2 trigger controller block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Timer synchronization in input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Timer synchronization in output compare mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. TIM2 output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. TIM2 output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. TIM2 Channel1 output signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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1 STM32F10xxx timer synchronization
1.1 Timer link system presentation
In the STM32F101xx and STM32F103xx microcontrollers, the embedded timers can be
linked together for timer synchronization or chaining purposes.
Using the timer link system, a timer configured in Master mode can:
reset the counter of the slave timer
start and/or stop the slave timer counter
clock the slave timer counter
1.2 How to synchronize two timers using the link system
In addition to the TIMx_CHx pins, timers have several internal triggers that are
indispensable for linking and chaining operation.
Figure 1 shows a simplified representation of the timer block, that highlights the internal
triggers. TIM2 is used as an example.
Figure 1. Simplified TIM2 trigger controller block
The internal triggers (ITR0, ITR2 and ITR3) are used when TIM2 is configured in the Slave
mode. They then determine which master controls TIM2.
TIMxCLK
ETR
TRG01
TRG03
TRG04
ITR0
ITR2
ITR3
TIM2
Trigger
controller
TRG0 TRG02
TI1FP1
TI2FP2
ai14603
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For example, if TIM2 uses ITR2 as an internal trigger, this means that TIM2 is synchronized
with TIM3.
These triggers can be easily redirected to the master by setting the right combination of TS
bits in the SMCR register.
The trigger output, TRGO, is used when TIM2 is configured in the Master mode. It then
determines which events or signals is sent to the slave timers for synchronization.
Different events or signals can be transmitted to the slave, as listed below. They are selected
using the MMS bits in the CR2 register.
reset event
enable event
update event
compare pulse
OCxREF where x is 1, 2, 3 or 4.
Once the master trigger output, TRGO, and the slaves internal triggers, ITRx, are
configured, the two timers are chained.
There are four different slave modes that are selected using the SMS bits in the SMCR
register. They are the following:
Reset mode: in this mode, the rising edge of the trigger signal reinitializes the counter
and generates an update of the registers.
Gated mode: the slave counter start and stop are both controlled by the high level on
the trigger input.
Trigger mode: the start of the slave counter is controlled by the rising edge of the trigger
input signal.
External clock mode1: the slave counter is clocked by the rising edges of the selected
trigger input signal.
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2 32-bit input capture timer resolution
2.1 Principle
To measure the period of an external signal, the timer can be used in input capture mode.
The maximum frequency, that can be measured with the 16-bit timer, depends on the
TIMxCLK signal.
For example, if the timer is clocked by 72 MHz (TIMxCLK = 72 MHz), the minimum
frequency F that can be measured is:
In some applications, the user needs to measure large periods. The idea is to increase the
timer resolution from 16-bit to 32-bit using a specific configuration based on the timer link
system.
2.2 Timer configuration
The measure is performed by two timers synchronized in a specific mode. The master
measures the LSB part of the external signal period/frequency and the slave measures the
MSB part. The two timers are used in input capture mode.
Figure 2 further explains the typical internal connection of the master and slave timers. TIM3
is used as the master for the TIM2 timer.
F
TIMxCLK
ARR
---------------------------
72 10
6
0xFFFF
------------------------ 1098 Hz = = =
AN2592 - Application note 32-bit input capture timer resolution
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Figure 2. Timer synchronization in input capture mode
2.2.1 TIM3 master configuration
The master timer is used to measure the LSB part of the external period or frequency. To do
so, it is configured as follows:
no prescaler is used
the external signal is connected to channel 1 and the rising edge is configured as the
active edge.
The input capture module is used to latch the value of the counter after a transition detected
by the corresponding input channel. To get the external signal period, two consecutive
captures are needed and the period is calculated by subtracting these two values.
To avoid this method and facilitate the input capture measurement, the master counter is
reset after each rising edge detected on the timer input channel by:
selecting TI1FP1 as the input trigger by setting the TS bits in the SMCR register
selecting the reset mode as the slave mode by configuring the SMS bits in the SMCR
register
Using this configuration, when an edge is detected, the counter is reset and the period of
the external signal is automatically given by the value on the CCR1 register.
TIMxCLK
ETR
TRG01
TRG03
TRG04
ITR0
ITR2
ITR3
TIM2
Trigger
controller
TRG0
TI1FP1
TI2FP2
Input filter &
edge detector
16-bit CCR1 register
ITR0
ITR1
ITR3
TIM3
Trigger
controller
TRG0
TI1FP1
TI2FP2
Input filter &
edge detector
16-bit CCR1 register
TI1
TI1
External signal
TIMxCLK
TRG02
ai14604
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2.2.2 TIM2 slave configuration
The slave timer is used to measure the MSB part of the external frequency. To do so, it is
configured as follows:
prescaler is fixed to 0xFFFF
the external signal is connected to channel 1 and the rising edge is configured as the
active edge.
2.2.3 Master and slave synchronization
Master configuration
Use the master update event as the master trigger output (TRGO)
Enable the Master/Slave mode.
Slave configuration
Select the slave input trigger: the master trigger output (TRGO) used as the input
trigger for the slave.
Enable the Master/Slave mode
Use the external clock mode 1 as the Slave mode: the slave is clocked by the update
event of the master timer. That is, when the master counter is overflow, the slave
counter is incremented.
Using this configuration, each time the period to be measured exceeds the 16-bit master
timer Auto-reload register, an update event is generated to clock the slave timer.
When the active edge is detected on the master and slave timer inputs, the two counter
values are copied into the master CCR1 register and the slave CCR1 register, respectively.
Since the slave is clocked by the master update event, the number of master overflow is
recorded by the slave as the MSB part of the 32-bit input capture register, the LSB is read
on the Master CCR1.
The external signal frequency is calculated on each master input capture interrupt as
follows:
LSB is the master capture compare register value (LSB = TIM3->CCR1 register value).
To get the MSB value, two consecutive captures are needed and the MSB variable is
calculated by subtracting these two values as shown below:
If MSB1 > MSB2 then MSB = 0xFFFF ((MSB1 MSB2)) 1
If MSB1 < MSB2 then MSB = (MSB2 MSB1) 1
MSB1 and MSB2 are given by the slave capture compare value (TIM2->CCR2 register
value).
Since the master timer is used in Reset mode, when the active edge is detected on the
master timer, the counter is reinitialized and an update is generated. To avoid this additional
update event, 1 is subtracted from the MSB value.
Using this method, the maximum frequency that can be measured, with TIMxCLK equal to
72 MHz, is 17 mHz instead of 1098 Hz when a 16-bit timer is used.
ExtSignalFreq
72 10
6