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.
Provides a total of 64 Mbytes of SDRAM and 512 Kbytes of Flash EPROM.
word[0] Line in the code where the diag failure is issued
word[1] Software item where the failure has been detected
word[2] Software line in the code where the error has been detected
word[3] Type of the detected error
(1)
(see Tab. 5.2)
word[0] Line in the code where the diag failure is issued
word[1] Software item where the failure has been detected
word[2] Softwareline in the code where the error has been detected
word[3] Type of the detected error
(1)
(see Tab. 5.2)
word[4] IXLT card alarm register
word[5] IXLT card sense point register
word[6] IXLT card loopback register
word[7] IXLT card control point register
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Provides two programmable serial communication channels.
Provides a high speed serial link.
Allows the handling of 12 sources of interrupts by two programmable interrupt
controller.
Provides maintenance circuitry for fault detection of microprocessor device and
associated circuits.
Allows the handling of the external alarms coming from the peripheral boards.
Houses the conguration control logic that selects the active copy of MPCC board.
MPCC diagnostics have been implemented with 3 working phases (see paragraph
5.4.2).
a) MPCC diag start phase
This phase consists of the check of the power supplier card.
OUTPUT if start phase fails:
b) MPCC diag phase 1
This phase consists of check of the alarm circuit of the card and its subsequent
reset.
OUTPUT if phase 1 fails:
c) MPCC diag phase 2
This phase consists of rmware card and hot link diagnostics.
OUTPUT if phase 2 fails:
d) MPCC diag phase 3
This phase consists of verifying if the rmware must be updated. The third phase is
executed only if the card has a rmware version to be updated; the decision is taken
by the Processor Complex Device Handler by querying the software Handling. Its to
be noticed that, in the negative event that the rmware does not work well, the
MPCC diagnostic is considered failed and the additional information reported to the
operator will highlight the cause. At this point, the operator must replace the card put
out of service for rmware problems. A subsequent diagnostic does not recover the
situation: it immediately will not succeed because the rmware test will not pass at
the second phase.
OUTPUT if phase 3 fails:
word[0] Line in the code where the diag failure is issued.
word[0] Software item where the failure has been detected
word[1] Software line in the code where the error has been detected
word[2] Type of the detected error
(1)
(see Tab. 5.2)
word[0] Software line in the code where the error has been reported
word[1] Software item where the failure has been detected
word[2] Software line in the code where the error has been detected
word[3] Type of the detected error
(1)
(see Tab. 5.2)
word[4] The signal subtype used to invoke the firmware
word[5] The firmware response
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e) MPCC diag end phase
This phase is meaningless.
5.4.5 TDPC Diagnostics
The TDPC is responsible for exchanging messages with the other network entities via
the LAPD and the SS7 processors. It handles all signalling functions above MTP layer
2 and all application processes related to call control, radio resource management and
mobility management.
The TDPC card is implemented with a 1+1 redundancy (active and stand-by copy).
The TDPC board provides the following functions:
Implements a microprocessor circuit based on a CPUIntel Pentium
.
Provides a total of 64 Mbytes of SDRAM and 512 Kbytes of Flash EPROM.
Provides two programmable serial communication channels.
Provides a high speed serial link.
Allows the handling of 12 sources of interrupts by two programmable interrupt
controller.
Provides maintenance circuitry for fault detection of microprocessor device and
associated circuits.
Provides a double interface toward the MEMT, PPXL boards by means of duplicated
address, data and control busses.
Allows the handling of the external alarms coming from MEMT, PPXL boards.
Allows the handling of two external reset and interrupt sources coming from MPCC.
Provides the or-function for sixteen external interrupts coming from PPXL boards.
Provides eighteen programmable selection board signals used for the PPXL boards.
TDPC diagnostics have been implemented with 3 working phases (see paragraph
5.4.2).
a) TDPC diag start phase
This phase consists in the check of the power supplier of the card.
OUTPUT if start phase fails:
b) TDPC diag phase 1
This phase checks that at least one MEMT copy is available to perform the diag-
nostic.
OUTPUT if phase 1 fails:
word[0] Software line in the code where the error has been reported
word[1] Software item where the failure has been detected
word[2] Software line in the code where the error has been detected
word[3] Type of the detected error
(1)
.(see Tab. 5.2)
ERR_firmware_STATE
ERR_firmware_TMOUT
ERR_firmware_CODE
word[4] The Operating System response
word[0] Line in the code where the diag failure is issued.
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c) TDPC diag phase 2
This phase consists in the check of the alarm circuit of the card and its subsequent
reset.
OUTPUT if phase 2 fails:
See previous phase.
d) TDPC diag phase 3
This phase consists of the check of the alarm circuit of the card by means of a card
reset and subsequent result of the autotest by the TDPC rmware (phase meaning-
less in the event of TDPC outage).
OUTPUT if phase 3 fails:
e) TDPC diag end phase
This phase is meaningless.
5.4.6 MEMT Diagnostics
The MEMT cards are used only as a communication vehicle between the MPCCand the
TDPC cards (DUAM functionality).
The MEMT implements:
4kx16 semaphored Dual Port Ram (DPMT) which implements the communications
between the TDPC and the MPCC;
two sixteen bit registers for a fast communication (interrupt handled) between MPCC
and TDPC.
The selection of the active copy of the TDPC is under control of the MPCC.
MEMT diagnostics have been implemented with 2 working phases (see paragraph
5.4.2).
a) MEMT diag start phase
This phase consists on the check of the power supplier of the card.
OUTPUT if start phase fails:
b) MEMT diag phase 1
Full check of the address/data buses from/to the MPCC card, read/write access
check (DUAM only), alarm forcing test.
OUTPUT if phase 1 fails:
word[0] Line in the code where the diag failure is issued
word[0] Line in the code where the diag failure is issued
word[1] Software item where the failure has been detected
word[2] Software line in the code where the error has been detected
word[3] Type of the detected error
(1)
(see Tab. 5.2)
word[4] Command sent to the TDPC firmware that failed
(2)
(see Tab. 5.2)
word[5] Debug data from TDPC firmware
word[0] Line in the code where the diag failure is issued.
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c) MEMT diag phase 2
Full check of the address/data buses from/to the TDPC, read/write access check
(DUAM only), alarm forcing test.
OUTPUT if phase 2 fails:
d) MEMT diag end phase
This phase is meaningless.
word[0] Line in the code where the diag failure is issued
word[1] Software item where the failure has been detected
word[2] Software line in the code where the error has been detected
word[3] Type of the detected error
(1)
(see Tab. 5.2)
word[0] Line in the code where the diag failure is issued
word[1] Software item where the failure has been detected
word[2] Software line in the code where the error has been detected
word[3] Type of the detected error
(1)
(see Tab. 5.2)
LEGEND
(1)
error code management
MEANING ERR. CODE
ERR_PRNMI 0x0A
ERR_PRLOOP 0x0B
ERR_NMIINT 0x0C
ERR_MOUTAGE 0x0D
ERR_INVCONF 0x0E
ERR_IPLOOP 0x10
ERR_AFORCE 0x11
ERR_PCSMT 0x14
ERR_INVCONT 0x15
ERR_PATTERN 0x17
ERR_INVCFG 0x18
ERR_INCONSIST 0x19
ERR_LOCKSEM 0x1A
ERR_DIFF_SENSE 0x1C
ERR_TMOUT 0x1D
ERR_TDPC_MEM 0x1F
ERR_FW_STATE 0x20
Tab. 5.2 Error Codes used by PWRS, MPCC, TDPC, MEMT Diagnosis
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5.4.7 NTW Diagnostics
The NTW object refers to three different cards:
UBEX: Universal Bus EXtender. It allows the MPCCto access the peripheral boards
and collects the interrupt signals coming from them;
PLLH: Phase Lock Looped High performance board. It delivers clock and synchro-
nization signals to all BSC devices. It can work in free-running or synchronized from
an external source (SYNC or SYNE).
SNxx: Switching Matrix at 64/16/8 Kbit/s. It performs, under the MPCC control, the
switching functionality among the channel from/to the line interface cards (LICD) and
peripheral processor boards (PPXX).
NTWdiagnostics has been implemented with 10 working phases (see paragraph 5.4.2).
a) NTW diag start phase
This phase performs a basic init of UBEX, PLLH, SN.
OUTPUT if start phase fails:
ERR_FW_TMOUT 0x21
ERR_FW_CODE 0x22
ERR_TDPC_STALL 0x23
ERR_HW_RESET 0x24
ERR_INV_ADDR 0x25
ERR_INV_ACC 0x26
ERR_MULTI_NMI 0x27
ERR_INV_CODE 0x28
ERR_INV_LEN 0x29
ERR_TINIT_REQ 0x2A
ERR_RTE 0x2B
ERR_MPCC_RESP 0x2D
ERR_TDPC_STATUS 0x2E
ERR_PR_BIST 0x2F
(2) failure of the TDPC FW
T81_FW_40_PROTOCOL_MODE 12
T81_FW_CLEAR_INT_MEMORY 13
T81_FW_START_FULL_DIAG 10
LEGEND
Tab. 5.2 Error Codes used by PWRS, MPCC, TDPC, MEMT Diagnosis
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b) NTW diag phase 1
This phase, after repetition of basic init of the UBEX, forces all of the UBEX alarms
to see that they arise correctly.
OUTPUT if phase 1 fails:
c) NTW diag phase 2
This phase, after repetition of basic init of the PLLH, forces all the PLLH alarms to
see that they arise correctly. Finally, it checks if there are not timing alarms on the
SN introduced by the PLLH.
OUTPUT if phase2 fails:
d) NTW diag phase 3
This phase schedules the self-diagnostic test executed by the residing rmware of
PLLH.
OUTPUT if phase 3 fails:
The same of phase 2.
e) NTW diag phase 4
This phase, after repetition of basic init of SN, forces all the alarms of SN to see if
they arise correctly.
OUTPUT if phase 4 fails:
For SN16
word[0] Internal error code(1).
word[1] Code for faulted device(2).
word[2] UBEX alarm register (3).
word[3] PLLH alarm register (4).
word[4] Cause of PLLH interrupt (12).
word[5] control alarm register of SN16(6) or SNAP(6).
word[6] input alarm register of SN16(8) or SNAP(13).
word[7] output alarm register of SN16(10) or SNAP(14).
word[0] Internal error code(1).
word[1] Code for faulted device(2).
word[2] UBEX alarm register(3).
word[0] Internal error code(1).
word[1] Code for faulted device(2).
word[2] PLLH alarm register(3).
word[3] Cause of PLLH interrupt(12).
word[0] Internal error code(1).
word[1] SNxx global alarm register(2).
word[2] Mask of the parity alarm of the incoming PCM lines at 8Mb/s n 16...23
word[3] Mask of the parity alarm of the incoming PCM lines at 8Mb/s n 0...15
word[4] Mask of the parity alarm of the incoming PCM lines at 2Mb/s n 0..3
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FOR SNAP
f) NTW diag phase 5 and phase 6: these two phases are skipped because they are
reserved to an hardware not supported.
g) NTW diag phase 7
SN16/SNAP: writes for diagnostics an address with a wrong parity, one by one, in
each location of the speech RAM, and checks that the alarmis detected by the gate
array.
OUTPUT if phase 7 fails:
For SN16
The same of phase 4.
For SNAP (if SNAP drivers failed).
h) NTW diag phase 8
SN16/SNAP: writes for diagnostic a datum with a wrong parity, one by one, in each
location of the speech RAM, and checks that the alarmis detected by the gate array.
OUTPUT if phase 8 fails:
The same of phase 4.
word[5] Mask of the comparision alarm of the outgoing PCM lines at 8Mb/s
n16...23
word[6] Mask of the comparision alarm of the outgoing PCM lines at 8Mb/s
n0...15
word[7] Bit mask of the other SNxx alarms(11).
word[0] Internal error code(1)
word[1] Snap Control Block Alarm register.
word[2] Snap Input Block Alarm register.
word[3] Ubex Address Bus register (bit 8...15).UBEX data bus register (bit 0...7)
word[4] Input alarm register of SN16(8) or SNAP(13)
word[5] Bank of Speech RAM Alarmed - Trapped Control RAM Address for
Speech RAM Data error(15).
word[6] Bank of Speech RAM Alarmed - Trapped Control RAM Address for
Speech RAM Address error(15).
word[7] Bank of Control RAM Alarmed - Trapped Control RAM Address for
Control RAM Data error(15).
word[0] Internal error code(1).
word[1] Line number of the module where error occurred.
word[2] Name of the module where error occurred.
word[3] FF
word[4] FF
word[5] FF
word[6] FF
word[7] FF
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i) NTW diag phase 9
SN16/SNAP: a wrong parity is written one by one in all the locations of the control
RAM to see if the alarm is detected by the gate array.
OUTPUT if phase 9 fails:
The same of phase 4.
j) NTW diag phase 10
SNAP: it performs a loop-test for all the channels, with pattern insertion at input and
verication that the same pattern is transmitted in output.
OUTPUT if phase 10 fails:
If test fails
If Snap drivers fails
k) NTW diag end phase
This phase is meaningless.
word[0] iSNAP Control Block Alarm Register.
word[1] SNAP Input Block Alarm Register.
word[2] SNAP Output Block Alarm Register.
word[3] Trapped value on 8Mb/s input line, before pattern insertion-Pattern
inserted on 8 Mb/s input line-Trapped value on 8 Mb/s output line.
word[4] Number of physical input line.
word[5] Number of time slot at 8 Kb/s on physical input line.
word[6] Number of physical output line.
word[7] Number of time slot at 8 Kb/s on physical output line.
word[0] Internal error code(1).
word[1] Line number of the module where error occurred.
word[2] Name of the module where error occurred.
word[3] FF
word[4] FF
word[5] FF
word[6] FF
word[7] FF
LEGEND
(1) The possible error codes issued by NTW diagnostic are listed
ERR. CODE MEANING
1 loop back test failed
2 parity error on UBEX bus
3 an unexpected alarm is found active
Tab. 5.3 Error Codes used by NTW Diagnostics
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5 forcing an alarm has no effect
6 (only PLLH) CRC error in the firmware protocol
7 (only PLLH) state inconsistency of the firmware
protocol
8 time out occurred in the hardware/firmware oper-
ation
17 the hardware has been found in unexpected state
(typical for PLLH: it is found master when
expected slave)
18 a connection in SNxx has been performed incor-
rectly by the hardware
19 (only SNxx): an unexpected value, different from
a test pattern previously inserted, has been
trapped in an incoming PCM channel
20 (only SNxx): an unexpected value, different from
a test pattern previously inserted, has been
trapped in an outgoing PCM channel
21 (only SNxx): interference between the values
transmitted on outgoing channels
22 (only SNxx): interference between the data
written in 2 different locations of the control
memory, after performing connections for test
purposes
23 (only PLLH): failure of a firmware auto-diagnose
26 (only SNxx): the type of switching matrix is
different from the one required by the BSC data
base
30 an unexpected NMI has arisen while accessing to
the hardware
(2) Code indicating the faulted device. Generally it should be consistent with the card
indicated in the proposed repair action
1 error on UBEX
2 error on PLLH
4 error on SN16
5 error on SNAP
(3) UBEX alarm register
Bit n Meaning
LEGEND
Tab. 5.3 Error Codes used by NTW Diagnostics
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7 If 1, there is an alarm forcing in progress
6 0
5 0
4 0
3 0
2 Chip select error
1 Data parity error
0 Address parity error
(4) PLLH alarm register
Bit n Meaning
7 WDT alarm of local CPU
6 UBEX bus data parity error
5 UBEX bus address parity error
4 PLLH 0 and 1 not synchronization (it is normal if
the other PLLH is failed)
3 Lack of the signal on the maintenance selector (it
is normal, if no synch. Source is under test)
2 Lack of outgoing signal
1 Lack of external synchronism (it is normal if the
PLLH is not synchronized master)
0 If 1, PLLH outputs its signal, otherwise the signals
of other PLLH
(6) SN16/SNAP control alarm register
Bit n Meaning
7 Lack of synchronism to the control gate array
6 Lack of clock to the control gate array
5 Generic internal alarm of the control gate array
4 Wrong parity in some control RAM location
3 FIFO error
2 PLL alarm
1 UBEX bus data parity error
0 UBEX bus address parity error
LEGEND
Tab. 5.3 Error Codes used by NTW Diagnostics
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(8) SN16 input alarm register
Bit n Meaning
7 Lack of synchronization to the input gate array
6 Lack of clock to the input gate array
5 Generic internal alarm of the input gate array
4 Wrong parity in some control RAM location
3 PCM parity error on some line from LICD
2 PCM parity error on some line from PPXX
1 UBEX bus data parity error
0 UBEX bus address parity error
(10) SN16 output alarm register
Bit n Meaning
7 Lack of synchronization to the input gate array
6 Lack of clock to the input gate array
5 Output block general alarm
4 Wrong parity in some control RAM location
3 Comparison alarm
2 PCM parity error on the internal parallel bus
1 UBEX bus data parity error
0 UBEX bus address parity error
(11) Summarization of some important alarms
Bit n Meaning
7 0
6 0
5 0
4 0
3 Unspecified internal alarm
2 SN: cyclic test alarm
1 UBEX data or address parity error
0 Timing problems
LEGEND
Tab. 5.3 Error Codes used by NTW Diagnostics
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(12) PLLH alarm register description
0x0008 checksum failed
0x0009 fault on DAC or ADC
0x000a phase comparator fault
0x000c generic protocol error
(13) SNAP input alarm register
7 0
6 0
5 Internal timing error/Reroute in matrix error
4 Logic OR of the CRAM data and address parity
error
3 0
2 Parity alarm on one or more of 8Mb PCM input
lines
1 0
0 0
(14) SNAP output alarm register
7 0
6 0
5 Output block general alarm
4 Wrong parity in some control RAM location
3 Comparison alarm
2 Parity alarm on the internal parallel bus
1 0
0 0
(15) Meaning of output diagnostics for SNAP card, in case of failure of phase n.4
4 Bit 0-15: Address that occured when a parity
address or data alarm was detected on UBEX
bus. This word contains a valid data as long as bit
0 or bit 1 of word [0] are set.
LEGEND
Tab. 5.3 Error Codes used by NTW Diagnostics
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5.4.8 PPLD/PPCC Diagnostics
The PPLD is responsible for handling the layer 2 of LAPD protocol. The card is based
on an INTEL CPU 80C186 running at 20 MHZ. The card architecture allows the down-
load of the code.
The MPCC controls, for operating and maintenance purposes, the PPLD via the UBEX;
the TDPC exchanges messages with the PPLD through a 8Mbyte dual port RAM; the
selection of the active copy of the TDPC is under the control of the MPCC.
The LAPD circuit interfaces the switching matrix by means of a duplicated 2Mbit/s link;
up to 8 physical channels can be interfaced both at 64kbit/s and 16kbit/s. An
"n+m"redundancy concept is used for the cards that implement this function.
The PPCC board is responsible for handling the MTP layer 1 and 2 of the Common
Channel Signalling System#7 (CCSS#7) protocol used for signalling on the A interface.
The hardware implementation of the PPCC is the same of the PPLD.
PPXX diagnostics has been implemented with 6 working phases (see paragraph 5.4.2).
a) PPXX diag start phase
This phase checks on NTW outage and TDPC outage, loopback test, CPU reset,
rmware autodiagnose, alarm-forcing test, software load.
OUTPUT if start phase fails:
5 Bit 0-13: Control RAM address location at which
occured a parity alarm on the Speech RAM data
bus
Bit 14-15: Bank of the Speech RAM memory
alarmed. Data contained in this word are valid
only if the bit in position 2 of word [2] is set to 1.
6 Bit 0-13: Control RAM address location at which
occured a parity alarm on the Speech RAM
address bus
Bit 14-15: Bank of the Speech RAM memory
alarmed. Data contained in this word are valid
only if the bit in position 2 of word [2] is set to 1.
7 Bit 0-13: Control RAM address in case the output
gate array detects a data parity alarm on the data
bus of the control RAM itself.
Data contained in this word are valid only if the bit
in position 4 of word [2] is set to 1.
LEGEND
Tab. 5.3 Error Codes used by NTW Diagnostics
word[0] source item(1)
word[1] source code line
word[2] error code(2)
word[3] additional information(3)
word[4] additional information(4)
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b) PPXX diag phase 1
This phase executes memory tests (RAM, TDPC-PPXX DUAM, checksum verica-
tion of EPROM content).
OUTPUT if phase 1 fails for hardware/rmware problems in diagnostic
command execuion:
OUTPUT if phase 1 fails because of unsuccessful answer coming from
PPLD/PPCC software:
c) PPXX diag phase 2
This phase checks the HSCX (PPLD) and the LCS7 (PPCC) channels.
OUTPUT if phase 2 fails:
See previous phase. As relating to the correspondence between the PPLD/PPCC
software internal phases and the diagnostic phases managed by the PPxx hardware
diagnostic routines: hardware diag phase 2 consists of internal phase 3 having the
meaning of checking correct LCS7 (on PPCC) or HSCX (on PPLD) programming.
word[5] additional information(5)
word[6] additional information(6)
word[7] additional information(7).
word[0] error source item (1)
word[1] error line inside source code
word[2] error code (2)
word[3] meaningless (0x0)
word[4] meaningless (0x0)
word[5] meaningless (0x0)
word[6] meaningless (0x0)
word[7] meaningless (0x0)
word[0] error code (2)
word[1] first byte coming from card software (0x13 if OK)
word[2] second byte coming from card software (0x80 if diag failed)
word[3] third byte coming fromcard software (bit mask of failed internal software
phases belonging to range 0-7). The correspondence between the
PPLD/PPCC software internal phases and the diagnostic phases
managed by PPxx hardware diagnostics routines is:
hardware diagnostics phase 1 consists of internal phases 0,1,2 having
the following meaning:
0 --> RAM test
1 --> PPxx_TDPC DUAM test
2 --> EPROM checksum test
word[4] fourth byte coming from card software (bit mask of failed internal soft-
ware phases belonging to range 8-15)
word[5] meaningless (0x0)
word[6] meaningless (0x0)
word[7] meaningless (0x0)
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d) PPXX diag phase 3
This phase performs loopback tests inside EXPI, HCSX test for PPLD or LCS7 test
for PPCC.
OUTPUT if phase 3 fails:
See diag phase 1. As relating to the correspondence between the PPLD/PPCC soft-
ware internal phases and the diagnostic phases managed by the PPxx hardware
diagnostic routines: hardware diag phase 3 consists of internal phases 4 and 5
having the following meaning:
4 --> HSCX (on PPLD) or LCS7 (on PPCC) loopback test
5 --> EXPI (Gate Array) loopback test
e) PPXX diag phase 4
This phase performs the W test on the EXPI loopback register.
OUTPUT if phase 4 fails:
See diag phase 1. As relating to the correspondence between the PPLD/PPCC soft-
ware internal phases and diagnostic phases managed by the PPxx hardware diag-
nostics routines: hardware diag phase 4 consists of internal phase 6 having the
following meaning:
6 --> R/W test on EXPI loopback register
f) PPXX diag phase 5
This phase performs parity alarmforcing, EPROMcompatibility, WDT alarmarising
in the event of missing reset operation, the missing clock alarm forcing and internal
loopback test (checking FIFO queues inside the LCS7 or the HSCX).
OUTPUT if phase 5 fails
See diag phase 1. As relating to the correspondence between the PPLD/PPCC soft-
ware internal phases and diagnostic phases managed by the PPxx hardware diag-
nostics routines: hardware diag phase 5 consists of internal phases 7, 8, 10 having
the following meaning:
7 ----> hardware alarms forcing
8 ----> card/EPROM compatibility
10 --> HSCX internal loopback test
If one or more tests fail, bit mask with notication of unsuccessful internal phases is
inside word [3] for phase 7 and inside word [4] for phases 8 and 10.
g) PPXX diag phase 6
This phase checks on the TDPC side (PPCC/PPLD DUAM) concerning NMI (Non
Maskable Interrupts) and card access test (routine activated by MPCC message).
OUTPUT if phase 6 fails
word[0] 0 - if phase result is good or DUAM problems are detected.
error code if an operating system or tasks communication problem took
place
error code - if an operating system or tasks communication problem
took place
word[1] source code item identifier (see Start Phase) in case of card problem
detected on DUAM side
word[2] source line number
word[3] error code(2) showing PPLD/PPCC fault
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h) PPXX diag end phase
This phase is meaningless.
word[4] meaningless (0x0)
word[5] meaningless (0x0)
word[6] meaningless (0x0)
word[7] meaningless (0x0)
LEGEND
(1) identifier of source item where problem took place
1 DHXXDCCH
2 DHXXDCDE
3 DHXXDCEH
4 DHXXDCSA
5 DHXXDCSM
6 DHXXDCTH
7 DHXXDDDI
8 DHXXDDHD
9 DHXXGSUT
10 DHXXININ
11 DGHDXXDP
(2) error code description
NTW_outage_test 0001h
TDPC_outage_test 0002h
loop_test 00e3h (access to loopback reg.)
00e4h (NMI)
FW_diagnose_test 00e2h (firmware self test failed)
008ah (firmware time out)
alarm_test 00a1h (forcing failed)
00a0h (alarm persists)
SW_load_test 000ch (load failed)
0014h (file system problem)
operating system problems 000ah (mailbox creation failed, null DH answer)
tasks interface problems 000bh (PPxx DH-time-out during load function)
software start 0080h (sw nack answer) or 008ah (sw time out)
Tab. 5.4 Error Codes used by PPxx Diagnostics
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forcing Out Of Service Idle status 008ch (software nack answer) or 008ah (sw time
out)
alarm raising during card access 008ch (time-out expired in command sending)
00a0h (alarm detected during reading operation
of software answer)
problems during command to
card
00a3h (writing error on MPCC-PPXX interface)
0082h (negative software answer, different from
Diag Executed)
0090h (Diag Failed answer inside software
second byte)
loopback test 00e4h if NMI problem
00e3h if card access problem
(3) additional information; in details:
NTW/TDPC outage, operating
system problem, software time-
out, firmware diagnosis failure,
software start/Force
If card access for report is successful:
high byte=parity alarm cause (if any)
low byte=mask of alarms not causing interrupts
OOS failure, load failure If card access for report fails: source code item
(1)
other causes mask of alarms causing interrupts (high byte);
mask of alarms not causing interrupts (low byte)
(4) additional information; in details:
NTW/TDPC outage, operating
system problem, software time-
out, firmware diagnosis failure,
software start/Force OOS failure,
load failure
If card access for report is successful:
high byte = mask of alarms causing interrupts
low byte = circuits enabled to transmit (to NTW) if
card access (for report) fails: source line number
other causes trapped PCM channel address (parity error) (high
byte); control mask of alarms towards UBEX (low
byte)
(5) additional information; in details:
NTW/TDPC outage, operating
system problem, software time-
out, firmware diagnosis failure,
software start/Force OOS failure,
load failure
If card access for report is successful:
high byte = first card control register
low byte = second card control register. If card
access (for report) fails: error code (2)
other causes trapped PCM channel data
LEGEND
Tab. 5.4 Error Codes used by PPxx Diagnostics
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5.4.9 LICD Diagnostics
The LICD is an object that represents the QTLP or STLP line interface boards.
The LICD realizes the interconnection with the PCM30/PCM24 links on the Asub and
Abis interfaces. Submultiplexed time slots coming fromthe BTS and the TRAU must be
extracted and rate adapted to the rate of the switching network and vice versa for
outgoing time slots. An "n+1"redundancy concept is used for the cards that implement
this function.
LICD diagnostics has been implemented with 3 working phases (see paragraph 5.4.2).
a) LICD diag start phase
This phase checks the compatibility of the LICD with the database, executes a test
on PDALARM forcing and some LOOPBACK tests on the card.
OUTPUT if start phase fails:
(6) additional information; in details:
NTW/TDPC outage, operating
system problem, software time-
out, firmware diagnosis failure,
software start/Force OOS failure,
load failure
If card access for report is successful:
high byte = card reset register (0011h no reset in
progress 00efh reset in progress)
low byte = semaphore PPxx -> DH on MPCC
(7) additional information; in details:
firmware diagnosis failure,
software Start/Force OOS failure
Negative firmware autodiagnostic result soft-
ware/firmware negative answer
Unsuccessful software load: Load failure nack cause:
3=Failed
11=No File Found
16=Card Problem
19=Load In Progress
NTW/TDPC outage, operating
system problem, software time-
out
no add info
other causes trapped PCM channel data (parity error)
LEGEND
Tab. 5.4 Error Codes used by PPxx Diagnostics
word[0] error code(1)
word[1..6] 0
word[7] LICD type required by DBA (low byte); physical LICD type really
present (high byte).
1=QTLP V1;
2=QTLP V2
3=STLP
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b) LICD diag phase 1
This phase executes twice the cardcheck rmware command to verify that the card
is working properly.
OUTPUT if phase 1 fails:
The same as start phase.
c) LICD diag phase 2
This phase performs the card reset, test network copy programming and executes
diagnostic checks on the specied card.
OUTPUT if phase 2 fails:
d) LICD diag phase 3
This phase performs card reset, test network copy programming and executes diag-
nostic check on specied card.
OUTPUT if phase 3 fails:
e) LICD diag end phase
This phase is meaningless.
OUTPUT if end phase fails:
word[0] error code(1)
word[1] firmware diagnose report(2)
word[2] firmware diagnose report(2)
word[3] firmware diagnose report(2)
word[4..6] 0
word[7] LICD type required by DBA (low byte);
physical LICD type actually present
(high byte).
1=QTLP V1;
2=QTLP V2
3=STLP
word[0] = error code(1); word[1-6] = 0 if card access fails OR
word[0-3]=FW diagnose repord; word[4-6] = 0
word[7] = as word[7] of phase 0
word[0] error code(1) ALARM REPORT(3)
word[1..6] 0 ALARM REPORT(3)
word[7] 0 ALARM REPORT(3)
word[0] = error code(1) ; word[1-7] = 0 if access card fails OR
word[0-7]= ALARM REPORT(3)
The same as start phase.
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LEGEND
(1) The possible error codes issued by the LICD diagnostic are listed
ERROR CODE MEANING
FFFD parity data alarm is raised
FFFC NMI has occurred
FFFB inconsistent firmware response
FFFA timeout for card response has expired
FFF9 request incompatible with previous set
FFF8 firmware mismatched the command
FFF7 wrong data read from DUAM
FFF6 a reset has occurred
FFF5 card not inserted or fuse burned
FFF4 diagnostic has started
FFF3 stack overflow
FFF2 command not correctly understood
FFF1 queue buffer is full
FFF0 relay fuse burned
FFEF requested reset has not performed
FFED DUAM write/read loop error
FFD8 loopback test failed
FFD7 parity err force not working
(2) Firmware diagnose report
QTLP V1 (bit coded)
word[0] xxxxxxxxxxxxxxxxxy y = 1 means board diagnose failed
word[1] xxxxxxxxxxxxxxxcba a = 1 means RAM1 failed
b = 1 means RAM2 failed
c = 1 means timer0 interrupt problem
word[2] xxxxxxxxxkhqrsvgp p = 1 means diagnose DTIOM0 failed
g = 1 means diagnose DTIOM1 failed
v = 1 means diagnose DTIOM2 failed
s = 1 means diagnose DTIOM3 failed
Tab. 5.5 Error Codes used by LICD Diagnostics
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r = 1 means diagnose DTIOM4 failed
q = 1 means diagnose DTIOM5 failed
h = 1 means diagnose DTIOM6 failed
k = 1 means diagnose DTIOM7 failed
word[3] xxxxxxxxxxxxxxxnm m = 1 diagnostic parity checker
n = 1 diagnostic multiplexer
QTLP V2 (bit coded)
word[0] xxxxxxxxxxxxxxxxxy y = 1 means board diagnose failed
word[1] xxxxxxxxxxedcbxxxa a = 1 means RAM1 failed
b = Internal alarm simulation test
c = MPCC Dual port RAM test
d = Flash EPROM checksum test
e = FPGA (Field Programmable Gate Array)
loopback test
word[2] xxxxxxxxxkhqrsvgp p = 1 line alarm n0 simulation test failed
g = 1 line alarm n1 simulation test failed
v = 1 line alarm n2 simulation test failed
s = 1 line alarm n3 simulation test failed
r = 1 line alarm n4 simulation test failed
q = 1 line alarm n5 simulation test failed
h = 1 line alarm n6 simulation test failed
k = 1 line alarm n7 simulation test failed
word[3] xxxxxxxxxxxxonmxx m = 1 ESCC2 channel n0 test failed
n = 1 ESCC2 channel n1 test failed
o = 1 Watch Dog Timer simulation test failed
STLP (bit coded)
word[0] xxxxxxxxxxxxxxxxxy y = 0 means board ok
y = 1 means board diagnose failed
word[1] xxxxxxxxxxedcbxxxa a = 1 means RAM1 failed
b = Internal alarm simulation(INA) test failed
c = MPCC Dual port RAM test (MDP) failed
d = Flash EPROM checksum test (CKS) failed
e = FPGA (Field Programmable Gate Array)
loopback test failed
LEGEND
Tab. 5.5 Error Codes used by LICD Diagnostics
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word[2] xxxxxxxxxkhqrsvgp p = 1 line alarm n0 simulation test failed
g = 1 line alarm n1 simulation test failed
v = 1 line alarm n2 simulation test failed
s = 1 line alarm n3 simulation test failed
r = 1 line alarm n4 simulation test failed
q = 1 line alarm n5 simulation test failed
h = 1 line alarm n6 simulation test failed
k = 1 line alarm n7 simulation test failed
word[3] xxxxlkji00f0 f = 1 line simulation test failed (line 8)
i = 1 Watch Dog Timer simulation test failed
j = 1 line simulation test failed (line 9)
k = 1 line simulation test failed (line 10)
l = 1 line simulation test failed (line 11)
k = 1 line simulation test failed (line 10)
l = 1 line simulation test failed (line 11)
(3) ALARM REPORT
word[0] xxxxxxxxxxxxxxxxxa a = 1 at least one internal alarm is active
word[1] xxxxxxlkjihgfedcba ab = 0: no alarm;
ab = 2: transient alarm on SN interface;
ab = 3: permanent alarm on SN interface
c = 1 relay power supply off
d = 1 detected parity alarm in read cycle
e = 1 multiplexer alarmed (QTLP V1, V2 only)
h = 1 Queue buffer full (QTLP V1 only)
i = 1 board reset alarm (QTLP V1, V2 only)
j = 1 stack overflow (QTLP V1 only)
k = 1 data parity alarm upon read access on
mpcc dual port (QTLP V1 only)
l = 1 data parity alarm of the FPGA control
memory (QTLP V2 only)
word[2] xxxxxxxxxhgfedcba a-h = alarmed state of lines 0-7
word[3] Not meaningful
LEGEND
Tab. 5.5 Error Codes used by LICD Diagnostics
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5.4.10 DK40 Diagnostics
The copy 0 of DK40 device is used for the change version procedure from BR5.5 to
BR6.0. It provides the following functions:
MPCC interface: it receives the addresses and data busses from the second copy
of the MPCC and selects the signals relevant to the active copy; maintenance
circuitry for fault detection is provided.
Clock processor: it is implemented by a 80C186 microprocessor which acts as co-
processor of the MPCC as fas as it concerns the disk le system functions.
4K words dual port RAM: it provides the intercommunications between the MPCC
and the disk processor.
Winchester Embedded Disk: it implements the mass storage memory.
Synchronous data link for cross-wired connection to opposite copy: it is provided for
maintenance purposes.
The copy 0 of DK40 unit also implements the control of the Alarm Panel circuit (ACKT).
DK40 diagnostic have been implemented with 5 working phases; phase 4 tests of the
DK40 disk (see paragraph 5.4.2).
a) DK40 diag start phase
This phase is defined in order to initialize the hardware. It executes the following
tests:
check of the power on of the card;
verify if the card is in the rack;
test the loop back register;
reset the local microprocessor.
OUTPUT if start phase fails:
word[0] 0x0001 POWER_ON_TEST
word[1] 0x8004 card_not_powered
word[2] MPCC_sense_point_register
word[0] 0x0002 INSERTION_TEST
word[1] 0x8005 card_not_inserted
word[2] MPCC_sense_point_register
word[0] 0x0002 INSERTION_TEST
word[1] 0x8006 NMI_1st_access
word[0] 0x0003 ACCESS_DETECTOR_TEST
word[1] 0xf000 nmi_after_alarm_reset
word[0] 0x0003 ACCESS_DETECTOR_TEST
word[1] 0xf002 nmi_after_sem_lock
word[2] MPCC_sense_point_register
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word[0] 0x0003 ACCESS_DETECTOR_TEST
word[1] 0xf003 sem_not_locked
word[2] maintenance_semaphore_lock_result +
alarm_semaphore_lock_result
word[0] 0x0003 ACCESS_DETECTOR_TEST
word[1] 0x8007 nmi_wr_word1
word[2] MPCC_sense_point_register
word[0] 0x0003 ACCESS_DETECTOR_TEST
word[1] 0x8008 w1_comp_failed
word[2] value written to the PCS loopback
register
word[0] 0x0003 ACCESS_DETECTOR_TEST
word[1] 0x8009 nmi_wr_word0
word[2] MPCC_sense_point_register
word[0] 0x0003 ACCESS_DETECTOR_TEST
word[1] 0x800a w0_comp_failed
word[2] value written to the PCS loopback
register
word[0] 0x0003 ACCESS_DETECTOR_TEST
word[1] 0xf004 sem_not_released
word[2] nmi_after_micro_reset
word[0] 0x0004 MICRO_RESET_TEST
word[1] 0xf004 sem_not_released
word[2] nmi_after_micro_reset
word[0] 0x0004 MICRO_RESET_TEST
word[1] 0x800b nmi_after_micro_reset
word[0] 0x0004 MICRO_RESET_TEST
word[1] 0x800c unsuccessful_micro_reset
word[2] DPR location 03CEh content
word[3] DPR location 03D0h content
word[4] DPR location 03D2h content
word[0] 0x0004 MICRO_RESET_TEST
word[1] 0x800d polling_interrupted
word[2] nmi_after_alarm_reset
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b) DK40 diag phase 1
This phase tests the DK40 internal alarm register to verify that the data and the
addressing parity alarm is correctly recognized.
OUTPUT if phase 1 fails:
c) DK40 diag phase 2
This phase tests the Dual Port RAM.
OUTPUT if phase 2 fails:
word[0] 0x0004 MICRO_RESET_TEST
word[1] 0x800e disk_not_available
word[2] DPR location 03DCh content
word[0] 0x0004 MICRO_RESET_TEST
word[1] 0x800f timeout_expired
word[2] DPR location 03DCh content
word[0] 0x0005 ALARM_REGISTER_TEST
word[1] 0xf000 nmi_after_alarm_reset
word[2] MPCC_sense_point_register
word[0] 0x0005 ALARM_REGISTER_TEST
word[1] 0x8010 no_nmi_after_al_forcing
word[2] MPCC_sense_point_register
word[0] 0x0005 ALARM_REGISTER_TEST
word[1] 0xf001 alarm_not_reset
word[2] DK40 internal alarm register
word[0] 0x0005 ALARM_REGISTER_TEST
word[1] 0x8011 alarm_not_forced
word[2] DK40 internal alarm register
word[0] 0x0006 DPR_TEST
word[1] 0xf002 nmi_after_sem_lock
word[2] MPCC_sense_point_register
word[3] not locked semaphore index
word[0] 0x0006 DPR_TEST
word[1] 0x8012 nmi_wr_idx0
word[2] MPCC_sense_point_register
word[3] DPR offset
word[0] 0x0006 DPR_TEST
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d) DK40 diag phase 3
This phase consists of calling to the internal diagnostics provided by the rmware in
order to test the RAM, the DPR, the SCC and the parity check circuit.
OUTPUT if phase 3 fails:
e) DK40 diag phase 4
This phase consists of calling the internal diagnostics provided by the rmware in
order to test the hard disk.
OUTPUT if phase 4 fails:
word[1] 0x8014 nmi_wr_idx1
word[2] MPCC_sense_point_register
word[3] DPR offset
word[0] 0x0006 DPR_TEST
word[1] 0x8016 nmi_clear_dpr
word[2] MPCC_sense_point_register
word[3] DPR offset
word[0] 0x0006 DPR_TEST
word[1] 0xf004 sem_not_released
word[2] MPCC_sense_point_register
word[0] 0x0006 DPR_TEST
word[1] 0x8013 i0_comp_failed
word[2] DPR offset
word[3] pattern read back from DPR
word[0] 0x0006 DPR_TEST
word[1] 0x8015 i1_comp_failed
word[2] DPR offset
word[3] pattern read back from DPR
word[0] 0x0006 DPR_TEST
word[1] 0x8017 clear_dpr_failed
word[2] DPR offset
word[3] pattern read back from DPR
word[0] 0x0007 FW_TEST
word[1] xxxxxxxxxxxxxxxxxxdcba a = 1 means RAM fault
b = 2means DPR fault
c = 3means SCC fault
d = 4means parity check ckt fault
word[2] DK40 internal alarm
register
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f) DK40 diag phase 5
This phase is dened in order to diagnose the alarm panel interface: it consists of
testing the lamp numbered 8..23 and the lamp numbered 0..7 corresponding to the
relay drivers.
OUTPUT if phase 5 fails:
g) DK40 diag end phase
This phase is meaningless in the DK40 diagnostics.
word[0] 0x0008 DISK_TEST
word[1] xxxxxxxxxxxxxxxxbxxxxa a = 1 means disk fault
b = 1 means disk not ready
word[2] DK40 internal alarm
register
word[0] 0x0009 ALARM_PANEL_TEST
word[1] 0x8018 lamps_not_turned_off
0x8019 set_lamp_failed
0x801a get_lamp_failed
word[2] DK40 internal alarm register
word[3] not working lamp state (high byte) + not
working lamp number
word[4] RELAY_DRIVERS_LAMP_TEST
word[5] 0x8018 lamps_not_turned_off
0x8019 set_lamp_failed
0x801a get_lamp_failed
word[6] DK40 internal alarm register
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LEGEND
TEST-ID VALUE
POWER_ON_TEST 0x0001
INSERTION_TEST 0x0002
ACCESS_DETECTOR_TEST 0x0003
MICRO_RESET_TEST 0x0004
ALARM_REGISTER_TEST 0x0005
DPR_TEST 0x0006
FW_TEST 0x0007
DISK_TEST 0x0008
ALARM_PANEL_TEST 0x0009
RELAY DRIVERS_LAMP_TEST 0x000a
Defines for each phase/test results
card_not_powered 0x8004
card_not_inserted 0x8005
NMI_1st_access 0x8006
nmi_wr_word1 0x8007
w1_comp_failed 0x8008
nmi_wr_word0 0x8009
w0_comp_failed 0x800a
nmi_after_micro_reset 0x800b
unsuccessfull_micro_reset 0x800c
polling_interrupted 0x800d
disk_not_available 0x800e
timeout_expired 0x800f
no_nmi_after_al_forcing 0x8010
alarm_not_forced 0x8011
nmi_wr_idx0 0x8012
i0_comp_failed 0x8013
nmi_wr_idx1 0x8014
i1_comp_failed 0x8015
Tab. 5.6 DK40: Test-id Values
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5.4.11 DISK on MPCC Diagnostics
The disk device realizes the mass storage of the SBS. The disks are housed on and
accessible from the MPCC cards. It is possible, through a flat cable that connects the
two MPCC cards, to access from an MPCC to the disk of the other MPCC.
DISK diagnostic has been implemented with 5 working phases (see paragraph 5.4.2).
a) DISK diag start phase
This phase is meaningless.
b) DISK diag phase 1
This phase veries the disk accessibility. It performs an hardware reset to the disk
unit and waits the result.
OUTPUT if phase 1 fails:
c) DISK diag phase 2
This phase issues to the disk the command that performs the internal diagnostic
tests implemented by the disk itself.
OUTPUT if phase 2 fails:
d) DISK diag phase 3
This phase veries the disk accessibility through the at cable. It performs an hard-
ware reset to the disk unit and waits the result.
OUTPUT if phase 3 fails:
nmi_clear_dpr 0x8016
clear_dpr_failed 0x8017
lamps_not_turned_off 0x8018
set_lamp_failed 0x8019
get_lamp_failed 0x801a
nmi_after_alarm_reset 0xf000
alarm_not_reset 0xf001
nmi_after_sem_lock 0xf002
sem_not_locked 0xf003
sem_not_released 0xf004
LEGEND
Tab. 5.6 DK40: Test-id Values
word[0] Disk status register
word[1] Disk error register
word[0] Disk status register
word[1] Disk error register
word[0] Disk status register
word[1] Disk error register
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e) DISK diag phase 4
This phase issues to the disk (through the at cable) the command that performs the
internal diagnostic tests implemented by the disk itself.
OUTPUT if phase 4 fails:
f) DISK diag phase 5
This phase veries the consistency of the system structures of the File System. If
any inconsistences are found during the check, they will will be removed and the
structures rebuilt.
OUTPUT if phase 5 fails:
g) DISK diag end phase
This phase is meaningless.
During the execution of a disk test, it never occurs that all the above phases are
performed. It depends on MPCC status and if the request diag is for the local or remote
disk. The table below shows in detail which phases are executed in the several condi-
tions.
5.4.12 IXLT Diagnostics
IXLT (Interface X.25 and Local Terminal) allows the MPCC to be connected to the OMC
(by a X.25 protocol) and to the LMT via a proprietary HDLC protocol with V.11 interface.
It implements the following functions:
MPCC interface: it receives the addresses and data busses from the second copy
of the MPCC and select the signals relevant to the active one;
word[0] Disk status register
word[1] Disk error register
word[0] Disk status register
word[1] Disk error register
word[2] Error counter
word[3] Error counter
word[4] Error counter
word[5] Error counter
word[6] Error counter
word[7] Error counter
LOCAL DISK REMOTE DISK,
MPCC HOT_STBY
REMOTE DISK, MPCC in Firmware
Start Start Start
WP 1 WP 1 WP 3
WP 2 WP 2 WP 4
WP 5 WP 3 WP 5
End WP 5 End
End
Tab. 5.7 List of phases that are executed in the several conditions
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8 Kbytes Dual Port Ram: it implements the intercommunications path between the
MPCC and the IXLT;
Two link controllers: they provide level 1 and level 2 both for the OMC and for the
LMT;
The IXLT processor is built around a 386 SX microprocessor, running at 16MHZ, with
3/4/6 Mbyte (depending on the card version) of RAM and 256 kbyte of EPROM (boot-
strap); it is able to handle the full OSI stack.
With BR 5.0 the last version IXLTV6 can be used. It has the following features:
Implements a microprocessor circuit based on CPUIntel 486SXLC-40 running at 20
MHz.
Provides a total of 6 MByte of static ram memory, parity protected, and 512 KByte
of EPROM.
Receives the address and data busses from the second copy of the administrative
processors (MPCC) and selects the signals relevant to the active copy.
Provides a 6 K or 8 K word Dual Port Ram, parity protected, that implements the
intercommunications path between IXLTV6 and the administrative processor
(MPCC).
Allows the administrative processor to reset directly the IXLTV6 processor and
control the V.11 interfaces.
Provides three programmable 16 bit timers.
Allows to handle 8 source of INTR interrupt by a programmable interrupt controller.
Provides 128x16 bit word of serial EPROM to store card identication data.
It implements the following interfaces via two ESCC2:
a 64 Kbit/s embedded in a 2 Mbit line torward the OMC via the MSC
a V.11-X.21 (DTE) link toward OMC via PSPDN
a V.11 (DCE) toward LMT
a V.28 toward a debugger terminal
IXLT diagnostics has been implemented with 4 working phases (see paragraph 5.4.2).
a) IXLT diag start phase
This phase is defined in order to check the card availability. It executes the following
tests:
verify if the card is powered
control if the card is in the rack
OUTPUT if start phase fails:
b) IXLT diag phase 1
This phase tests the address bus with the walking one method and reset of the local
microprocessor.
OUTPUT if phase 1 fails:
word[0] 0x0001 TEST_ID _POWER_ON
word[1] 0x8003 CARD_NOT_POWERED
OR
word[0] 0x0002 TEST_ID _INSERTION
word[1] 0x8004 CARD_ACCESS_FAILED
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c) IXLT diag phase 2
This phase tests the internal alarmregister to verify that the data and the addressing
parity alarms are recognized correctly .
OUTPUT if phase 2 fails:
d) IXLT diag phase 3
This phase tests the entire DPR.
OUTPUT if phase 3 fails:
e) IXLT diag phase 4
This phase call to the internal diagnostic provided by the rmware.
OUTPUT if phase 4 fails:
word[0] 0x0003 TEST_ID_ACCESS_DETECTOR
word[1] 0x8004 CARD_ACCESS_FAILED
OR
word[0] 0x0003 TEST_ID_ACCESS_DETECTOR
word[1] 0x8009 ALARM_NOT_RESET
OR
word[0] 0x0004 TEST_ID_MICRO_RESET
word[1] 0x8005 UNSUCCESSFUL_MICRO_RESET
OR
word[0] 0x0004 TEST_ID_MICRO_RESET
word[1] 0x8007 UNSUCCESSFUL_FW_READY
word[2] IXLT alarm register
word[3] IXLT sense point register
word[4] IXLT loopback register
word[5] IXLT control point register
word[6] IXLT DUAM interrupt register
OR
word[0] 0x0004 TEST_ID_MICRO_RESET
word[1] 0x8006 UNSUCCESSFUL_DUAM_INIT
word[2] IXLT alarm register
word[3] IXLT sense point register
word[4] IXLT loopback register
word[5] IXLT control point register
word[6] IXLT DUAM interrupt register
word[0] 0x0006 TEST_ID_ALARM_REGISTER
word[1] 0x8008 ALARM_NOT_FORCED
word[2] ERR_ALRM
ERR_NONMI
ERR_FORCE
word[0] 0x0005 TEST_ID_DPR
word[1] 0x800a UNSUCCESSFUL_DPR_TEST
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f) IXLT diag end phase
This phase gives a reset to the microprocessor to delete card settings.
word[0] 0x0007 TEST_ID_FW
word[1] 0x800b MBX_ERROR
0x800c MSG_ERROR
0x800d TIMER_ERROR
0x800e TIMEOUT_ERROR
0x800f FW_READY_OK
0x8010 FW_READY_NOK
word[2] IXLT alarm register
word[3] IXLT sense point register
word[4] IXLT loopback register
word[5] IXLT control point register
word[6] IXLT DUAM interrupt register
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LEGEND
TEST-ID VALUE
MDGHD_IXLT 0x0000
TEST_ID_POWER_ON 0x0001
TEST_ID_INSERTION 0x0002
TEST_ID_ACCESS_DETECTOR 0x0003
TEST_ID_MICRO_RESET 0x0004
TEST_ID_DPR 0x0005
TEST_ID_ALARM_REGISTER 0x0006
TEST_ID_FW 0x0007
Defines for each phase/test results
INVALID_CARD_MNEMONIC 0x8000
COPY_OUT_OF_RANGE 0x8001
INVALID_PHASE_NUMBER 0x8002
CARD_NOT_POWERED 0x8003
CARD_ACCESS_FAILED 0x8004
UNSUCCESSFUL_MICRO_RESET 0x8005
UNSUCCESSFUL_DUAM_INIT 0x8006
UNSUCCESSFUL_FW_READY 0x8007
ALARM_NOT_FORCED 0x8008
ALARM_NOT_RESET 0x8009
UNSUCCESSFUL_DPR_TEST 0x800a
MBX_ERROR 0x800b
MSG_ERROR 0x800c
TIMER_ERROR 0x800d
TIMEOUT_ERROR 0x800e
FW_READY_OK 0x800f
FW_READY_NOK 0x8010
Tab. 5.8 IXLT: Test-id Values
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5.4.13 PPCU Diagnostics
The PPCU card is a peripheral processing board which allows the GPRS feature in the
SBS. Its basic functions are channel resource allocation and protocol conversion
between the Abis and the Gb interface.
One BSCcan be equipped with 4 PPCUboard. The boards are subdivided into two pairs
with redundancy 1+1. Each pair of redundant PPCUs identifies a PCU serving an inde-
pendent GPRS area.
The perform-test command is addressed to a PPCU x, where x is the absolute number
of the PPCU: the first two copies refer to the first PCU, the last two to the second one.
The MPCC controls the PPCU via the UBEX, for operating and maintenance purposes;
the TDPC exchanges messages with the PPCU through a 8 Kbyte dual port RAM; the
selection of the active copy of the TDPC is under the control of the MPCC.
One PCU(a couple of 1+1 redounded PPCU) has access to a whole 2 Mb/s flux towards
SN16. This bandwidth, composed of 32 time slots at 64 Kb/s, is shared by the four DSPs
of the ABIC processor (which work on 16 Kb/s time slots connected to the BTS) and by
the GbIC (connected via frame relays at 64 Kb/s to the SGSN). The PPCU under test,
however, and in general the PPCU that is not providing service, is disconnected from
the SN.
PPCU diagnostics have been implemented with 5 working phases (see paragraph
5.4.2). The phases 1, 2, 3 are in effect performed by the PCUC software, but are
requested by the MPCC software via a unique command (MPCC DUAM). The output
result towards MPCC (about 230 bytes) contains the information regarding all these 3
phases. The MPCC diagnostic software splits this information up and formats it for the
output result.
a) PPCU diag start phase
This phase checks NTW outages and TDPC outages, loopback tests, CPU resets,
rmware auto-diagnosis, software loads.
OUTPUT if start phase fails:
word[0] Source item (1)
word[1] Source code line
word[2] Error code (2)
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word[3] Cases:
a) Firmware autodiagnostics failure
(meaning of possible bit values):
0 = test failure of Pentium RAM (64 MB);
1 = test failure of DSP 0 internal RAM (64KB);
2 = test failure of DSP 1 internal RAM (64KB);
3 = test failure of DSP 2 internal RAM (64 KB);
4 = test failure of DSP 2 internal RAM (64 KB);
5 = test failure concerning RAM on Motorola (2MB);
6 = test failure of TDPC-PPCU DUAM)
b) Unsuccessful Start / Force Out of Service Command to
PCUC:
Low byte -> Byte 0 of PCUC answer = 0x36 (Start/Force Out
of Service Code);
High byte -> Byte 1 = 0x2 (unsuccessful)
c) Unsuccessful software executable load: cause of failure
(possible nack causes:
3 = Failed
11 = No File Found
16 = Card Problem
19 = Load In Progress)
d) Unsuccessful patches load: list of possible nack causes:
3 = Failed (patch file probably corrupted)
19 = Another Load In Progress
21 = File System failure
23 = Load Aborted
e) Time out during a MPCC - PCUC command, TDPC
outage and all other causes of error:
UBEX Register "mirror" (stored copy of last written values)
(low byte)
Saved bit mask of PPCU last alarms read on UBEX register (if
any) (high byte)
word[4] Cases: firmware diagnostics failure, unsuccessful Start /
Force Out Of Service command to PCUC:
Byte 2 of PCUC answer (low byte);
Byte 3 of PCUC answer (high byte)
In case of time out during a MPCC - PCUC command, TDPC
outage and all other causes of error:
software semaphore (MPCC -> PCUC) on MPCC-PCUC
DUAM (low byte)
First byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
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b) PPCU diag phase 1
This phase tests the hardware circuitry that can be interfaced by the PCUC. It
performs a read/write check on the TDPC and MPCC DUAM (checks for parity
alarms). It performs a fast access test of the Qspan, (checks for access alarms).
Notice that the phase 3, which checks the GbIC, indirectly performs a test of the
Qspan. The Qspan is the Bus Bridge which allows communication between the
PCUC and the GbIC.
OUTPUT if phase 1 fails:
word[5] Cases: firmware diagnostics failure, unsuccessful Start /
Force Out Of Service command to PCUC:
Byte 4 of PCUC answer (low byte);
Byte 5 (high byte)
In case of time out during a MPCC - PCUC command, TDPC
outage and all other causes of error:
Second byte of PPCU DH command to PPCU Agent on
PCUC (low byte);
Third byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
word[6] Cases: firmware diagnostics failure, unsuccessful Start /
Force Out Of Service command to PCUC:
Byte 6 of PCUC answer (low byte);
Byte 7 (high byte)
In case of time out during a MPCC - PCUC command, TDPC
outage and all other causes of error:
software semaphore (PCUC -> MPCC) on MPCC-PCUC
DUAM (low byte);
first byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
word[7] Cases: firmware diagnostics failure, unsuccessful Start /
Force Out Of Service command to PCUC:
Byte 8 of PCUC answer (low byte);
Byte 9 (high byte)
In case of time out during a MPCC - PCUC command, TDPC
outage and all other causes of error:
Second byte of PPCU Agent answer to PPCU DH on MPCC
(low byte)
Third byte of PPCU Agent answer to PPCU DH on MPCC
(high byte)
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word[0] If a problem was detected by diagnostic test:
Bit mask showing problem area:
00000100 means MPCC DUAM failure;
00001000 means TDPC DUAM failure.
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Source item (high byte) and error code (low byte).
word[1 If a problem was detected by diagnostic test:
Stored copy of last value written on UBEX register (low byte)
and stored copy of last alarms (if any) read on UBEX register
(high byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Source code line
word[2] If a problem was detected by diagnostic test:
software semaphore (MPCC -> PCUC) on MPCC-PCUC
DUAM (low byte)
First byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Stored copy of last value written on UBEX register (low byte)
and stored copy of last alarms (if any) read on UBEX register
(high byte)
word[3] If a problem was detected by diagnostic test:
Second byte of PPCU DH command to PPCU Agent on
PCUC (low byte);
third byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
software semaphore (MPCC -> PCUC) on MPCC-PCUC
DUAM (low byte)
First byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
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c) PPCU diag phase 2
This diagnostic phase checks the AbIC, verifying whether all the DSPs are correctly
sending the communication interrupt to the PCUC.
OUTPUT if phase 2 fails:
word[4] If a problem was detected by diagnostic test:
software semaphore (PCUC -> MPCC) on MPCC-PCUC
DUAM (low byte);
first byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Second byte of PPCU DH command to PPCU Agent on
PCUC (low byte);
third byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
word[5] If a problem was detected by diagnostic test:
Second byte of PPCU Agent answer to PPCU DH on MPCC
(low byte)
Third byte of PPCU Agent answer to PPCU DH on MPCC
(high byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
software semaphore (PCUC -> MPCC) on MPCC-PCUC
DUAM (low byte);
first byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
word[6] If a problem was detected by diagnostic test:
Fourth byte of PPCU Agent answer to PPCU DH on MPCC
(low byte)
Fifth byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Second byte of PPCU Agent answer to PPCU DH on MPCC
(low byte)
Third byte of PPCU Agent answer to PPCU DH on MPCC
(high byte)
word[7] If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Fourth byte of PPCU Agent answer to PPCU DH on MPCC
(low byte)
Fifth byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
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word[0] If a problem was detected by diagnostic test:
Bit mask showing problem area:
00000001 means AbIC failure.
0x0020 means loop test on AbIS interface of DSP processors
failed: more in details, one or more AbIC received some
uncorrect PCU Frames from PLD closed in loop mode.
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Source item (high byte) and error code (low byte).
word[1] If a problem was detected by diagnostic test:
a) if AbIS loop test failed: Bit mask of failed DSP (for example,
0x0005 means DSP-0 (0X01) and DSP-2 (0x04)).
b) otherwise: stored copy of last value written on UBEX
register (low byte) and stored copy of last alarms (if any) read
on UBEX register (high byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Source code line
word[2] If a problem was detected by diagnostic test:
a) if AbIS loop test failed: Bit mask of PDT channels involved
in failure (AbIC-0 -->PDT 0-15)
b) otherwise: software semaphore (MPCC -> PCUC) on
MPCC-PCUC DUAM (low byte)
First byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Stored copy of last value written on UBEX register (low byte)
and stored copy of last alarms (if any) read on UBEX register
(high byte)
word[3] If a problem was detected by diagnostic test:
a) if AbIS loop test failed: Bit mask of PDT channels involved
in failure (AbIC-1 -->PDT 16-31)
b) otherwise: second byte of PPCU DH command to PPCU
Agent on PCUC (low byte);
third byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
software semaphore (MPCC -> PCUC) on MPCC-PCUC
DUAM (low byte)
First byte of PPCU DH command to PPCU Agent on PCUC
(high byte).
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word[4] If a problem was detected by diagnostic test:
a) if AbIS loop test failed: Bit mask of PDT channels involved
in failure (AbIC-2 --> PDT 32-47).
b) otherwise: software semaphore (PCUC -> MPCC) on
MPCC-PCUC DUAM (low byte);
first byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Second byte of PPCU DH command to PPCU Agent on
PCUC (low byte);
third byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
word[5] If a problem was detected by diagnostic test:
a) if AbIS loop test failed: Bit mask of PDT channels involved
in failure (AbIC-3 --> PDT 48-63).
b) otherwise: second byte of PPCU Agent answer to PPCU
DH on MPCC (low byte)
Third byte of PPCU Agent answer to PPCU DH on MPCC
(high byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
software semaphore (PCUC -> MPCC) on MPCC-PCUC
DUAM (low byte);
first byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
word[6] If a problem was detected by diagnostic test:
a) if AbIS loop test failed: word not used
b) otherwise:
Fourth byte of PPCU Agent answer to PPCU DH on MPCC
(low byte)
Fifth byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Second byte of PPCU Agent answer to PPCU DH on MPCC
(low byte)
Third byte of PPCU Agent answer to PPCU DH on MPCC
(high byte)
word[7] a) if AbIS loop test failed: word not used
b) otherwise: If a fault was detected during MPCC-PCUC
interface (concerning hardware or firmware or TDPC-PPCU
DUAM):
Fourth byte of PPCU Agent answer to PPCU DH on MPCC
(low byte)
Fifth byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
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d) PPCU diag phase 3
This phase tests the performance of the GbIC software and obtains the result of the
self-tests that are done by the GbIC software after it has been started by the PCUC.
OUTPUT if phase 3 fails:
word[0] If a problem was detected by diagnostic test:
Bit mask showing problem area:
00000010 means GBIC failure;
00010000 means QSPAN failure.
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Source item (high byte) and error code (low byte).
word[1] If a problem was detected by diagnostic test:
stored copy of last value written on UBEX register (low byte)
and stored copy of last alarms (if any) read on UBEX register
(high byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Source code line
word[2] If a problem was detected by diagnostic test:
software semaphore (MPCC -> PCUC) on MPCC-PCUC
DUAM (low byte)
First byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Stored copy of last value written on UBEX register (low byte)
and stored copy of last alarms (if any) read on UBEX register
(high byte)
word[3] If a problem was detected by diagnostic test:
Second byte of PPCU DH command to PPCU Agent on
PCUC (low byte);
third byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
software semaphore (MPCC -> PCUC) on MPCC-PCUC
DUAM (low byte)
First byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
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e) PPCU diag end phase
The only role of this phase is to put the PPCU in the off-line state. It does not contain
any diagnostic information.
(1) identier of source item where problem took place:
word[4] If a problem was detected by diagnostic test
software semaphore (PCUC -> MPCC) on MPCC-PCUC
DUAM (low byte);
first byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Second byte of PPCU DH command to PPCU Agent on
PCUC (low byte);
third byte of PPCU DH command to PPCU Agent on PCUC
(high byte)
word[5] If a problem was detected by diagnostic test:
Second byte of PPCU Agent answer to PPCU DH on MPCC
(low byte)
Third byte of PPCU Agent answer to PPCU DH on MPCC
(high byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
software semaphore (PCUC -> MPCC) on MPCC-PCUC
DUAM (low byte);
first byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
word[6] If a problem was detected by diagnostic test:
Fourth byte of PPCU Agent answer to PPCU DH on MPCC
(low byte)
Fifth byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Second byte of PPCU Agent answer to PPCU DH on MPCC
(low byte)
Third byte of PPCU Agent answer to PPCU DH on MPCC
(high byte)
word[7] If a fault was detected during MPCC-PCUC interface
(concerning hardware or firmware or TDPC-PPCU DUAM):
Fourth byte of PPCU Agent answer to PPCU DH on MPCC
(low byte)
Fifth byte of PPCU Agent answer to PPCU DH on MPCC (high
byte)
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LEGEND
(1) Identifier of source item where problem occurred
1 DHXXDCCH
2 DHXXDCDE
3 DHXXDCEH
4 DHXXDCSA
5 DHXXDCSM
6 DHXXDCTH
7 DHXXDDDI
8 DHXXDDHD
9 DHXXGSUT
10 DHXXININ
11 DGHDXXDP
12 DHXXDDPU
(2) Error code description
NTW_outage_test: 0001h
TDPC_outage_test: 0002h
Loop_test: 00e3h (access to loopback reg.)
00e4h (NMI)
FW_diagnose_test: 00e2h (diagnosis failed)
008ah (firmware time out)
SW_load_test: 000ch (load failed)
0014h (file system problem)
Operating system problems: 000ah (mailbox creation failed, null DH answer)
Tasks interface problems: 000bh (PPxx DH time-out during load function)
Software start: 0080h (software nack answer) or 008ah (software
time out)
Forcing Out Of Service idle
status:
0081h (software nack answer) or 008ah (software
time out)
Alarm raising during card
access:
008ch (time-out expired in command sending)
00a0h (alarm detected during reading operation of
software answer)
Tab. 5.9 PPCU: Test-id Values
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5.4.14 PPXL Diagnostics (for BSC High Capacity)
The PPXL card is a peripheral processing board, introduced in the BSC to handle all
SS7 and LAPD links. A unique PPXL is able to handle up to 256 links: then one board
can handle all the LAPD (240) and SS7L (8) links. The redundancy approach chosen is
to spread signalling links on both boards having both in service. When both PPXLs are
in service, each of them brings half of the configured LAPDs and SS7Ls.
The PPXL is realised with a standard Intel Pentium processor architecture. The host
processor used is the Mobile PentiumIII feature on-die 256 kbyte L2 cache and the host
bus runs at 100Mhz. The equipment of Pentium III includes the Intel 440BX AGPset,
which consists of the 82443BX Host Bridge Controller (BX) and the 82371AB PCI ISA
IDE Accelerator (PIIX4E). At On the PCI bus is located an HDLC controller (from
CONEXANT) that handles L2 protocol handling manages the LAPD/SS7 links. The
HDLC controller has the capability to handle up to 256 physical channels; up to 240
LAPD can be handled (e.g. 78 channels at 64 kbit/s and 162 channels at 16 kbit/s + 8
SS7 channels). The same bandwidth can be used with a smaller number of channels
but at higher bit rate; the super-channeling is supported in hardware by the HDLC
controller itself, for the LAPD/SS7 application the device is always connected to the
SNAP.
From the MPCC point of view, the hardware/software interface is structured by several
register accessible by PPXL Device Drivers.
Control points:
Active TDPC selection
Active SNAP/PLLH selection
Connection/Disconnection of PCM output from SNAP
Alarm reset
CPU reset
Sense points:
Timing alarm (missing clock from PLLH)
Address parity alarm on UBEX bus
Data parity alarm on UBEX bus
Wrong parity from SNAP
The rest of the 256 byte MPCC DUAM is used for message exchange between the
MPCC software and the PPXL software.
PPXL diagnose has been implemented with 4 working phases (see paragraph 5.4.2).
a) PPXL diag start phase
This phase resets the card checking the result asks the System Download Task to
load it, then verifies that the software answers correctly, check the alarm presence.
OUTPUT if start phase fails:
Word
number
Byte Possible
values
Meaning
word[0] Item
word[1] Line
word[2] Error Code
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b) PPXL diag phase 1
MPCC-PPXU DUAM (the test reads and rewrites each MPCC duam location to
x memory parity errors).
TDPC-PPXU DUAM(the test reads and rewrites each TDPC duamlocation to x
memory parity errors)
OUTPUT if phase 1 fails:
c) PPXL diag phase 2
FPGA loopback
MUSYCC tests
MUSYCC loop
MUSYCC alarms
OUTPUT if phase 2 fails:
word[3] Register 4&7 Dump.
If ErrorCode=0xC, this word contains the
error_cause, defined in sdbaincl (CSD_)
word[4] Register 8&11 Dump
word[5] Register 17&20 Dump
word[6] Register 86&87 Dump
word[7] Register 88&89 Dump
Word
number
Byte Possible
values
Meaning
word
number
byte possible
values
meaning
word[0] low 0x03 MPCC DUAM check failure(writing/reading)
word[0] high
word[0] low 0x05 NMI during MPCC DUAM access
word[0] high bit mask:
0001 0000
0010 0000
0100 0000
1000 0000
Source of NMI:
Transmission conflicts towards SNAP
(DSP/MUSYCC)
Watch dog
Data parity error in read operation from DUAM
Parity error on PCI bus
word[0] low 0x04 TDPC DUAM check failure
word[0] high
word[0] low 0x07 Lack of PCU power (1.8 V)
word[0] high
word[0] low 0x06 NMI during TDPC DUAM access
word[0] high bit mask:
0001 0000
0000 0010
0000 0100
0000 1000
Data parity alarm on bits 0-7(reading operation)
Data parity alarm on bits 8-15
Data parity alarm on bits 16-23
Data parity alarm on bits 24-31
word[1...7] low/high not used not used
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d) PPXL diag end phase
The only role of this phase is to put the PPXL in service.
5.4.15 PPXU Diagnostics
The PPXU card is a peripheral processing board, introduced in the BSC high capacity
to allow the GPRS feature. Its basic functions are channel resource allocation and
protocol conversion between Abis and Gb interface. The redundancy scheme chosen is
load balancing in order to have all boards in service.The perform-test command is
addressed to a PPXU x, where x is the absolute number of PPXU.
The PPXU board is composed of several parts:
The PCUC (PCU Control Processor): it is realised with a standard Intel Pentium
processor architecture. The host processor used is the Mobile PentiumIII running at
either 400 MHz or 500 MHz, depending on the equipped component. The Mobile
Pentium III feature on-die 256 Kbyte L2 cache and the host bus runs at 100 MHz.
The equipment of PentiumIII includes the Intel 440BX AGPset, which consists of the
82443BX Host Bridge Controller (BX) and the 82371AB PCI ISA IDE Accelerator
(PIIX4E). At On the PCI bus is located an HDLC controller that has the capability to
handle up to 256 physical channels but, in GPRS application, a reduced number is
required (max 127; 64 to Abis interface and 63 to Gb interface for each board). The
same bandwidth can be used with a smaller number of channels but at higher bit
rate; the super-channeling is supported in hardware by the HDLC controller itself.
The device, for the GPRS application, is connected to the SNAP.
The ABIC (Abis interface controller): it is composed of 4 DSPs TMS320C5410 from
Texas Instruments, each one with its three integrated serial communication control-
lers. They internally run with a 100 MHz clock, and work together exchanging
packets on Abis. They operate via a DSP controller (PLD UART - Universal Asyn-
chronous Receiver/Transceiver) on ISA bus that on its turn, through the PIIX4
Bridge, can communicate with the PCI bus.
External Telephony and Administration Bus interface: it includes 2 Dual Port RAMs
one with size 8 Kb by 18 bits for data exchange with TDPC, and the other with size
256 bytes by 9 bits for data exchange with MPCC.
word
number
byte possible
values
meaning
word[0] low 0x01 Failure of FPGA loopback access test
word[0] high
word[0] low 0x08 MUSYCC initialization problem
word[0] high S
word[0] low 0x09 Problem during MUSYCCinternal loop
(pattern sending/receiving)
word[0] high
word[0] low 0x0A Presence of SERR alarm
(address parity error) on MUSYCC
word[0] high
word[1...7] low/high not used not used
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The integrated PCI bus interface: it is clocked at 33.3 or 30 MHz and allows commu-
nication among PIIX4, QSpan and MTXC
PPXU diagnose has been implemented with 5 working phases (see paragraph 5.4.2).
a) PPXU diag start phase
This phase resets the card checking the result asks the System Download Task to
load it, then verifies that the software answers correctly, check the alarm presence.
OUTPUT if start phase fails:
b) PPXU diag phase 1
CPU power (the test veries 1.8 V voltage)
MPCC-PPXU DUAM (the test reads and rewrites each MPCC duam location to
x memory parity errors).
TDPC-PPXU DUAM(the test reads and rewrites each TDPC duamlocation to x
memory parity errors).
OUTPUT if phase 1 fails:
Word
number
Byte Possible
values
Meaning
word[0] Item
word[1] Line
word[2] Error Code
word[3] Register 4&7 Dump.
If ErrorCode=0xC, this word contains the
error_cause, defined in sdbaincl (CSD_)
word[4] Register 8&11 Dump
word[5] Register 17&20 Dump
word[6] Register 86&87 Dump
word[7] Register 88&89 Dump
Word
number
Byte Possible
values
Meaning
0 low 0x07 CPU power lack (1.8V)
0 high -
0 low 0x03 MPCC DUAM check failure (writing/reading)
0 high -
0 low 0x05 NMI during MPCC DUAM access
0 high bit mask:
0001 0000
0010 0000
0100 0000
1000 0000
sources of NMI
Transmission conflicts towards SNAP
(DSP/MUSYCC)
Watch Dog
data parity error in read operation from DUAM
parity error on PCI Bus
0 low 0x04 TDPC DUAM check failure
0 high -
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possible specic problems (rst add info in test report); see Tab. 5.10.
c) PPXU diag phase 2
FPGA loopback
MUSYCC tests
MUSYCC loop
MUSYCC alarms
OUTPUT if phase 2 fails:
possible specic problems (rst add info in test report); see Tab. 5.10.
d) PPXU diag phase 3
MUNICH internal loop
MUNICH - DSP loop
MUNICH - FPGA loop
OUTPUT if phase 3 fails:
0 low 0x06 NMI during TDPC DUAM access
0 high bit mask:
0000 0001
0000 0010
0000 0100
0000 1000
Data parity alarm on bits 0-7 (reading operation)
Data parity alarm on bits 8-15 (reading)
Data parity alarm on bits 16-23 (reading)
Data parity alarm on bits 24-31 (reading)
1..7 low /
high
Not used Not used
Word
number
Byte Possible
values
Meaning
Word
number
Byte Possible
values
Meaning
0 low 0x01 Failure pf FPGA loopback access test
0 high -
0 low 0x08 MUSYCC Initialization problem
0 high -
0 low 0x09 Problem during MUSYCC internal loop
(patterns sending/receiving)
0 high -
0 low 0x0A Presence of SERR alarm (address parity error)
on MUSYCC
0 high -
1..7 low /
high
Not used Not used
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Word
number
Byte Possible values Meaning
0 low 0x20 MUNICH Initialization problem during
internal MUNICH loop or MUNICH-DSP
loop
1 high/
low
Range 0x000 -
0xFFFF
Number of source code line
2 low 0x00
0x01
0x02
0x03
Uncorrect input argument of MUNICH Init
routine
MUNICH reset failure
Port configuration failure
Channel Init failure
0 low 0x23 Failure during MUNICH internal loop
test
0 high - Number of faulted channels
1 low - -
1 high - -
2 low - -
2 l high - -
3 low - -
3 high - -
4 low Bit mask 0000 0001--> problem on channel 0
0000 0010 --> problem on channel 1
0000 0100 --> problem on channel 2
................................
1000 0000 --> problem on channel 7
4 high Bit mask 0000 0001--> problem on channel 8
0000 0010 --> problem on channel 9
0000 0100 --> problem on channel 10
................................
1000 0000 --> problem on channel 15
5 low Bit mask 0000 0001--> problem on channel 16
0000 0010 --> problem on channel 17
0000 0100 --> problem on channelel 18
................................
1000 0000 --> problem on channel 23
5 high Bit mask 0000 0001--> problem on channel 24
0000 0010 --> problem on channel 25
0000 0100 --> problem on channel 26
................................
1000 0000 --> problem on channel 31
6 low bit mask 0000 0001--> problem on channel 32
0000 0010 --> problem on channel 33
0000 0100 --> problem on channel 34
................................
1000 0000 --> problem on channel 39
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6 high bit mask 0000 0001--> problem on channel 40
0000 0010 --> problem on channel 41
0000 0100 --> problem on channel 42
................................
1000 0000 --> problem on channel 47
7 low bit mask 0000 0001--> problem on channel 48
0000 0010 --> problem on channel 49
0000 0100 --> problem on channel 50
................................
1000 0000 --> problem on channel 55
7 high bit mask 0000 0001--> problem on channel 56
0000 0010 --> problem on channel 57
0000 0100 --> problem on channel 58
................................
1000 0000 --> problem on channel 63
NOTE:
Other information (if any) about channels
problems are reported inside System Info
report issued by PPXU Device Handler
on MPCC (info id=... and originator=...)
0 low 0x25 Failure of DSP setting to MUNICH-DSP
loop mode (case a) or: failure of
MUNICH-DSP loop test (case b)
0 high Case a:
2->DSP
address=0x8002
4->DSP
address=0x8004
Case a: Location where an uncorrect
value was read
Case b: 0xFF (meaningless)
1 High/
low
Range 0x000xFFFF Cases a, b: number of source code line
2 low Case a: bit mask
0000 0001 DSP-0
0000 0010 DSP-1
0000 0100 DSP-2
0000 1000 DSP-3
Case b:
range 1-256
Case a: Faulty DSP during loop setting
Case b: number of faulty channels
2 high not used not used
Word
number
Byte Possible values Meaning
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3 low bit mask:
0000 0001 AbIC-0
0000 0010 AbIC-1
0000 0100 AbIC-2
0000 1000 AbIC-3
0001 0000 AbIC-4
0010 0000 AbIC-5
0100 0000 AbIC-6
1000 0000 AbIC-7
Case a: Faulty AbIC (DSP cores) during
loop setting
Case b: not used
3 high bit mask:
0000 0001 AbIC-8
0000 0010 AbIC-9
0000 0100 AbIC-10
0000 1000 AbIC-11
0001 0000 AbIC-12
0010 0000 AbIC-13
0100 0000 AbIC-14
1000 0000 AbIC-15
4 high/
low
Case a: value read on AbIC-0
Case b: bit mask of faulty channels (0-15)
5 high/
low
Case a: value read on AbIC-1
Case b: bit mask of faulty channels (16-
31)
6 high/
low
Case a: value read on AbIC-2
Case b: bit mask of faulty channels (32-
47)
7 high/
low
Case a: value read on AbIC-3
Case b: bit mask of faulty channels (48-
63)
NOTE:
Other information (if any) about channels
problems are reported inside System Info
Report issued by PPXU Device Handler
on MPCC (info id=... and originator=...)
0 low 0x26 Failure of DSP setting to MUNICH-
FPGA loop mode (case a) or:
failure of MUNICH-FPGA loop test
(case b)
0 high Case a:
2--> DSP
address=0x8002
4--> DSP
address=0x8004
Case a: Location where an uncorrect
value was read
Case b: 0xFF (meaningless)
1 low /
high
Range 0x00-0xFFF Cases a,b:Number of souce code line
Word
number
Byte Possible values Meaning
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possible specic problems (rst add info in test report); see Tab. 5.10.
2 low Case a:
Bit mask:
0000 0001 DSP-0
0000 0010 DSP-1
0000 0100 DSP-2
0000 1000 DSP-3
Case b:
range 1-256
Case a: Faulty DSP during loop setting
Case b: number of fauty channels
2 high not used not used
3 low Bit mask:
0000 0001 AbIC-0
0000 0010 AbIC-1
0000 0100 AbIC-2
0000 1000 AbIC-3
0001 0000 AbIC-4
0010 0000 AbIC-5
0100 0000 AbIC-6
1000 0000 AbIC-7
Case a: Faulty AbIC (DSP cores) during
loop setting
Case b: not used
3 high Bit mask:
0000 0001 AbIC-8
0000 0010 AbIC-9
0000 0100 AbIC-10
0000 1000 AbIC-11
0001 0000 AbIC-12
0010 0000 AbIC-13
0100 0000 AbIC-14
1000 0000 AbIC-15
Case a: Faulty AbIC (DSP cores) during
loop setting
Case b: not used
4 low /
high
Case a: Value read on AbIC-0
Case b: bit mask of faulty channels (0-15)
5 low /
high
Case a: Value read on AbIC-1
Case b: bit mask of faulty channels (16-
31)
6 low /
high
Case a: Value read on AbIC-2
Case b: bit mask of faulty channels (32-
47)
7 low /
high
Case a: Value read on AbIC-3
Case b: bit mask of faulty channels (48-
63)
NOTE:
Other information (if any) about channels
problems are reported inside System Info
Report issued by PPXU Device Handler
on MPCC (info id=... and originator=...)
Word
number
Byte Possible values Meaning
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e) PPXU diag end phase
The only role of this phase is to put the PPXU in service.
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5.4.16 CPEX Diagnostics
The CPEX card replaces DK40 (LEDalarmpanel handling board) in the BSC_120 chan-
nels rack. The disk functionality is on the MPCC board since BR 6.0.
The CPEX (Control Panel and External alarms device) is redundant 1+1.
The diagnostic has two phases, which performs respectively the alarm-forcing test for
all fault detectors of the CPEX card, fan and the ENVA. Beside thiese, the start phase
(i.e. the phase 0)tests the accessibility of the CPEX and the absence of card alarms.
a) CPEX diag start phase
This phase checks the card presence and the loop back register and force the CPEX
card alarm registers.
OUTPUT if start phase fails:
LEGEND
(1) Possible specific problems
PPXUAGDC_NMI_MPCC_DUAM_ERR 0x05 (NMI during access to DUAM)
PPXUAGDC_MPCC_DUAM_ERR 0x03 (error in writing/reading DUAM)
PPXUAGDC_NMI_TDPC_DUAM_ERR_
DUAM
0x06 (NMI during access to TDPC-PPXU)
PPXUAGDC_TDPC_DUAM_ERR 0x04 (error in writing/reading DUAM)
PPXUAGDC_FPGA_LOOPB_ERR 0x01
PPXUAGDC_MUSYCC_LOOP_ERR 0x09
PPXUAGDC_MUSYCC_ALARM_ERR 0x0A
PPXUAGDC_MUNICH_INIT_ERR 0x20 (MUNICH Init problems)
PPXUAGDC_MUNICH_DIAG_ERR 0x23 (internal loop problems)
PPXUAGDC_MUNICH_INIT_ERR 0x20
PPXUAGDC_DSP_LOOP_ERR 0x25 (loop problems)
PPXUAGDC_DSP_FPGA_LOOP_ERR 0x26
PPXUAGDC_CPU_POWER_ERR 0X07 (CPU power lack)
PPXUAGDC_MUSYCC_INT_ERR 0x08 (MUSYCC Init problems)
Tab. 5.10 PPXU: Test-id Values
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b) CPEX diag phase 1 (WP1)
Fan alarm register test
OUTPUT if phase 1 fails:
c) CPEX diag phase 2 (WP2)
ANVA alarm register.
OUTPUT if phase 2 fails:
Word
number
Byte Possible values Meaning
word[0] 0001h CPEX access test
word[1] axxxxxxx a=0
a=1
loop test failed
Card_Alarm_Regis
ter
word[2] abcdefgh a=data parity alarm 0-7 1=on
b=fixed to 0
c=address parity alarm lines 0-7 1=on
d=address parity alarm lines 8-15 1=on
e=global alarm of the MPCC 0=on
f=data parity alarm 8-15 1=on
g=CLK 2m alarm 1=on
h=voltage sense monitor 0=on
this word is mean-
ingful only if word 0
is 1
Word
number
Byte Possible values Meaning
word[0] 0002h Fan_Force_Alarm
_Test
word[1] abxcxxxxx a=major fan alarm
b=minor fan alarm
c=fan box presence
lFan_Alarm_
Register dump
word[2] abcdefgh a=data parity alarm 0-7 1=on
b=fixed to 0
c=address parity alarm lines 0-7 1=on
d=address parity alarm lines 8-15 1=on
e=global alarm of the MPCC 0=on
f=data parity alarm 8-15 1=on
g=CLK 2m alarm 1=on
h=voltage sense monitor 0=on
this word is
meaningful only if
word 0 is 1
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d) CPEX diag end phase
This phase is meaningless.
Word
number
Byte Possible values Meaning
word[0] 0003h ENVA_
Force_
Alarm_
Test
word[1] abcdefghijklmnop a=expansion alarm 0
b=expansion alarm 1
c=expansion alarm 2
d=expansion alarm 3
e=expansion alarm 4
f=expansion alarm 5
g=expansion alarm 6
h=expansion alarm 7
i=expansion alarm 8
j=expansion alarm 9
k=expansion alarm 10
l=expansion alarm 11
l=expansion alarm 12
m=expansion alarm 13
n=expansion alarm14
o=expansion alarm 15
lENVA_
Alarm_
Register
dump
word[2] abcdefgh a=data parity alarm 0-7 1=on
b=fixed to 0
c=address parity alarm lines 0-7 1=on
d=address parity alarm lines 8-15 1=on
e=global alarm of the MPCC 0=on
f=data parity alarm 8-15 1=on
g=CLK 2m alarm 1=on
h=voltage sense monitor 0=on
this word is
meaningful
only if word
0 is 1
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LEGEND
(1) Possible specific problems
PPXUAGDC_NMI_MPCC_DU
AM_ERR
0x05 (NMI during access to DUAM)
PPXUAGDC_MPCC_DUAM_E
RR
0x03 (error in writing/reading DUAM)
PPXUAGDC_NMI_TDPC_DU
AM_ERR_DUAM
0x06 (NMI during access to TDPC-PPXU)
PPXUAGDC_TDPC_DUAM_E
RR
0x04 (error in writing/reading DUAM)
PPXUAGDC_FPGA_LOOPB_
ERR
0x01
PPXUAGDC_MUSYCC_LOOP
_ERR
0x09
PPXUAGDC_MUSYCC_ALAR
M_ERR
0x0A
PPXUAGDC_MUNICH_INIT_E
RR
0x20 (MUNICH Init problems)
PPXUAGDC_MUNICH_DIAG_
ERR
0x23 (internal loop problems)
PPXUAGDC_MUNICH_INIT_E
RR
0x20
PPXUAGDC_DSP_LOOP_ER
R
0x25 (loop problems)
PPXUAGDC_DSP_FPGA_LO
OP_ERR
0x26
PPXUAGDC_CPU_POWER_E
RR
0X07 (CPU power lack)
PPXUAGDC_MUSYCC_INT_E
RR
0x08 (MUSYCC Init problems)
Tab. 5.11 PPXU: Test-id Values
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5.5 NACK CAUSES
- unsuccessful wrong meid the objects addressed are not correct.
- object not equipped the MOT is not created.
- other tests running maximumnumber of tests are already queued
or running. No more tests are acceptable.
- MOTS_NOT_LOCKED the MOT is not locked.
The following are the nack causes directly reported by DH:
- T_Resource_Currently_Busy
- T_Invalid_Command_Parms
- Unsuccessful_Ntv_Outage
- Unsuccessful_Object_Notequipped
- Unsuccessful_Invalid_Status
- Unsuccessful_Power_Off
- Unsuccessful_Other_Copy_Powered_Down
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6 Abbreviations
ACTM ACT for the Base Rack/Shelter
BSS Base Station System
BTS Base Transceiver Station ,
BTSE Base Transceiver Station Equipment
CPEX Control Panel and External alarms device
CPEX Control Panel Expansion
DH Device Handler
DISK physic disk
DK40 Led Alarm Panel Control
DUKIT Duplex Combiner Kit
EMI Electro Magnetic Interference
ESD Electrostatic Sensitive Device
GSM Global Systemfor Mobile Communications
HMOI Hardware Managed Object
HW Hard Ware
HW Hardware
ITMN Installation & Test Manual
IXLT Interface X.25 and Local Terminal Interface
,
LAPD Link Access Procedure on the D-Channel
LED Light Emitting Diode
LICD Line Card
LICDS Line Card Spare
LMT Local Maintenance Terminal
MEMT Memory of Telephone Processor
MOT Managed Object Under Test
MPCC Main Processor Control Circuit
N No
nob-RIU Not On Board Remote Inventory Unit , , , ,
, , , , , , , , , , , ,
NTW Network
ob_RIU On Board Remote Inventory Unit
OMC Operation and Maintenance Center ,
OS Operating System
PCM Pulse Code Modulation
PLLH Phase Locked Loop Oscillator High Perfor-
mance
PLMN Public Land Mobile Network
PPCC Peripheral Processor Common Channel
PPCU Peripheral packet Control Unit
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PPLD Peripheral Processor LAPD
PPXL Peripheral processor LAPD/SS7
PPXU Peripheral processor used at PPCU evolu-
tion
PPXX Peripheral Processor (general purpose)
PWRD Power Distributor
QTLP Quad Trunk Line Peripheral
RC Radio Commander
SBS Siemens Base Station
SN16 Switching Network at 16 Kbit/s
SNAPSwitching Network Advanced Performance
SS7 CCITT Common Channel Signalling No.7
STLP Super Trunk Line Peripheral
SW Software
SYNC Synchronization Source
SYNE External Synchronization Source
TAC Technical Assistance Center
TDPC Telephony and Distributor Processor Circuit
TRAU Transcoder and Rate Adaption Unit
UBEX Universal Bus Extender
Y Yes