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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO.

9, SEPTEMBER 2008 3249


Power-Conditioning Circuitry for a Self-Powered
System Based on Micro PZT Generators in a
0.13-m Low-Voltage Low-Power Technology
Jordi Colomer-Farrarons, Student Member, IEEE, Pere Miribel-Catal, Member, IEEE,
Albert Saiz-Vela, Student Member, IEEE, Manel Puig-Vidal, Member, IEEE, and
Josep Samitier, Member, IEEE
AbstractThe concept and design of a power-conditioning cir-
cuit for an autonomous low-power System-in-Package (SiP) is
presented in this paper. The SiPs main power source is based on
the use of micropiezoelectric generators. The electrical model of
the power source, which has been obtained based on experimen-
tal measurements and implemented on Cadence Analog Artists
Spectre simulation environment, is explained. The model has been
used to simulate the power source with the power-conditioning
electronics over the entire design process. Finally, the simulated
and experimental results of the developed integrated power cir-
cuits, which are formed by a rectier and a low-power bandgap
reference voltage source to dene the threshold voltage for the
closed-loop regulation process, are also shown. These circuits have
been designed using a commercial 0.13-m technology from ST
Microelectronics through the Multi-Projects Circuits (CMP) Tech-
niques of Informatics and Microelectronics for Integrated Systems
Architecture (TIMA) service.
Index TermsElectric power generation, energy scavenging,
low-power electronics, power conditioning, vibrations.
I. INTRODUCTION
N
OWADAYS, there is an enormous interest in renewable
energy sources and their applications, particularly for
high power levels [1][3]. There is also an increasing interest in
using free available external energy sources for powering small
electronic systems, a process known as energy harvesting [4].
However, the amount of energy that can be obtained from these
external ambient sources like vibrations, heat, light, radio waves
[5][8], or from human activity [9], [10] is limited regarding
power-consumption levels.
Some already published works show the design of self-
powered systems based on microelectromechanical-system
(MEMS) micropower sources like electromagnetic micropower
MEMS generators [11], [12], variable capacitors [13], piezo-
electric (PZT)-based generators [14], or dening completely an
integrated sensor node [15]. Examples of this technologies are
the design of self-powered wireless networks [16] formed by
distributed sensors which are capable of monitoring the real-
time condition of motors, turbines, pumps, and gear boxes and
the design of heating or ventilation control systems for burglar
Manuscript received February 28, 2008; revised June 17, 2008. First pub-
lished July 9, 2008; last published August 29, 2008 (projected).
The authors are with the Systems for Instrumentation and Communications
Laboratory (SIC), Electronics Department, Universitat de Barcelona, 08028
Barcelona, Spain (e-mail: jcolomer@el.ub.es).
Digital Object Identier 10.1109/TIE.2008.927973
alarms. One of the most interesting elds where this technology
is being applied is biology, where self-powered RF-ID tags can
monitor the working temperature on ultrahigh bands [18], [19]
or check animals healthcare [20], [21]. Finally, self-powered
commercial devices have been developed using the harvesting
approach like the Seiko Kinetic wristwatch [22] or a smart
tennis racquet [23].
The continuous advances in the semiconductors integration
technology related to the reduction of the transistors size
allow the industry to develop these new self-powered portable
electronic devices which usually include in their System-in-
Package (SiP) or System-on-Chip (SoC) a great variety of
circuitry and functions like wireless sensor networks or bio-
medical electrical instrumentation. However, the main problem
with these new devices resides in the power-supply system,
which is usually based on a typical bulky battery solution often
with much larger size than the SiP or SoC itself.
The size, width, nite-energy lifetime, and battery replace-
ment are important drawbacks for those small and portable
applications that need long-lifetime energy-supply systems
[24][26]. Therefore, novel and innovative energy-supply al-
ternatives must be explored to remove or replace the battery
dependence and make feasible the deployment of these free-
battery-dependence devices. Focusing on this eld, a new trend
in the research of energy sources for low-power applications
has grown rapidly in recent years. This approach consists of
harvesting the available energy of the environment in order to
supply enough power to the electronic applications instead of
using a battery or other technologies with short lifetime and
nite amount of energy.
This paper is focused on the development of a real power-
supply system based on the scavenged energy from mechanical
vibrations [27]. The idea is to avoid the use of any standard
battery and just work with the energy provided by the vibrations
of PZT materials. The developed power-supply system will be
the main part of the power-management circuitry of a self-
powered microsensor network which is still being designed.
The structure of this paper is the following. In Section II, the
conception of the full system is presented. Section III shows the
electrical model of the PZT generator. The designed integrated
circuits that dene the whole system (formed by a rectier, a
bandgap circuit, and control unit) are described in Section IV.
Finally, Section V presents the simulated and experimental
results of the power-conditioning circuitry.
0278-0046/$25.00 2008 IEEE
3250 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 9, SEPTEMBER 2008
Fig. 1. Proposed self-powered SiP.
Fig. 2. Performance of the presented PCC.
II. CONCEPT OF THE SIP SYSTEM
The proposed whole system (see Fig. 1) is conceived as a
SiP, where sensors, interface electronics, processing, wireless
communications, and power systems are combined inside the
same package. However, the presented work in this paper is
focused on the development of the SiPs power-supply system.
The input energy source is based on a PZT microgenerator
which supplies an ac voltage. This ac signal must be rectied,
and the obtained dc signal, with some ripple, is used to drive a
supercapacitor (SCapa).
A logic circuitry (control unit, Fig. 1) based on several
comparators senses the voltage at the SCapa and denes two
trigger values (V
max
out
and V
min
out
) in order to control two PMOS
switching transistors. One PMOS switch is used to control the
power delivered to the interface and processing electronics,
whereas the other one is used to control the power delivered
to the RF circuitry.
After the charging phase, when the voltage value at the
SCapa raises to the regulated value of V
max
out
provided by the
rectier, a control signal is generated to switch-on the PMOS
transistors in order to start a discharge process (discharging
phase) over the SCapa. When the voltage decreases down to
V
min
out
, the switching transistors are switched-off, nishing the
discharging phase. Note that V
min
out
is dened by the minimum
suitable voltage to ensure the right performance of the load
electronics that would be used.
Once nished with the described chargedischarge cycle, the
SCapa is charged again to the dened V
max
out
(recharging phase)
as it is shown in Fig. 2. Furthermore, both trigger values, V
max
out
and V
min
out
, could be dened by the control unit, as it is presented
in Section IV.
III. ELECTRICAL MODEL OF THE PZT POWER SOURCE
A. Simple PZT Model
The used PZT generator is based on the Quick Pack QP20W
(Mid Technology Corporation, Medford, MA, USA). The
Quick Pack QP20W [28] is a composite beam made of two
PZT layers working as a bimorph body, with an intermediate
layer based on polyimide. This composite beam is then located
with one end clamped to a vibrating body and the other end
remaining free. The vibrations forced at the clamped end are
propagated along the cantilever beam. This wave generates
an induced strain in the membrane, which at the same time
produces an electrical charge.
A lumped electrical model compatible with Spectre software
has been developed to validate the conception of the power-
conditioning-circuit (PCC) integrated circuit. The model is
based on the modal analysis of PZT EulerBernoulli beam
equations [29]. Solving the beam equation for the rst res-
onance mode and considering the equivalences between the
equations dening a mechanical system and the equations
COLOMER-FARRARONS et al.: POWER-CONDITIONING CIRCUITRY FOR A SELF-POWERED SYSTEM 3251
Fig. 3. QP20W experimental-setup model identication and validation.
dening an electrical circuit, then an electromechanical equiv-
alent circuit is proposed. All the electrical components that
appear in the equivalent circuit have been dened by means
of the beam geometrical and material parameters. Due to the
composite nature of the material, some of these parameters are
experimentally identied. The experimental setup for model
identication and model validation is shown in Fig. 3. The
transducer is mounted and clamped over an electromagnetic vi-
bration shaker ET-132 from Labworks Inc. The shaker is driven
with a specic amplier Pa-119 from Labworks Inc., with the
command signals coming from a function generator. For the
displacement measurements, a triangulation laser LC2440 from
Keyence is used. A model of the PZT is shown in Fig. 4.
B. Array of PZT Model
In order to increase the current capability of the power
source, different PZT have been used at the same time. This new
power-source structure uses in parallel different PZTs, allowing
the system to obtain a higher current. The idea is shown in
Fig. 1. Different simple PZT generators are connected in par-
allel, creating an array of generators, assuming, at rst glance,
that all of the PZT generators are synchronized and vibrating
at the same frequency. This array is then connected to the
power-conditioning circuitry to load the SCapa. This topology
allows us to use one or several PZT generators, increasing or
decreasing the total amount of current generated by the PZTs.
Moreover, the use of several PZT generators in a parallel
conguration decreases the required charging time of the SCapa
at the initial start-up instant. The fall of the charging time is
shown in the simulation of Fig. 5, where different charging
times for different arrays of PZT generators at the 100-F
capacitor are shown. Waveform Vldo9 shows the charging time
for an array composed by nine simple GP20W generators.
Fig. 4. (a) PZT model. (b) PZT symbol.
Waveform Vldo3 represents the time involved in the charge for
an array of three elements, whereas waveform Vldo1 represents
the time for a single PZT generator.
It is important to remark that the simulation shown in Fig. 5
has been carried out with a capacitive element which is not
exactly the one used in the SiP. This simulation has just been
performed to show how the use of an array of PZT can reduce
the charging time of the SCapa. It can also be noticed that
there is not a perfect additive current effect. Table I summarizes
the most important features of the three situations simulated
using different arrays of PZT generators vibrating with an
acceleration of 7 m/s
2
at 80 Hz, which is the frequency used
for the experimental validation presented in Section V.
With this acceleration value, the PZT open-circuit voltage
(V
oc
) is equal to 2.5 V. The working principle of the PCC
(control unit) is based in achieving the maximum PZT trans-
ducer efciency [30], which is dened by
V
co
= V
oc
/2 (1)
where V
co
is the rectied voltage with the generators connected
to the circuit. All these voltages are peak values.
IV. POWER-CONDITIONING CIRCUITRY
The power-conditioning circuitry combines three main cir-
cuits: an integrated rectier, which is needed to rectify the
ac signal coming from the PZT source; a voltage bandgap
reference circuit, which is used to dene a reference voltage;
and a control unit.
A. Rectier Circuits
Since the PZT generator supplies an ac voltage, a rectica-
tion stage is needed. Two different rectiers [31], [32] based
on the diode-bridge conguration have been tested (see Fig. 6).
Vin
+
Vin

is the generated ac signal that has to be rectied,


and V
SCapa
is the dc voltage at the SCapa (see Fig. 1). The
rst rectier is based on NMOS transistors [Fig. 4(a)] and
the second one based on PMOS transistors [Fig. 4(b)]. From
simulated results, it can be demonstrated that the efciency of
both architectures is around 70%. However, the PMOS rectier
presents a better behavior with an efciency near 72%. In spite
of this better efciency, the NMOS rectier has been selected
due to its reduced size. The PMOS rectier is ten times larger
than the NMOS rectier.
B. Bandgap Circuit
In order to avoid the use of bipolar transistors [35], [36], the
proposed bandgap circuit is based on a full MOSFET bandgap
3252 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 9, SEPTEMBER 2008
Fig. 5. SCapa initial charging time for different arrays of PZT.
TABLE I
ARRAY OF PZT FEATURES
Fig. 6. Integrated rectiers. (a) NMOS. (b) PMOS.
Fig. 7. Schematic of the bandgap circuit.
architecture [33], [34]. A solution using bipolar transistors is
not possible because these transistor types are not available in
the integration technology used to design and manufacture the
circuits. The full MOSFET bandgap architecture [37] is shown
in Fig. 7.
Fig. 8. Bandgap temperature response.
It consists of a self-biased peaking current source (CS) [38],
[39] with a series resistor. M3 and M4 transistors, and R1
resistor, form the peaking reference CS. The transistors work
in the subthreshold region. M4 transistor is designed such that
I
D4
is at its peaking value. The design condition is dened by
I
D3
R
1
= NV
T
. (2)
Then, it can be demonstrated [2] that the relationship be-
tween I
D3
and I
D4
, if the last condition is satised, is
I
D4
= I
D3
K
4
K
3
e
1
(3)
where K
3
= W
3
/L
3
and K
4
= W
4
/L
4
.
Owing to the current mirror, the condition I
D3
= I
D4
is
achieved, and then, the relationship between K
3
and K
4
to
satisfy the last condition is K
4
/K
3
= e. If this ration is dened
between the transistors, the peaking condition is maintained.
COLOMER-FARRARONS et al.: POWER-CONDITIONING CIRCUITRY FOR A SELF-POWERED SYSTEM 3253
Fig. 9. Examples of bandgap Monte Carlo simulations at 22

C and 65

C.
The currents are proportional to the absolute temperature
(PTAT). Then, the voltage drop in R1 is PTAT. The bandgap
reference voltage (BG) is dened by
BG =
R
2
R
1
NV
T
+V
GS3
. (4)
With the right ratio between R2 and R1, it is possible to
compensate the variations with the temperature of V
GS3
.
Several simulations have been carried out obtaining a nomi-
nal value for the reference voltage of 465 mV. The temperature
coefcient is 100 ppm/

C, and a PSRR of 42 dB can be


expected for T = 27

C and VSCapa = 1.4 V. The PSRR
is 80 dB for VSCapa = 1.8 V, and even greater (90 dB)
for higher values up to 2.5 V. The power dissipation is
11 W at 1.4 V.
In Fig. 8 are shown some simulations of the reference voltage
(BG) against the temperature for two different voltage values
available at the SCapa. The BG starts to work properly at a
voltage around 800 mV.
In Fig. 9 are shown two Monte Carlo simulations taking into
account process and mismatching variations, with a number of
100 samples (Y -axis: samples distribution) for two different
working temperature conditions: 22

C and 65

C.
C. Control Unit
The architecture of the unit is shown in Fig. 10. The ba-
sic elements are two comparators that sense continuously the
voltage at the SCapa and compare it with a reference voltage
supplied by the bandgap. Two resistive networks are used to
adapt the level values of V
SCapa
to the range dened by the
bandgap reference voltage (BG, Fig. 10). One comparator is
prepared to sense when the voltage at the SCapa reaches V
max
out
,
and the other one is prepared to detect V
min
out
. In addition, the
comparators have been designed with a hysteresis of 20 mV
Fig. 10. Control unit.
Fig. 11. Comparator architecture.
in order to dene better the voltage-detection points. The archi-
tecture and hysteresis of the comparator are shown in Fig. 11.
Both comparators share the same bandgap circuit, and also, they
use the same CS in order to reduce the consumption of this unit.
The dened hysteresis band is 25 mV.
The signals generated by the comparators are used by a
simple logical circuitry to generate the control signal for the
PMOS transistors and dene the charge and discharge phases
3254 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 9, SEPTEMBER 2008
Fig. 12. Controls signals generated by the control unit.
of the SiP. The comparators and the digital logic are powered
by the voltage at the SCapa.
As commented upon previously, the comparators are in
charge of detecting the maximum and minimum voltages at the
SCapa. In this way, several values of V
max
out
and V
min
out
can be
selected using different values for the resistive networks.
Fig. 12 shows the control signals generated by the control
unit. It is also possible to observe how the output of the
comparators increase and decrease its output in function of the
supply voltage provided by the SCapa.
In this implementation, the control module is able to work
with an integrated on-chip resistance network able to detect
V
max
out
= 1.1 V and V
min
out
= 1.0 V or with an external resis-
tance allowing the system to work until a maximum voltage
up to 2.3 V.
V. SIMULATED AND EXPERIMENTAL RESULTS
The circuit has been designed in 0.13-m technology by
STMicroelectronics through CMPTIMA [40]. The circuit in
the die is shown in Fig. 13(a). The total size is 950 m
550 m. To validate the circuit, the experimental results have
been compared with the simulated ones, and some of them are
presented in this section. The experimental setup is based on
the use of four Quick Pack PZT QP20W stacked in parallel,
working at 7 m/s
2
at 80 Hz. It is assumed that the PZTs are not
exactly synchronized. The generators are mounted and clamped
over an electromagnetic vibration shaker ET-132 Labworks Inc.
The shaker is driven with the Pa-119 Labworks Inc. amplier.
An LC2442 laser by Keyence is used for the displacement
measurements. Two Tektronix oscilloscopes TDS 2014 and
TDS 714L are used to visualize the circuit and the Agilent Tech-
nology N6705A DC Power Analyzer is used to verify the power
consumption. The experimental setup is shown in Fig. 13(b).
Fig. 13. (a) Final die implementation and (b) experimental setup.
To verify the system, an estimated power of 1.5 mW has
been assumed representing the consumption of the full load
(RF plus processing, Fig. 1). Both PMOS switches are activated
at the same time using just one control unit. In addition, it is
assumed that the power is consumed in pulses of 10 ms.
The selected value of the capacitor is 47 F. A SCapa or
a long capacitor value is not used to avoid long simulations
time. Using the previous values and taking into account that the
energy transferred form the capacitor to the load is described
by (5), where V
max
out
and V
min
out
are the dened maximum and
minimum voltage values selected at the capacitor. With these
values, the total energy involved in the discharge phase is
around 5 J, dening an average output current of 600 A.
For this paper, 1.1 and 1.0 V have been used as maximum and
minimum voltages, respectively. These values are obtained
using the on-chip resistance network in the control module.
From the simulations, several interesting values could be
extracted. The start-up time is 230 ms (Fig. 2); the time involved
in the discharge phase is 8 ms; and in the recharge phase is
COLOMER-FARRARONS et al.: POWER-CONDITIONING CIRCUITRY FOR A SELF-POWERED SYSTEM 3255
Fig. 14. Simulated steady-state response of the system and voltage drop across the PMOS switch at 7 m/s
2
at 80 Hz.
Fig. 15. Experimental system start-up at 7 m/s
2
at 80 Hz.
60 ms (Fig. 14) for a typical case. The voltage drop across the
PMOS switch is 11 mV also for a typical case. Several Monte
Carlo simulations show that the drop voltage range can vary
from 25 to 3 mV depending on the technological variation.
Fig. 15 shows the experimental start-up. The time involved
in this phase is 250 ms. The maximum voltage at the capacitor
is 1.14 V, whereas V
min
is 1.02 V. The bandgap voltage
is 438 mV.
The experimental discharge and recharge times are 10 and
55 ms, respectively. The drop voltage across the switch is
17 mV. These values are shown in detail in Fig. 16. The whole
consumption of the electronics is 67 W. All experimental
values are closed to the extracted simulated values, and the
system is fully validated. The time differences between exper-
imental and simulated values are due to the accuracy of the
developed spectre-compatible model in terms of the generated
Fig. 16. Experimental steady-state response of the system and voltage drop
across the PMOS switch at 7 m/s
2
at 80 Hz.
current and by the consumption of the implemented circuit.
A successful test has been carried out using external resistors
networks working with V
max
= 1.4 V and V
min
= 1.2 V.
E
(J)
= 0.5C
SCapa
(V
max
out
)
2
0.5C
SCapa

V
min
out

2
. (5)
VI. CONCLUSION
This paper has presented a full custom PCC for a self-
powered system based on vibration-energy scavenging, which
is a low-cost PZT commercial generator in order to validate the
conception of the IC.
The whole architecture has been designed using a low-power
low-voltage commercial technology. The design of the system
is based on the use of a validated model of the PZT micro power
3256 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 9, SEPTEMBER 2008
TABLE II
PCC MAXIMUM RATINGS
generator. The architecture of the proposed PCC is presented,
and each circuit block is also described in detail.
The experimental performance of the PCC has been pre-
sented and compared with the simulated values controlling
booth PMOS switches with just one control unit. The simula-
tions are fully validated by experimental measurements.
These results conrm the correct performance of the adopted
architecture integrated in a commercial technology. In Table II
are shown the main parameters of the PCC in terms of the
following: the maximum voltage at the input rectier and at the
SCapa and the drop voltage across the PMOS switch.
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COLOMER-FARRARONS et al.: POWER-CONDITIONING CIRCUITRY FOR A SELF-POWERED SYSTEM 3257
Jordi Colomer-Farrarons (S06) received the B.Sc.
degree in electrical engineering from the Salesians
Technical Engineering School, Barcelona, Spain, in
2002, and the M.Sc. degree in electrical engineer-
ing from the University of Barcelona, Barcelona,
in 2005.
From 2002 to 2005, he was a Hardware De-
sign Engineer with Francisco Albero SA, Barcelona.
Since 2005, he has been a FellowResearcher with the
Systems for Instrumentation and Communications
Laboratory, Electronics Department, University of
Barcelona, where he is working on low-voltage low-power circuits, smart
power, harvesting design circuits, interface circuits for biomedical applications,
and microelectronic design.
Pere Miribel-Catal (M08) received the M.Sc.
degree in physics and the Ph.D. degree from the
University of Barcelona, Barcelona, Spain, in 1994
and 2000, respectively.
From 1993 to 1999, he was a Research Fellow
with the Systems for Instrumentation and Communi-
cations Laboratory, Electronics Department, Univer-
sity of Barcelona, where he worked on high-voltage
smart-power circuits and microelectronic design,
and since 2003, has been an Associate Professor
(Professor Titular). In 1998, he was a Visiting Re-
search Fellow at the LAAS-CNRS Laboratory, Toulouse, France. He had a
postdoctoral position in the design center of ON Semiconductor Inc., Toulouse,
France, where he designed power-management integrated dcdc converters. His
research topics are focused on low-voltage low-power integrated circuits, inter-
face and analog processing circuits, particularly for biomedical applications,
and smart-power and power-management circuits.
Albert Saiz-Vela (S06) received the M.Sc. de-
gree in electrical engineering from the University
of Barcelona, Barcelona, Spain, in 2001, where he
is currently working toward the Ph.D. degree in
electrical engineering in the Systems for Instrumen-
tation and Communications Laboratory, Electronics
Department, Universitat de Barcelona.
From 2001 to 2003, he was a Hardware Design
Engineer with the Research Division, Comelta,
with AMR Systems, and with the Plasma TV De-
sign Group, Sony BCN Technology Center, Sony,
Barcelona. His main research interests include efcient high-voltage switched-
capacitor dcdc converter design (commonly known as charge pumps), nu-
merical simulation of analog circuits, and analog driving circuit design for
PZT-based actuators in miniaturized systems (specically miniaturized robots).
Manel Puig-Vidal (M94) received the M.Sc. de-
gree in physics from the University of Barcelona,
Barcelona, Spain, in 1988, and the Ph.D. degree from
Paul Sabatier University, Toulouse, France, in 1993.
From 1989 to 1993, he was a Research Fellow
with the Laboratoire dAutomatique et dAnalyse
des Systmes, Toulouse, where he worked on
latch-up-free smart-power technology for automo-
tive applications. In 1993, he was an Assistant Pro-
fessor with the University of Barcelona, where he
worked in the eld of power electronics, and, since
1995, he has been an Associate Professor with the Systems for Instrumentation
and Communications Laboratory, Electronics Department, where he teaches
power electronics, control systems, and robotics in the electronic and computer
science engineering undergraduate programs. He is currently developing his
research in the eld of smart-power integrated-circuit design and micro-
robotics design based on smart materials for bioengineering applications in
the Bioelectronics and Nanobioscience Division, Nanobioengineering Research
Laboratory, Barcelona.
Josep Samitier (M95) received the M.Sc. degree
in physics and the Ph.D. degree from the University
of Barcelona, Barcelona, Spain, in 1982 and 1986,
respectively.
From February 1984 to June 1985, he was a Vis-
iting Research Fellow at the Philips Electronic Lab-
oratory (LEP), Paris, France. From March 2001 to
June 2005, he was the Director of the Electronics De-
partment and Deputy Head of the Barcelona Science
Park (PCB). He is currently a Full Professor with the
Systems for Instrumentation and Communications
Laboratory, Electronics Department, University of Barcelona, and the Director
of the Nanobioengineering Laboratory that is supported by the Institute of Bio-
engineering of Catalonia (IBEC). His current research and developed projects
concern the development of nanotechnologies for biomedical applications. He
has published more than 150 scientic papers in these elds. He is the holder
of four licensed patents.
Prof. Samitier is the Coordinator of the Spanish Platform on Nanomedi-
cine and member of the nanotechnology networks: Nano Spain, European
network Phantom, and Nano2life European Network of Excellence. In the last
15 years, he has participated and coordinated several European projects con-
cerning integrated microsystems and, more recently, nanotechnology devices.
He was a co-recipient of the Barcelona City Prize from the 2003 Barcelona
Council in the area of technology.