E. F.

Schubert, Rensselaer Polytechnic Institute, 2003

1
MOSFETS - Fabrication


Fabrication of MOSFETs

The first MOSFETs had Al gates.
As we will see later, modern MOSFETs do no longer employ Al gates.


E. F. Schubert, Rensselaer Polytechnic Institute, 2003
2


Thermal oxide of Si:
Si + O
2
SiO
2

this reaction is mediated by high temperatures.

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
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thermal oxide has great technical relevance.
Properties of SiO
2
:
Adherent
Chemically inert
Diffusion barrier
Excellent insulator
Excellent Si / SiO
2
interface

Question: What properties does an excellent interface have?

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
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Disadvantage of the process described above is the stringent alignment
tolerance:

(1) If there is a large overlap of gate electrode and contact tubs.
A high parasitic capacitance is obtained as a result.


(2) If there is no overlap of gate electrode and contact tubs.
MOSFET does not work.




E. F. Schubert, Rensselaer Polytechnic Institute, 2003
5
Self-aligned, poly-Si gate process revolutionized fabrication




Self-aligned process minimizes overlap capacitances. S, G, & D defined
in one photolithographic step.


E. F. Schubert, Rensselaer Polytechnic Institute, 2003
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Poly-Si gates have a higher resistance than Al gates. To reduce the gate
resistance the poly-Si is n
+
-type poly-Si. However, because the gate
carries no current, the resistance of poly-Si is acceptable. Self-aligned
process is not possible with Al, because Al does not withstand
T = 800 C required after implantation.


E. F. Schubert, Rensselaer Polytechnic Institute, 2003
7
Comparison of MOS technologies

P-channel MOS is oldest and simplest technology but slow due the
low mobility of holes.
N-channel MOS is faster than p-channel MOS, due to higher mobility
of electrons than holes.
CMOS technology is prevalent technology at the present time.




E. F. Schubert, Rensselaer Polytechnic Institute, 2003
8
CMOS technology
CMOS uses an n-channel and a p-channel FET in series.
Illustration of a CMOS inverter:



N-channel MOS turns on for positive V
GS
. P-channel MOS turns on for
negative V
GS
. One of them is always in the off state.
CMOS consumes very little power. VLSI circuits are possible only with
CMOS technology. An n-MOS VLSI circuit would consume too much
power.

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
9
Parasitic MOSFET operation



Note that

d
OX, gate
<< d
OX, field


d
OX, gate
100 or smaller

d
OX, field
10 000 = 1.0 m


E. F. Schubert, Rensselaer Polytechnic Institute, 2003
10
Transmission electron micrograph (TEM) of MOSFETs

(after Lucent Corporation)

Micrograph reveals that the gate length is a tenth-micron (0.1 m)
Si has an ordered atom configuration
The SiO
2
has a disordered atom configuration
Minimum oxide thickness is about 10 20 , limited by gate leakage

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
11


Micrograph reveals a gate length of 0.05 m
Silicide layer has purpose of contacting the poly-Si gate

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
12
Ion implantation

Ion implantation is the dominant doping technique in Si microelectronics.



An implant has a projected range, projected straggle, and lateral
straggle
They depend on the implant energy and implant species

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
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E. F. Schubert, Rensselaer Polytechnic Institute, 2003
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Estimate projected range, projected straggle, and lateral straggle
for the preceding figure!

Calculated depth distribution for Be and Si in GaAs:



E. F. Schubert, Rensselaer Polytechnic Institute, 2003
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Questions:
Are projected range and projected straggle independent?
Are lateral range and projected straggle independent?
What determines the projected range?
For a given ion energy, is Be or Si will be implanted deeper? Why?

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
16
Post-implantation anneal
High temperatures required to anneal defects created by
implantation
Types of defects: native defects and non-native defects
Give examples of native and non-native defects!
Activation energy to create a native defect (e. g. moving a Si atom
from a Si lattice site to an interstitial position) is higher than the
activation energy to create a non-native defect (e. g. moving a B
atom from a Si lattice site to an interstitial position). Why?
E
native
> E
non-native


E. F. Schubert, Rensselaer Polytechnic Institute, 2003
17
Arrhenius plot of diffusion constant::


Plot shows: High temperatures required to anneal native defects
Diffusants (i. e. elements that diffuse) in a material with many defects
have a higher diffusion constant than in a material that is structurally
perfect
Transient enhanced diffusion (TED) occurs as a result


E. F. Schubert, Rensselaer Polytechnic Institute, 2003
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Native defects need to be annealed out rapidly in order to avoid
excessive diffusion of dopants.




E. F. Schubert, Rensselaer Polytechnic Institute, 2003
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Shallow implants in modern MOSFET structure
As scaling progresses, implants get shallower.
Shallow junction process:


Why two implants?

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
20
Silicon-on-insulator (SOI) technology

Thin Si active layer on top of an insulator, namely SiO
2

n
+
-type bathtubs reach all the way to the oxide
Reduced junction capacitances, that is, reduced p-n junction
capacitance between the n
+
-type bathtub and the p-type body
(substrate)
Higher speed
Soitec Corporation is manufacturer of SOI wafers using smart cut
technology
IBM Corporation has alternative process, called SIMOX process
(silicon implantation with oxide)

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
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SOI process

Splitting of wafers due to mechanical strain induced by H implant
Si/SiO
2
interface is of high quality due to thermal oxide process

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
22
Original Si wafer can be re-used, i. e. Si wafer can be recycled
Micrograph of SOI wafer






E. F. Schubert, Rensselaer Polytechnic Institute, 2003
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(after IBM Corp.)


(after Soitec Corp.)

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
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High-
r
and low-
r
materials (also called high-k and low-k
materials)
There are two application areas of dielectrics in CMOS ICs:
Gate dielectric
Field dielectric
SiO
2
(silica) is the natural but not the optimal choice for these dielectrics.
The relative dielectric constant (
r
) of SiO
2
is
r
= 3.9. The dielectric
constant for the optimal-choice-material would be

Optimum
>
SiO2
for the gate dielectric (Why?)

Optimum
<
SiO2
for the field dielectric (Why?)
This motivates the search for high-
r
and low-
r
materials.
Low-
r
materials are
r
= 2.0 3.0
High-
r
materials are
r
> 5.0

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
25
Interconnects

The conventional choice for the metal interconnects is aluminum (Al). Al
has relatively high conductivity and is easy to evaporate. However, there
are metals that have a higher conductivity, namely Cu and Au. However,
in contrast to Al, both Cu and Au form deep levels in Si (see, for
example, S. M. Sze Physics of semiconductor devices, J ohn Wiley and
Sons, New York, 1982).

Specific resistivity of some metals:
Ag = 1.591 E08 cm Cu = 1.664 E08 cm
Au = 2.349 E08 cm Al = 2.655 E08 cm


E. F. Schubert, Rensselaer Polytechnic Institute, 2003
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Au (Gold)
In addition to forming deep levels in Si, Au reacts with Si and forms a
brittle inter-metallic compound called purple plague. The purple plague
material has been identified as AuAl
2
. Therefore Au is not a good choice
for interconnects on Si.

Note: A totally unrelated meaning of Purple plague relates to the
proliferation of a non-native plant called Purple Loosestrife in North
Americas wetlands.

(Picture of Purple Loosestrife)

E. F. Schubert, Rensselaer Polytechnic Institute, 2003
27
Cu (Copper)
Copper is the current choice for interconnects. Diffusion barrier is
required. Tungsten (W) is a common diffusion barrier.
(Cu interconnects on an IC)

Ag (Silver)
Ag is a soft metal. Ag oxidizes easily. Ag is quite reactive. Would
encapsulation help?


E. F. Schubert, Rensselaer Polytechnic Institute, 2003
28
Optical interconnects
Future interconnects may be optical.
Electrical interconnects are limited by RC time delay
RC time delay increases with length of interconnect line
Optical interconnects are not limited by RC-time delays
Optical interconnects are increasingly used for shorter and shorter
distances