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Objective

This project aims at developing an efficient multiplier that will enhance the performance
of the processors or signal processing application. As we know that many multimedia and DSP
applications are highly multiplication intensive so that the performance and power consumption
of these systems are dominated by multipliers. Unfortunately, portable devices mostly operate
with stand-alone batteries, but multipliers consumes large amount of power. Digital signal
processing systems need multiplication algorithms to implement DSP algorithms such as filtering
where the multiplication algorithm is directly within the critical path. Consequently, it’s greatly
imperative to develop power-efficient multipliers to compose a high-performance and low-power
portable multi-media and DSP system.















Introduction:-
Multiplication is a mathematical operation that at its simplest is an abbreviated process of
adding an integer a specified number of times. Multiplication is the fundamental arithmetic
operation important in several processors and digital signal processing systems. Digital signal
processing systems need multiplication algorithms to implement DSP algorithms such as
filtering where the multiplication algorithm is directly within the critical path .Therefore, the
demand for high-speed multiplication algorithms has become more important. The higher
speed results to enlarged power consumption, thus, low power architectures will be the
choice of the future. This has given way to the growth of new circuit algorithms, with the
plan of reducing the power consumption of multiplication algorithms with having high-speed
structures and appropriate performance. There are two kinds of multiplication algorithms as
shown in fig. 1.1
a) Serial multiplication algorithms
b) Parallel multiplication algorithms










Figure1.1: Classification of multipliers

Digital multipliers
Serial multipliers Parallel multipliers
Array multipliers Tree multipliers
1. Binary tree
2. Wallace tree
3. Dada tree
Unsigned multiplication
1. Braun multiplier
Signed multiplication
1. Booth multiplier
2. MBE
3. Baugh Wooley
multiplier
Serial multiplication algorithms use sequential circuits with feedbacks. In serial
multiplication algorithms, inner products are sequentially produced and computed.
But speed of serial multipliers is very less than parallel multipliers. The only reason one
prefer parallel multiplier. Parallel multiplication algorithms often use combinational circuits,
and do not contain feedback structures.
In parallel multipliers, there are two main classifications. They are
1. Array multipliers
2. Tree multipliers.
C.S. Wallace proposed a tree multiplier architecture which performs high speed
multiplication. But this has a high structural irregularity and is unsuitable for VLSI
implementation as it demands regularity. Array multiplier classified as signed and unsigned
multipliers. Braun multiplier is used for unsigned multiplications whereas Baugh-Wooley
multiplier, booth multiplier and modified booth multiplier can be used for signed
multiplication.
In various computing and signal processing applications, parallel multiplier has been a basic
building block for many algorithms. Many high performance algorithms and architectures
have been proposed to accelerate multiplication. Multiplication can be divided into three
steps-:
a) generating partial products
b) summing up all partial products until only two rows remain
c) Adding the remaining two rows of partial products by using a carry propagation adder.

In the first step, two methods are commonly used to generate partial products. The first
method generates partial product directly by using a 2-input AND gate. The second one uses
Baugh Wooley, radix-2, radix-4 modified Booth encoding (MBE), radix-8 to generate partial
products. Radix-4 MBE has been widely used in parallel multipliers to reduce the number of
partial products by a factor of two. Baugh Wooley generally not used because they are not
suitable for large size operands. Techniques like Wallace tree, Compressor tree are used in
the second step to reduce the number of rows of the partial product. During third step,
advanced adding concepts like carry-look-ahead, carry select adder are used.
Methodology/ Planning of work
Booth’s Algorithm
The booth’s algorithm handles both signed and unsigned number. When the multiplier has a
stream of 1’s, the number of additions required is minimized. This speeds up the multiplication
operation as compared to method followed for unsigned number. The exact amount of time
reduction depends on the bit pattern in the multiplier. The basic principle followed in Booth’s
algorithm i.e. multiplication is nothing but addition of properly shifted multiplicand pattern.
Radix 2 Booth’s Algorithm
Radix 2 multiplication algorithm is multiplication algorithm that multiplies two
signed binary numbers in two’s compliment notations.
The Booth's algorithm serves two purposes:
1. Fast multiplication
2. Signed multiplication.
Booth algorithm requires examination of the multiplier bits, and shifting of the partial
product. Prior to the shifting, the multiplicand may be added to partial product, subtracted
from the partial product, or left unchanged according to the following rules:
Booth algorithm gives a procedure for multiplying binary integers in signed –2’s complement
representation. The booth algorithm with the following example:
Example: 2 ten × (–4) ten
0010 two × 1100 two
Step 1: Making the Booth table
I. From the two numbers, pick the number with the smallest difference between a
series of consecutive numbers, and make it a multiplier.i.e., 0010 — From 0 to 0
no change, 0 to 1 one change,1 to 0 another change, and so there are two changes
on this one,1100 — From 1 to 1 no change, 1 to 0 one change, 0to 0 no change, so
there is only one change on this one.Therefore, multiplication of 2 × (–4), where 2
ten (0010two) is the multiplicand and (–4) ten (1100two) is the multiplier.
II. Let X = 1100 (multiplier)
Let Y = 0010 (multiplicand)
Take the 2’s complement of Y and call it –Y
–Y = 1110
III. Load the X value in the table.
IV. Load 0 for X-1 value it should be the previous first least significant bit of X.
V. Load 0 in U and V rows which will have the product of X and Y at the end of
operation.
VI. Make four rows for each cycle; this is because we are multiplying four bits
numbers.
Step 2: Booth Algorithm
Booth algorithm requires examination of the multiplier bits, and shifting of the partial
product. Prior to the shifting, the multiplicand may be added to partial product, subtracted
from the partial product, or left unchanged according to the following rules:
Look at the first least significant bits of the multiplier ―X‖, and the previous least
significant bits of the multiplier ―X - 1‖.
I 0 0 Shift only
1 1 Shift only.
0 1 Add Y to U, and shift
1 0 Subtract Y from U, and shift or add (-Y) to U and shift
II Take U & V together and shift arithmetic right shift which preserves the sign bit of
2’s complement number. Thus a positive number remains positive, and a negative
number remains negative.
III Shift X circular rights shift because this will prevent us from using two registers for
the X value.



Tool Required:-
Model Sim
Xilinx ISE 13.1
FPGA kit (if available)