Px4x - 9 2LE TM EN 001

MiCOM Px4x-92LE
ALSTOM 2013. All rights reserved. Information contained in this document is indicative only. No representation or warranty is
given or should be relied on that it is complete or correct or will apply to any particular project. This will depend on the technical
and commercial circumstances. It is provided without liability and is subject to change without notice. Reproduction, use or
disclosure to third parties, without express written authority, is strictly prohibited.
Technical Manual
IEC 61850-9-2LE Interface
Platform Hardware Version: M
Platform Software Version: (P446, P546, P841B) v74, (P645,
P746) v12
Publication Reference: Px4x-92LE-TM-EN-1.1
Contents
Chapter 1 Introduction 1
1 Chapter Overview 3
2 Foreword 4
3 P446 Ordering Options 5
7 P841B Ordering Options 9
Chapter 2 Hardware Design 11
2 Board Connections 14
3 Location in IED 15
Chapter 3 Settings and Records 17
2 P446, P546, P841B 20
2.1 Settings Table 20
2.2 Channel mappings for SAV Test, SAV Questionable, SAV Invalid 23
3 P645 24
4 P746 27
5 Virtual CT and VT Ratio Settings 30
Chapter 4 Operation 31
2 IEC 61850 34
2.1 Benefits of IEC 61850 34
2.2 IEC 61850 Interoperability 34
2.3 Introduction to IEC 61850-9-2LE 34
3 Data Resampling 36
4 Sampled Value Alignment 37
5 Data Quality 38
5.1 Impact of Data Quality on Protection Functions 38
5.1.1 P446, P546, P841B 38
5.1.2 P645 39
5.1.3 P746 40
6 Process Bus Performance 41
6.1 Sample Loss Data 41
7 VT Switching 42
8 IED Alarms 43
9 P546 44
9.1 Current Differential Function 44
Chapter 5 Application Examples 47
1 Application Examples 49
2 Overview 50
3 P446 51
3.1 Sampled Value Distribution 51
4 P546 53
4.2 Current Differential Schemes 54
5 P645 57
6 P746 59
7 Bay Architecture 60
7.1 Arrangement of the Station and Process Buses 62
8 Voltage Input Switching 63
Chapter 6 Scheme Logic 65
2 Programmable Scheme Logic 68
3 P446, P546, P841B 69
3.1 DDB Signals Table 69
4 P645 70
5 P746 71
Chapter 7 Commissioning Instructions 73
2 General Guidelines 76
3 Commissioning Test Equipment 77
4 Check Connections 78
5 IED With One Logical Node Configured 79
6 IED With Two or More Logical Nodes Configured 80
7 P645, P746 81
7.1 Differential Protection Function Testing 81
8 P546 82
8.1 Comissioning the GPS functionality 82
8.1.1 Strength of P594 Optical Signal at IED 82
8.1.2 Checking the GPS Synchronisation Signal at the IED 82
8.1.3 Commissioning Mode 82
Chapter 8 Technical Specifications 83
2 Interfaces 86
2.1 100 Base FX Transmitter Characteristics 86
2.2 100 Base FX Receiver Characteristics 86
2.3 Ethernet Port Copper 86
Appendix A Wiring Diagrams 87
1 Appendix Overview 89
2 P446 with IEC 61850-9-2LE Interface Configuration 1 90
Contents Px4x-92LE
ii Px4x-92LE--TM-EN-1.1
27 P841B with IEC 61850-9-2LE Interface Configuration 1 115
Index 121
Px4x-92LE Contents
Px4x-92LE--TM-EN-1.1 iii
Contents Px4x-92LE
iv Px4x-92LE--TM-EN-1.1
Table of Figures
Figure 1: IEC 61850-9-2LE board connectors 14
Figure 2: Rear view of IED showing IEC 61850-9-2LE interface 15
Figure 3: MiCOM IED with conventional CT and VT inputs 35
Figure 4: IED with IEC 61850 9-2LE inputs 35
Figure 5: Data sampling using CTs/VTs and an input board 36
Figure 6: Data sampling using an IEC 61850-9-2LE interface 36
Figure 7: Two-ended P546 scheme with IEC 61850-9-2LE IEDs at both feeder ends 44
Figure 8: Conventional and non-conventional P546 IEDs combined in a current
differential scheme
45
Figure 9: Overview of functionality 51
Figure 10: IED receiving Sampled Values from two merging units 52
Figure 11: IED receiving Sampled Values from four merging units 52
Figure 12: Overview of P546 functionality 53
Figure 13: IED receiving Sampled Values from two merging units 54
Figure 14: IED receiving Sampled Values from four merging units 54
Figure 15: Two-ended scheme with Sampled Value unputs 55
Figure 16: Three-ended scheme with analogue and Sampled Value unputs 56
Figure 17: Overview of P645 functionality 57
Figure 18: IED receiving sampled from three merging units 58
Figure 19: IED receiving Sampled Values from five merging units 58
Figure 20: IED receiving sampled from six merging units 59
Figure 21: Example of Bay Architecture with IEC 61850-9-2LE IEDs 61
Figure 22: Integration of an IED with the Station Bus 62
Figure 23: Example of three-phase voltage switching 63
Figure 24: Application of switching the check synchronizing voltage 64
Figure 25: P446 distance 80TE with NCIT 24 inputs and 32 outputs. Part 1 of 2 90
Figure 26: P446 distance 80TE with NCIT 24 inputs and 32 outputs. Part 2 of 2 91
Figure 27: P446 distance 80TE with NCIT 24 inputs, 8 standard outputs and 12 high-break
outputs. Part 1 of 2
92
93
94
95
Figure 31: P546 current differential 80TE with NCIT 24 inputs and 32 outputs. Part 1 of 2 96
Figure 32: P546 current differential 80TE with NCIT 24 inputs and 32 outputs. Part 2 of 2 97
Figure 33: P546 current differential 80TE with NCIT 24 inputs, 16 standard outputs and 8
high-break outputs. Part 1 of 2
98
99
100
101
Figure 37: P645 current differential 5 bias input transformer differential 80TE with 4-pole
VT inputs, with NCIT, 24 inputs, 20 outputs plus CLIO and RTD . Part 1 of 1
102
Figure 38: P645 current differential 5 bias input transformer differential 80TE with 4-pole
VT inputs, with NCIT, 16 inputs, 24 outputs plus CLIO and RTD . Part 1 of 1
103
Figure 39: P746 busbar 80TE with NCIT, 16 inputs, 16 outputs. Part 1 of 1 104
Figure 40: P746 busbar 80TE with NCIT, 16 inputs, 8 standard outputs, 8 high-break
105
107
109
110
112
Figure 50: P841B autoreclose 80TE with NCIT, 24 inputs, 32 outputs. Part 1 of 2 115
Figure 51: P841B autoreclose 80TE with NCIT, 24 inputs, 32 outputs. Part 2 of 2 116
Figure 52: P841B autoreclose 80TE with NCIT, 24 inputs, 16 standard outputs, 8 high-
break outputs. Part 1 of 2
117
118
119
120
Table of Figures Px4x-92LE
vi Px4x-92LE--TM-EN-1.1
INTRODUCTION
CHAPTER 1
Chapter 1 - Introduction Px4x-92LE
2 Px4x-92LE--TM-EN-1.1
1 CHAPTER OVERVIEW
This chapter contains the following sections:
Chapter Overview 3
Foreword 4
P446 Ordering Options 5
P841B Ordering Options 9
Px4x-92LE Chapter 1 - Introduction
Px4x-92LE--TM-EN-1.1 3
2 FOREWORD
This technical manual provides a functional and technical description of Alstom Grid's Px4x-92LE, as well as
a comprehensive set of instructions for using the device.
We have attempted to make this manual as accurate, comprehensive and user-friendly as possible.
However we cannot guarantee that it is free from errors. Nor can we state that it cannot be improved. We
would therefore be very pleased to hear from you if you discover any errors, or have any suggestions for
improvement. All feedback should be sent to our contact centre via the following URL:
http://www.alstom.com/grid/contactcentre/
3 P446 ORDERING OPTIONS
E00012
Digit # 5 6 7 8 9 10 11 12-13 14 15
Distance Protection Relay P446 1 C 1 B 1 M 0 74 0 M
Version: Distance & Autoreclose for 2 Circuit Breakers
Vx auxiliary rating
In/Vn rating
Hardware options
A
Product options - 1
Product options - 2
Protocol options
Mounting
Language
Software version
Customer Specific Options
Standard Version
Hardware version
P446
1 - 4
1
C
1
0
M
B
1
M
0
74
24 - 54Vdc
48 - 125Vdc (40 - 100Vac)
110 - 250 Vdc (100 - 240 Vac)
Dual rated CT (1 / 5A : 100 - 120 V)
IEC 61850-9-2LE Sampled Analogue Values Ethernet board
Standard - None
IRIG-B only (Modulated)
Fibre Optic Converter Only
IRIG-B (Modulated) & Fibre Optic Converter
Ethernet (100Mbit/s)
Ethernet (100Mbit/s) plus IRIG-B (Modulated)
Ethernet (100Mbit/s) plus IRIG-B (Un-modulated)
IRIG-B (Un-modulated)
InterMiCOM + Courier Rear Port
InterMiCOM + Courier Rear Port + IRIG-B modulated
Redundant Ethernet Self-Healing Ring, 2 multi-mode fibre ports + Modulated IRIG-B
Redundant Ethernet Self-Healing Ring, 2 multi-mode fibre ports + Un-modulated IRIG-B
Redundant Ethernet RSTP, 2 multi-mode fibre ports + Modulated IRIG-B
Redundant Ethernet RSTP, 2 multi-mode fibre ports + Un-modulated IRIG-B
Redundant Ethernet Dual-Homing Star, 2 multi-mode fibre ports + Modulated IRIG-B
Redundant Ethernet Dual-Homing Star, 2 multi-mode fibre ports + Un-modulated IRIG-B
Redundant Ethernet PRP, 2 multi-mode fibre ports + Modulated IRIG-B
Redundant Ethernet PRP, 2 multi-mode fibre ports + Un-modulated IRIG-B
1
24 inputs and 32 standard outputs
24 inputs and 8 standard plus 12 high break outputs
K-Bus
IEC870
DNP3.0
Flush/Panel mounting
19" Rack mounting
English, French, German, Spanish
English, French, German, Russian
Chinese, English or French via HMI, with English or French only via Communications port
No fibre interface
Ch1=850nm multi-mode , Ch2=850nm multi-mode
Ch1=1300nm single-mode , Ch2=not fitted (2 Terminal only)
Ch1=1300nm single-mode , Ch2=1300nm single-mode
Ch1=1300nm multi-mode , Ch2=not fitted (2 Terminal only)
Ch1=850nm multi-mode , Ch2=1300nm single-mode
Ch1=1300nm single-mode , Ch2=850nm multi-mode
Standard Version
Customer Specific
74 - based on '57' but with support for Sampled Analogue Values
M: As K plus increased main processor memory (XCPU3), Cyber Security
K: Extended main processor (XCPU2) With Function Keys & Tri-colour LEDs
E00017
1-4 5 6 7 8 9 10 11 12-13 14 15
Current Differential with Distance Backup P546 1 C 1 A 1 M 0 74 0 M
M
Software Options Design Suffix dependent
74
Vx Aux Rating
1
In/Vn Rating
C
Hardware Options
Product Specific Options - 1
Product Specific Options - 2
A
Protocol/Communications Options
1
Mounting Option
M
Language
0
Customisation
0
1
Design Suffix : Options
based on preferred solutions selection here
Ch1=850nm multi-mode, Ch2=850nm multi-mode
Ch1=1300nm single-mode, Ch2=not fitted (2 Terminal only)
Ch1=1300nm single-mode, Ch2=1300nm single-mode
Ch1=1300nm multi-mode, Ch2=not fitted (2 Terminal only)
Ch1=1550nm single-mode, Ch2=not fitted (2 Terminal only)
Ch1=1550nm single-mode, Ch2=1550nm single-mode
Ch1=850nm multi-mode, Ch2=1300nm single-mode
Ch1=850nm multi-mode, Ch2=1550nm single-mode
Ch1=1300nm single-mode, Ch2=850nm multi-mode
Ch1=1550nm single-mode, Ch2=850nm multi-mode
24 - 54Vdc
48 - 125Vdc (40 - 100Vac)
110 - 250 Vdc (100 - 240 Vac)
Default
Customer
J: As G plus dual characteristic optos
G: Enhanced Main Processor (CPU2) with hotkeys
B: Phase 2 Enhanced Coprocessor, wide range opto
74 - With Distance (Based on 57 but with support for Sampled Analogue Values)
Flush/Panel Mounting with Harsh Environment Coating
Rack Mounting with Harsh Environmental Coating
Flush/panel mounting with harsh environment coating
Rack mounting with harsh environmental coating
Standard - None
K-Bus
IEC60870-5-103 (VDEW)
DNP3.0
Multilingual - English, French, German, Spanish
Multilingual - English, French, German, Russian
In = 1A/5A ; Vn = 100-120Vac
E00024
P645 (Transformer Protection) Nomenclature
1-4 5 6 7 8 9 10 11 12-13 14 15
1 C 1 F 1 M 0 12 0 M
Vx Aux Rating :
1
Analogue Input (In) Rating :
C
Hardware Options :
Product Specific Options :
Protocol Options :
1
Mounting Options :
M
Language Options :
0
Software Version Options :
12
Settings Files Options :
0
Design Suffix : (Factory determined)
M
P645
F
1
24 - 54Vdc
48 - 125Vdc (40 - 100Vac)
110 - 250 Vdc (100 - 240 Vac)
Standard - no options
IRIG-B (Modulated) only
Fibre Optic Converter only
2nd Rear Comms port
2nd Rear Comms port + IRIG-B (Modulated)
Size 16 (80TE) case, 24 optos + 24 relays
Size 16 (80TE) case, 24 optos + 24 relays + RTD
Size 16 (80TE) case, 24 optos + 24 relays + CLIO (mA I/O)
Size 16 (80TE) case, 24 optos + 24 relays + RTD + CLIO (mA I/O)
Size 16 (80TE) case, 24 optos + 20 relays (including 4 high break)
Size 16 (80TE) case, 24 optos + 20 relays (including 4 high break) + RTD
Size 16 (80TE) case, 24 optos + 20 relays (including 4 high break) + CLIO (mA I/O)
Size 16 (80TE) case, 24 optos + 20 relays (including 4 high break) + RTD + CLIO (mA I/O)
Size 16 (80TE) case, 16 optos + 24 relays (including 8 high break)
Size 16 (80TE) case, 16 optos + 24 relays (including 8 high break) + RTD
Size 16 (80TE) case, 16 optos + 24 relays (including 8 high break) + CLIO (mA I/O)
Size 16 (80TE) case, 16 optos + 24 relays (including 8 high break) + RTD + CLIO (mA I/O)
K-Bus/Courier
Modbus
IEC60870-5-103
DNP3.0
Default
Customer Settings
12 - With Support for Sampled Analogue Values
HV-LV In = 1A/5A, Vn = (100/120V) (18CT/1VT)
HV-LV In = 1A/5A, Vn = (100/120V) (18CT/4VT)
Extended Phase 3 CPU with increased main processor memory
E00026
P746 Numerical Busbar Differential Protection
1-4 5 6 7 8 9 10 11 12-13 14 15
P746 1 C 1 A 1 M 0 12 0 M
Vx Aux Rating:
1
Analogue Input (In) Rating:
C
Hardware Options:
1
Product Specific Options:
A
Protocol Options:
1
Mounting Options :
M
Language Options:
0
Software Version Options :
12
Settings Files Options:
0
Design Suffix:
M
24 - 54Vdc
48 - 125Vdc (40 - 100Vac)
110 - 250 Vdc (100 - 240 Vac)
Nothing
IRIG-B (Modulated) only
Fibre Optic Converter only
2nd Rear Comms port
2nd Rear comms port + IRIG-B (Modulated)
Size 16 Case, 16 optos + 16 Relays
Size 16 Case, 16 optos + 8 Relays + 8 High Break Relays
K-Bus/Courier
Modbus
IEC60870-5-103
DNP3.0
Default
Customer Settings
12 - Based on 03 but with support for Sampled Analogue Values
CT1 - CT18 In = 1A/5A, Vn = (100/120V) (18CT/3VT)
Extended Phase 3 CPU with increased main processor memory
7 P841B ORDERING OPTIONS
E00023
Digit # 5 6 7 8 9 10 11 12-13 14 15
Multi-functional line terminal IED 1 C 1 C 1 M 0 74 0 M
Vx auxiliary rating
In/Vn Rating & Main Functionality
Hardware options
A
Product options
Protocol options
Mounting
Language
Software version
Customer Specific Options
Standard Version
Hardware version
P841
1 - 3
1
C
1
0
M
C
1
M
0
74
24 - 54Vdc
48 - 125Vdc (40 - 100Vac)
110 - 250 Vdc (100 - 240 Vac)
Standard - None
K-Bus
IEC870
DNP3.0
24 Inputs & 32 Standard Outputs
24 Inputs & 16 Standard + 8 High Break Outputs
24 Inputs & 8 Standard + 12 High Break Outputs
Standard Version
Customer Specific
74 - Based on 57 but with support for Sampled Analogue Values
Model A: Autoreclose for one CB (60TE) Dual rated CT(1/5A :100-120V)
Model B: Autoreclose for one/two CB (80TE) Dual rated CT(1/5A :100-120V)
Model B: Autoreclose for one/two CB (80TE) With IEC 61850-9-2LE Sampled Analogue Values Ethernet board
10 Px4x-92LE--TM-EN-1.1
HARDWARE DESIGN
CHAPTER 2
Chapter 2 - Hardware Design Px4x-92LE
12 Px4x-92LE--TM-EN-1.1
1 CHAPTER OVERVIEW
This chapter provides information about the product's hardware design.
Chapter Overview 13
Board Connections 14
Location in IED 15
Px4x-92LE Chapter 2 - Hardware Design
Px4x-92LE--TM-EN-1.1 13
2 BOARD CONNECTIONS
RX
TX
LINK
ACTIVITY
Fibre optic
Ethernet
connections
RJ45 service
port for
commissioning
and testing only
E00227
RJ45
1
2
3
4
5
6
7
8
TX+
TX-
RX+
RX-
Figure 1: IEC 61850-9-2LE board connectors
Optical Fibre Connectors
Uses 1300 nm multi mode 100BaseFx with ST connectors.
RJ45 Connector
This is a service port for commissioning and testing only. Do not use this for permanent connections.
LEDs
LED Function On Off Flashing
Green Link Link ok Link broken
Yellow Activity Traffic
Board Location
The board is located in the slot reserved for communication boards, usually slot C.
14 Px4x-92LE--TM-EN-1.1
3 LOCATION IN IED
The following diagram shows the IEC 61850-9-2LE interface highlighted in grey.
A B C
D E F G H J K L M N
E00250
Figure 2: Rear view of IED showing IEC 61850-9-2LE interface
Px4x-92LE Chapter 2 - Hardware Design
Px4x-92LE--TM-EN-1.1 15
16 Px4x-92LE--TM-EN-1.1
SETTINGS AND RECORDS
CHAPTER 3
Chapter 3 - Settings and Records Px4x-92LE
18 Px4x-92LE--TM-EN-1.1
1 CHAPTER OVERVIEW
IEDs which use the IEC 61850-9-2LE interface have additional settings, each depending on the IED.
Chapter Overview 19
P446, P546, P841B 20
P645 24
P746 27
Virtual CT and VT Ratio Settings 30
Px4x-92LE Chapter 3 - Settings and Records
Px4x-92LE--TM-EN-1.1 19
2 P446, P546, P841B
2.1 SETTINGS TABLE
IEDs which have the IEC 61850-9-2LE interface must be configured to the system and application.
MENU TEXT Col Row Default Setting Available Setting
Description
IEC 61850-9.2LE 18 00
This column contains all the configure/setting measurement parameters relative to IEC61850-9-2LE.
Physical Link 18 01 Fibre Optic Copper, Fibre Optic
This setting specifies the physical connection between the IED and the Process Bus network. The RJ45 copper port is for service use only and
should not be used as a permanent connection.
AntiAias Filter 18 02 Enabled Disabled, Enabled
This setting activates or deactivates the anti-aliasing filter, which conditions the Sampled Values from the Process Bus network.
Synchro Alarm 18 03 Local 1PPS
No SYNC CLK, Local
1PPS, Global 1PPS
This setting specifies the type of Sampled Value synchronisation expected by the IED, depending on the application.
Global 1PPS: the Sampled Values are synchronised with a global area clock (GPS like clock). The IED issues an alarm (9-2 Sample Alarm)
when it receives Sampled Value frames without Global 1PPS.
Local 1PPS: the Sampled Values are synchronised with a local area clock signal at the substation. Sampled Value frames received with Global or
Local synchronisation are acceptable with this setting. The IED issues the alarm '9-2 Sample Alarm' if the Sampled Value frames received have
no synchronisation.
No SYNC CLK: the Sampled Values do not need to be synchronised. With this setting the IED ignores the synchronisation flag in the Sampled
Value frames.
9.2 Test Mode 18 04 Test Blocked
Test Blocked, Test
Ignored, Test Only
This setting is used for processing Sampled Value frames with an IEC 61850 Test mode flag. This setting is common to all Logical Nodes
configured in the IED.
Test Blocked: all channel data frames received with an IEC 61850 Test flag are treated as invalid. The IED blocks relevant protection functions
and issues a 9-2 Sample Alarm.
Test Ignored: all channel data frames received with an IEC 61850 Test flag are treated as good so all protection functions remain active.
Test Only: all channel data received with an IEC 61850 Test flag are treated as good. Any channel data received without the Test flag are treated
as invalid. The IED blocks relevant protection functions and issues a 9-2 Sample Alarm.
Merge Unit Delay 18 05 1 ms
When Sampled Values are received at the IED from different Merging Units, they may not arrive simultaneously due to differences in Merging Unit
performance or different network path delays. This setting specifies the maximum time delay expected, starting at the reception of the Sampled
Value frame from the first Merging Unit to the reception of the Sampled Value frame from the last Merging Unit for each sample count. Signal
processing starts at the end of the Merging Unit delay and if a frame is not received in that specified time, an alarm appears.
(9-2 Sample Alarm).
The IED has a search command to measure and display the maximum Sampled Value frame delay. The Merging Unit Delay can be set based on
the result of the search, which is displayed on the IED.
VT Switch Mode 18 06 Disabled Disabled, Enabled
If VT Switching Mode is enabled, you can configure the IED to switch between different VT inputs. These can be single-phase or three-phase
inputs and are received as Sampled Values. The corresponding setting cells are visible when VT Switching Mode is enabled. Switching is
controlled either using opto or virtual inputs. These can be assigned in the IED's Programmable Scheme Logic. If you do not need to use VT
switching for voltage based protection functions or check synchronising, disable it.
LN Count 18 11 1
This setting specifies the number of Logical Nodes in use for receiving the Sampled Values required by the IED. The default value varies with the
product. Modify the LN Count to match the number of Merging Units relevant for the IED in each specific application. The default LN Count is
model dependent.
LN1 Name to LN9 Name 18 12 MiCOM Logical Node 1 to 9
20 Px4x-92LE--TM-EN-1.1
Description
Each Logical Node must be identified by a unique name that allows it to receive Sampled Values from a specific Merging Unit. The default name
for LN1 is MiCOM Logical Node 1. You can edit this ASCII text string using between 10 and 34 characters to match the Merging Units Logical
Node (sample value identifier) name . The same applies for LN2 to 9. The Logical Node name is the system-wide unique identification MsvID
defined in the Merging Unit control block MSVCB according to IEC 61850-9-2 Ed 1.0. The number of Logical Nodes available is variable, as set in
LN Count. For example, with an LN Count of 3, LN1 Name, LN2 Name and LN3 Name should be set to match those of the corresponding Merging
Units.
Rename the Logical Nodes used for the application. Use between 10 and 34 characters to match each MU Logical Node name. Each Logical
Node name must be exactly the same as the one set in the Merging Unit that broadcasts it.
IA1 IB1 IC1 18 31 LN1
Unused, LN1, LN2, LN3,
,LN 9
Three-phase current inputs to the IED.
IA2 IB2 IC2 18 32 Unused
Unused,LN1, LN2, LN3,
,LN 9
Three-phase current inputs to the IED.
INsen 18 33 Unused
,LN 9
Current input with sensitive range for SEF/REF functions. This single-phase current signal is recovered from the neutral current in the IEC
61850-9-2LE frame of the LN assigned.
IM 18 34 Unused
,LN 9
Current input for neutral current from a parallel feeder. This single-phase current signal is recovered from the neutral current in the IEC
61850-9-2LE frame of the LN assigned.
VA VB VC 18 35 LN1
,LN 9
Three-phase voltage inputs to the IED. The default setting Logical Node 1 indicates that only one LN is configured. This cell is visible only when
VT Switch Mode [18 06] is disabled.
Vsc1 18 36 Unused
,LN 9
This single-phase voltage is recovered from the phase(s) assigned in the IED setting. It may be assigned to Van, Vbn, Vcn, Vab, Vbc or Vca in the
settings. The IEC 61850-9-2LE interface uses the appropriate phase(s) from the Sampled Value frame received on the Logical Node configured
for Vsc1. The IED raises an Illegal Channel Map alarm if the same Logical Node is assigned to both [VA VB VC] and Vsc1. This cell is visible only
when VT Switch Mode is disabled.
Vsc2 18 37 Unused
,LN 9
This single-phase voltage is recovered from the phase(s) assigned in the IED setting. It may be assigned to Van, Vbn, Vcn, Vab, Vbc or Vca in the
settings. The IEC 61850-9-2LE interface uses the appropriate phase(s) from the Sampled Value frame received on the Logical Node configured
for Vsc2. The IED raises an Illegal Channel Map alarm if the same Logical Node is assigned to both [VA VB VC] and Vsc2. This cell is visible only
when VT Switch Mode is disabled.
VA1 VB1 VC1 18 38 LN1
,LN 9
One of the two Sampled Value inputs for selection of three-phase voltage for use by functions in the relay, such as distance protection or
overvoltage protection. This cell is visible only when VT Switch Mode is enabled.
VA2 VB2 VC2 18 39 Unused
,LN 9
The second of the two Sampled Value inputs for selection of three-phase voltage for use by functions in the relay, such as distance protection or
overvoltage protection. This cell is visible only when VT Switch Mode is enabled.
Vcs1 18 3A Unused
,LN 9
Px4x-92LE--TM-EN-1.1 21
Description
The first of the three Sampled Value inputs for selection of single-phase voltage for check synchronising function. This cell is visible only when VT
Switch Mode is enabled.
This single-phase voltage is recovered from the phase(s) assigned in the IED setting. It can be assigned to Van, Vbn, Vcn, Vab, Vbc or Vca in the
settings. The IEC 61850-9-2LE interface uses the appropriate phase(s) from the Sampled Value frame. These are received on the Logical Node
which is configured for Vcs1.
Vcs2 18 3B Unused
,LN 9
The second of the three Sampled Value inputs for selection of single-phase voltage for check synchronising function. This cell is visible only when
VT Switch Mode is enabled.
Vcs3 18 3C Unused
,LN 9
The third Sampled Value inputs for selection of single-phase voltage for check synchronising function. This cell is visible only when VT Switch
Mode is enabled.
MUs Delay Search 18 41 No No, Yes
MUs Delay Max 18 42 0
When sampled values are received at the IED from different Merging Units, they may not arrive simultaneously due to differences in Merging Unit
performance or different network path delays. This setting specifies the maximum time-delay expected, starting at the reception of the sampled
value frame from the "first" Merging Unit to the reception of the sampled value frame from the last Merging Unit for each sample count. Signal
processing starts at the end of the Merging Unit delay and if a frame is not received in that specified time, a synchronisation alarm appears.
Trust Ques Data 18 43 000000 0 or 1 for each flag
This setting specifies how the Sampled Values are processed by the IED when the associated Quality tag is Questionable. There are six binary
flags (0 = No, 1 = Yes) which can be set by the user, corresponding to the data quality attributes Out of Range, Bad Reference, Oscillatory,
Old Data, Inconsistent and Inaccurate. Questionable data is treated as invalid if the flag is 0. To process the data as good samples, the flag is
changed to 1. The setting is common to all Logical Nodes in service.
Loss Rate Level 18 44 10%
This setting is related to Process Bus network performance, in particular, the possibility of loss of samples. The set threshold is an upper limit for
the loss of Sampled Values from any of the Logical Nodes configured in the IED, calculated every cycle. If the loss rate level exceeds the set
value, the IED generates the 9-2 Sample Alarm and the related protection functions are inhibited. 1.25% corresponds to the loss of 1 out of the
80 samples expected every cycle, averaged over one second. The loss rate calculation and threshold check is performed independently for each
Logical Node configured.
SAV Absence 18 51 000000000 0 or 1 for each flag
This is a data cell with 9 binary flags. It indicates the presence or absence of Sampled Values from each of the Merging Units the IED is
communicating with. There is a maximum of 9 Logical Nodes. The cell data for each Logical Node is continuously refreshed.
0: Sampled Values being received from the Merging Unit.
1: No Sampled Values being received from the Merging Unit.
SAV No SmpSynch 18 52 000000000 0 or 1 for each flag
This is a data cell with 9 binary flags. It indicates the healthiness of the Sampled Values being received from each of the Merging Units configured:
0: Sampled Values received are synchronised and any loss of samples is within acceptable limits.
1: Sampled Values received are not synchronised (Setting : Synchro Alarm) or the Sampled Value delay exceeds the acceptable value (Merging
Unit Delay setting). The IED raises a SAV No SmpSynch when any one of the binary flags is 1.
SAV Test 18 53
00000000 00000000
00000000
0 or 1 for each flag
22 Px4x-92LE--TM-EN-1.1
Description
This is a data cell with 24 binary flags. It indicates the status of the IEC 61850 Test mode flag for each analogue channel processed by the IED
(eg: VA, the A-phase voltage). The channel assignment depends on the IED.
SAV Questionable 18 54
00000000 00000000
00000000
This is a data cell with 24 binary flags. It indicates the status of the IEC 61850 Quality attribute Questionable in the Sampled Value frames for
each of the analogue channels. The channel assignment depends on the IED.
SAV Invalid 18 55
00000000 00000000
00000000
This is a data cell with 24 binary flags. It indicates the status of the IEC 61850 Quality attribute Invalid in the Sampled Value frames for each of
the analogue channels. The channel assignment depends on the IED.
Frame Loss Data 18 70
This column contains all the configure/setting measurement parameters relative to frame loss data.
Frame Loss Rate 18 71 Enabled Disabled, Enabled
Enables the frame loss rate counter
LN1 LN9
Loss Rate Sec
18 72 7A 0
These data cells indicate the percentage of SV frames missing during the past second, for LNx
LossRate Reset 18 90 No No, Yes
Resets the frame loss rate counter
Reset Time 18 91 0
This data cell is the time stamp of the most recent instance of Frame Loss Rate counter
LN1 LN9 FrmLoss Cuml 18 92 9A 0
These data cells indicate the number of frames lost since last reset for LN 19; the most recent reset time available in the IED menu.
LN1 - LN9 Error Second 18 B1 to 9 0
Frame Error Seconds is a cumulative value since the last reset per LN. If the Frame Loss Rate exceeds 1.25% (one sample per cycle on average
for one second) the IED records this as an Error Second.
VA VB VC 18 D1
VA1 VB1 VC1, VA2 VB2
VC2
This data cell displays the three-phase voltage input in use by the relay. This cell is visible only when VT Switch Mode is enabled.
Vsc1 18 D2 Vcs1, Vcs2, Vcs3
This data cell displays the single-phase voltage in use by the System Check function as Vsc1. This cell is visible only when VT Switch Mode is
enabled.
Vsc2 18 D3 Vcs1, Vcs2, Vcs3
This data cell displays the single-phase voltage in use by the System Check function as Vsc2. This cell is visible only when VT Switch Mode is
enabled.
2.2 CHANNEL MAPPINGS FOR SAV TEST, SAV QUESTIONABLE, SAV
INVALID
These signals correspond to the analogue channels in a conventional MiCOM IED. The channel name
appears on the IED display against each bit.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
VA VB VC VSC1 IA1 IB1 IC1 IM INSEN IA2 IB2 IC2 VSC2
Px4x-92LE--TM-EN-1.1 23
3 P645
3.1 SETTINGS TABLE
Description
IEC 61850-9.2LE 18 00
Synchro Alarm 18 03 Local 1PPS No SYNC CLK, Local 1PPS, Global 1PPS
no synchronisation.
Value frames.
9-2 Test Mode 18 04 Test Blocked Test Blocked, Test Ignored, Test Only
(9-2 Sample Alarm).
LN Count 18 11 8
model dependent.
Units.
24 Px4x-92LE--TM-EN-1.1
Description
IA1 IB1 IC1 - IA5 IB5 IC5 18 31 - 35 LN1 - 5 Unused, LN1, LN2, LN3,,LN 8
Three-phase current inputs to the IED for HV, LV and TV windings.
IY1 - IY3 18 36 - 38 LN6 - LN8 Unused, LN1, LN2, LN3,,LN 8
The single-phase current signals IY1, IY2 and IY3 for REF function. These are recovered from the neutral current in the IEC 61850-9-2LE frame of
the assigned LN
VA VB VC 18 39 LN1 Unused, LN1, LN2, LN3,,LN 8
The three-phase voltage input [VA VB VC] used for overflux element W1. The IED raises an Illegal Channel Map alarm if the same Logical Node
is assigned to both [VA VB VC] and VFLUX.
VFLUX 18 3A LN2 Unused,LN1, LN2, LN3,,LN 8
The single phase input VFLUX is used for overflux element W2. The IED raises an Illegal Channel Map alarm if the same Logical Node is
assigned to both [VA VB VC] and VFLUX.
1: Sampled Values received are not synchronised (Setting : Synchro Alarm) or the Sampled Value delay exceeds the acceptable value (Merging
Unit Delay setting). The IED raises a 9-2 Sample Alarm when any one of the binary flags is 1.
SAV Test 18 53
00000000 00000000
00000000
00000000 00000000
00000000
Px4x-92LE--TM-EN-1.1 25
Description
SAV Invalid 18 55
00000000 00000000
00000000
LN1 - LN8
LossRate Sec
18 72 - 79 0
These data cells indicate the percentage of SV frames missing during the past second, for LNx.
Reset Time 18 91 0
This data cell is the time stamp of the most recent instance of Frame Loss Rate counter.
LN1 LN8 FrmLoss Cuml 18 92 - 99 0
These data cells indicate the number of frames lost since last reset for LN 18, the most recent reset time available in the IED menu.
INVALID
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
VA VB IY1 IY2 IY3 IA2 IB2 IC2 IA1 IB1 IC1 VC VFLUX IA5 IB5 IC5 IA4 IB4 IC4 IA3 IB3 IC3
26 Px4x-92LE--TM-EN-1.1
4 P746
4.1 SETTINGS TABLE
Description
IEC 61850-9.2LE 18 00
Synchro Alarm 18 03 Local 1PPS No SYNC CLK, Local 1PPS, Global 1PPS
no synchronisation.
Value frames.
9-2 Test Mode 18 04 Test Blocked Test Blocked, Test Ignored, Test Only
(9-2 Sample Alarm).
LN Count 18 11 6
model dependent.
Units.
Px4x-92LE--TM-EN-1.1 27
Description
IA1 IB1 IC1 - IA6 IB6 IC6 18 31 - 36 LN1 - 6 Unused, LN1, LN2, LN3,,LN 8
Three-phase current inputs to the IED for busbar protection and backup functions.
VA VB VC 18 39 LN1 Unused,LN1, LN2, LN3,,LN 8
Three-phase voltage input [VA VB VC].
1: Sampled Values received are not synchronised (Setting :Synchro Alarm) or the Sampled Value delay exceeds the acceptable value (Merging
Unit Delay setting). The IED raises a 9-2 Sample Alarm when any one of the binary flags is 1.
SAV Test 18 53
00000000 00000000
00000000
00000000 00000000
00000000
SAV Invalid 18 55
00000000 00000000
00000000
28 Px4x-92LE--TM-EN-1.1
Description
LN1 - LN8
LossRate Sec
18 72 - 79 0
These data cells indicate the percentage of SV frames missing during the past second, for LNx
Reset Time 18 91 0
This data cell is the time stamp of the most recent instance of Frame Loss Rate counter
LN1 LN8 FrmLoss Cuml 18 92 - 99 0
These data cells indicate the number of frames lost since last reset for LN 18, the most recent reset time available in the IED menu.
INVALID
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
VA VB IA3 IB3 IC3 IA2 IB2 IC2 IA1 IB1 IC1 VC IA6 IB6 IC6 IA5 IB5 IC5 IA4 IB4 IC4
Px4x-92LE--TM-EN-1.1 29
5 VIRTUAL CT AND VT RATIO SETTINGS
The Sampled Value frames are primary measurements. These come from Merging Units (MU) connected to
conventional CTs and VTs or Non-Conventional Instrument Transformers (NCITs). Alternatively they may
come directly from NCITs. The IED algorithms are typically based on secondary values. If primary values are
needed, they are calculated by the IED based on set CT or VT ratio(s).
The amplitudes for 1A CT inputs are limited to 64 A secondary. The amplitudes for 5A CT inputs are limited
to 320 A secondary. The VT secondary is limited to 200 V phase-to-earth. Therefore it is necessary to set
appropriate CT and VT ratios for the protection functions to operate correctly. The instrument transformer
ratios are set in the IED menu CT AND VT RATIOS, which is common to both conventional and IEC
61850-9-2LE IEDs.
Measurement from a MU connected to a CT
As this has a real CT ratio, set the real primary CT ratio.
Direct measurement from an NCIT
There is no physical CT ratio. Set the CT ratio high enough so the maximum primary current (maximum fault
level) when converted to secondary is not clamped.
For example if the maximum primary current is 50 kA:
If the CT ratio is set to 1000:1 the converted secondary current is up to 50 A. This is less than 64 A so
is acceptable.
If the CT ratio is set to 500:1 the converted secondary current is up to 100 A. This is above 64 A so is
not acceptable.
30 Px4x-92LE--TM-EN-1.1
OPERATION
CHAPTER 4
Chapter 4 - Operation Px4x-92LE
32 Px4x-92LE--TM-EN-1.1
1 CHAPTER OVERVIEW
This chapter provides details of how the product functions.
Chapter Overview 33
IEC 61850 34
Data Resampling 36
Sampled Value Alignment 37
Data Quality 38
Process Bus Performance 41
VT Switching 42
IED Alarms 43
P546 44
Px4x-92LE Chapter 4 - Operation
Px4x-92LE--TM-EN-1.1 33
2 IEC 61850
This section describes how the IEC 61850 standard is applied to the Px40 platform. It is not a description of
the standard itself. The level at which this section is written assumes that the reader is already familiar with
the IEC 61850 standard.
IEC 61850 is the international standard for Ethernet-based communication in substations. It enables
integration of all protection, control, measurement and monitoring functions within a substation, and
additionally provides the means for interlocking and inter-tripping. It combines the convenience of Ethernet
with the security that is so essential in substations today.
2.1 BENEFITS OF IEC 61850
The standard provides:
Standardized models for IEDs and other equipment within the substation
Standardized communication services (the methods used to access and exchange data)
Standardized formats for configuration files
Peer-to-peer communication
The standard adheres to the requirements laid out by the ISO OSI model and therefore provides complete
vendor interoperability and flexibility on the transmission types and protocols used. This includes mapping of
data onto Ethernet, which is becoming more and more widely used in substations, in favour of RS485. Using
Ethernet in the substation offers many advantages, most significantly including:
Ethernet allows high-speed data rates (currently 100 Mbps, rather than 10s of kbps or less used by
most serial protocols)
Ethernet provides the possibility to have multiple clients
Ethernet is an open standard in every-day use
There is a wide range of Ethernet-compatible products that may be used to supplement the LAN
installation (hubs, bridges, switches)
2.2 IEC 61850 INTEROPERABILITY
A major benefit of IEC 61850 is interoperability. IEC 61850 standardizes the data model of substation IEDs,
which allows interoperability between products from multiple vendors.
An IEC 61850-compliant device may be interoperable, but this does not mean it is interchangeable. You
cannot simply replace a product from one vendor with that of another without reconfiguration. However the
terminology is pre-defined and anyone with prior knowledge of IEC 61850 should be able to integrate a new
device very quickly without having to map all of the new data. IEC 61850 brings improved substation
communications and interoperability to the end user, at a lower cost.
2.3 INTRODUCTION TO IEC 61850-9-2LE
IEC 61850-9-2LE defines Process Bus communications between the different components of the substation
automation system. The IEC 61850-9-2LE interface allows MiCOM IEDs to communicate with the Process
Bus and receive IEC 61850-9-2LE data from Merging Units. Analogue Merging Units digitise analogue
values from conventional CTs and VTs, replacing analogue inputs. This provides safer and more economical
cross-site communication using fibre optics. It also allows the IED to receive current and voltage sampled
data through Digital Merging Units from non-conventional instrument transformers such as optical and
Rogowski devices.
The Alstom Grid implementation has been designed to be especially resilient and reliable in the presence of
interference, such as latency, jitter and missing or suspect data.
34 Px4x-92LE--TM-EN-1.1
E01034
Va
Vb
Vc
Ia
Ib
Ic
CPU
CT/VT
input
module
Sampling
IED
Figure 3: MiCOM IED with conventional CT and VT inputs
Va
Vb
Vc
Ia
Ib
Ic
Analogue
Merging
Unit
NCIT Va
NCIT Vb
NCIT Vc
NCIT Ia
NCIT Ib
NCIT Ic
Ethernet
Switch
IED with
IEC 61850 9-2LE
Interface
E01032
Digital
Merging
Unit
Figure 4: IED with IEC 61850 9-2LE inputs
Px4x-92LE--TM-EN-1.1 35
3 DATA RESAMPLING
The IEC 61850-9-2LE interface receives 80 Sampled Values per cycle from the Process Bus. This is the
same for both 50 and 60 Hz. The IEC 61850-9-2LE interface then resamples these Sampled Values to make
the data appear the same to the IED as analogue signals would do on its normal inputs from CTs and VTs.
The resampling frequency depends on the IED:
P446, P546, P841B - 48 samples/cycle
P645, P746 - 24 samples/cycle
The IEC 61850-9-2LE interface also tracks the supply frequency because the Sampled Values from the
Process Bus network are fixed at 4000 samples/sec for 50Hz and 4800 samples/sec at 60 Hz.
E01034
Va
Vb
Vc
Ia
Ib
Ic
CPU
CT/VT
input
module
Sampling
IED
Figure 5: Data sampling using CTs/VTs and an input board
IED
E01035
Va
Vb
Vc
Ia
Ib
Ic
Merging
Unit
IEC 61850 9-2LE
Interface
CPU
80 samples
per cycle
Process Bus
Resampling
Figure 6: Data sampling using an IEC 61850-9-2LE interface
36 Px4x-92LE--TM-EN-1.1
4 SAMPLED VALUE ALIGNMENT
Sampled Value frames from different Merging Units on the Process Bus may not arrive at the same time at
the IED. The transmission delay depends on the background Ethernet traffic and how many switches are
used in the Process Bus network.
Transmission delays do not usually matter for functions such as three-phase overcurrent protection where
current signals are all received in a single frame. However, a function such as distance protection uses
voltage and current signals which may be from different merging units with different transmission delays. The
IEC 61850-9-2LE interface synchronises the voltage and current samples that are sent to the IEDs distance
protection function. The IED then uses the Merging Unit Delay setting, which is set to the maximum
expected delay between the first and last Sampled Value.
The following examples show how you would need to set the delay.
If the IED receives one Logical Node only, no delay is needed so it operates correctly with a Merging
Unit Delay setting of '0ms'.
If the IED receives several Logical Nodes at the same time, no delay is needed so it operates correctly
with a Merging Unit Delay setting of '0ms'.
If the IED receives several Logical Nodes but not at the same time, set the Merging Unit Delay to an
appropriate non-zero value for the IED to operate correctly.
If all the Logical Nodes configured in the IED are not received during the Merging Unit Delay time, an
alarm is raised.
To set the merging unit delay during commissioning, set MUs Delay Search to 'Yes'. The IED then monitors
the Sampled Value frames received for the next two seconds and displays the maximum delay between
identical samples.
Px4x-92LE--TM-EN-1.1 37
5 DATA QUALITY
Any degredation in the measurement or transmission of Sampled Values means that the protection function
of the IED cannot operate correctly. Therefore to be able to detect questionable data, the IEC 61850 protocol
assigns quality flags to each channel in the Sampled Value frame.
Data frames from a typical Logical Node with four voltages and four currents [VA, VB, VC, VN, IA, IB, IC, IN]
have quality flags for each of the channels. The IED adapts the behaviour of protection functions according
to the quality flags.
The front panel of the IED shows the quality flags for each of the analogue channels configured. The number
of analogue channels depends on the IED type; unused channels appear as 0.
IEDs which have an IEC 61850-9-2LE interface use the quality flags on Sampled Values. For protection
functions to work correctly, the Sampled Values arriving at the IED should have Good quality, as defined by
the IEC 61850 standard. Samples that have an Invalid or Questionable quality could result in unacceptable
performance from the protection functions.
The way that the IED treats questionable data is user configurable. However, the default setting can be
changed to Trust Questionable Data for one or more specific type, such as Out Of Range. This setting is
common for all Logical Nodes and all channels configured in the IED. It can be used to analyse the impact of
questionable data on the performance of the IED.
A protection function operates normally when all the necessary Sampled Value inputs are available and have
a Good quality flag. When the flag for one or more of the Sampled Value inputs changes to Invalid or
Questionable, the protection function is inhibited. The IED can be configured to ignore the Questionable flag
but the protection function is not inhibited. The protection function returns to Normal state when the quality
flags for all the necessary Sampled Value inputs are Good. The quality flags can change with each sample,
therefore there is a one-cycle transition delay between the Normal and Inhibit states for each protection
function.
5.1 IMPACT OF DATA QUALITY ON PROTECTION FUNCTIONS
In the following tables:
X means the SV input affects the Normal and Inhibit states of the protection function.
# means the protection function is affected where configured to work with this input.
$ means that frequency protection operates if any one current or voltage phase is good quality.
For example, overcurrent protection can be configured as directional, in which case the voltage inputs have
an impact on the function. The quality of the voltage input is not important if the overcurrent is non-
directional.
5.1.1 P446, P546, P841B
The following table shows how Sampled Value errors affect protection functions.
[I
A1
I
B1
I
C1
] [I
A2
I
B2
I
C2
] [V
A
V
B
V
C
] V
SC1
V
SC2
I
N SEN
I
M
Differential
Protection
X # #
Distance
Protection
X # X
Directional
Earth Fault
X # X
Overcurrent
Protection
X # #
38 Px4x-92LE--TM-EN-1.1
[I
A1
I
B1
I
C1
] [I
A2
I
B2
I
C2
] [V
A
V
B
V
C
] V
SC1
V
SC2
I
N SEN
I
M
Negative
Sequence
X # #
Broken
Conductor
X #
Earth Fault
Protection
X # #
REF
Protection
X
SEF
Protection
X
Residual
Overvoltage
X
Voltage
Protection
X
Frequency
Protection
$ $ $
5.1.2 P645
The following table shows how Sampled Value errors affect protection functions.
[
I
A
1

I
B
1

I
C
1
]
[
I
A
2

I
B
2

I
C
2
]
[
I
A
3

I
B
3

I
C
3
]
[
I
A
4

I
B
4

I
C
4
]
[
I
A
5

I
B
5

I
C
5
]
I
Y1
I
Y2
I
Y3
[
V
A

V
B

V
C
]
V
F
L
U
X
Differential
Protection
X # # # X
REF HV
Protection
X # X
REF LV
Protection
# X X
REF TV
Protection
# X # X
Overcurrent HV
Protection
X # #
Overcurrent LV
Protection
# X #
Overcurrent TV
Protection
# X # #
NPS HV
Protection
X # #
NPS LV
Protection
# X #
NPS TV
Protection
# X # #
Earth Fault HV
Protection
# # # #
Earth Fault LV
Protection
# # # #
Earth Fault TV
Protection
# # # # #
Px4x-92LE--TM-EN-1.1 39
[
I
A
1

I
B
1

I
C
1
]
[
I
A
2

I
B
2

I
C
2
]
[
I
A
3

I
B
3

I
C
3
]
[
I
A
4

I
B
4

I
C
4
]
[
I
A
5

I
B
5

I
C
5
]
I
Y1
I
Y2
I
Y3
[
V
A

V
B

V
C
]
V
F
L
U
X
Voltage Protection X
Residual
Overvoltage NVD
X
Overfluxing
Volts/Hz W1
X
Overfluxing
Volts/Hz W2
X
Frequency
Protection
$ $ $ $ $ $ $
5.1.3 P746
The following table shows how Sampled Value errors affect protection functions in the P746 IED.
[
I
A
1

I
B
1

I
C
1
]
[
I
A
2

I
B
2

I
C
2
]
[
I
A
3

I
B
3

I
C
3
]
[
I
A
4

I
B
4

I
C
4
]
[
I
A
5

I
B
5

I
C
5
]
[
I
A
6

I
B
6

I
C
6
]
[
V
A

V
B

V
C
]
Differential Protection # # # # # # #
Overcurrent Terminal 1 X
Earth Fault Terminal 1 X
Dead Zone OC 1 X
Dead Zone OC 2 X
Dead Zone OC 3 X
Dead Zone OC 4 X
Dead Zone OC 5 X
Dead Zone OC 6 X
40 Px4x-92LE--TM-EN-1.1
6 PROCESS BUS PERFORMANCE
Currents and voltages are received by the IED as Sampled Values over the network. Any degradation of the
network means that the protection function of the IED cannot operate correctly.
Ethernet networks sometimes lose frames, so the IED tolerates some loss of samples to ensure availability
of its protection functions. The IED calculates a Frame Loss Rate every cycle for each Merging Unit (Logical
Node) it is communicating with. If the Frame Loss Rate is less than the Loss Rate Level setting, the IED
tolerates network losses of up to three consecutive samples. If the Frame Loss Rate is greater than the Loss
Rate Level setting, the protection functions are temporarily inhibited.
The IED display shows information about Sampled Value losses on the Process Bus for each Logical Node
associated with the IED. This is useful during testing or commissioning to identify and resolve any network
problems which could degrade the protection scheme.
6.1 SAMPLE LOSS DATA
The Sampled Value loss data can be reset manually.
The sample loss data provided are:
LNx Frm Loss Rate Sec: Percentage of SV frames missing during the past second, for LNx
LNx FrmLoss Cuml: Number of frames lost since last reset; the most recent reset time available in the IED
menu.
LNx Error Second: Frame Error Seconds is a cumulative value since the last reset. If the Frame Loss Rate
exceeds 1.25% (one sample per cycle on average for one second) the IED records this as an Error Second.
Px4x-92LE--TM-EN-1.1 41
7 VT SWITCHING
This function is used in the P446, P546 and P841B IEDs which have an IEC 61850-9-2LE interface. It allows
the user to switch the three-phase voltage input between two independent Sampled Value frames while the
IED is in service. This may correspond to two separate voltage transformers in the primary system. The VT
Switch function also allows the single-phase check synchronising voltages to be selected from three
independent Sampled Value frames.
The VT switching function is disabled by default. To enabled it, in the IED menu IEC 61850-9-2LE, select VT
Switch Mode then Enabled.
Three-Phase Voltage Input Switching
The three-phase voltage can be switched between two Sampled Value frames. These are [VA1 VB1 VC1]
and [VA2 VB2 VC2]. The switching is controlled by the status of the DDB VABC Select x. The logic is shown
in the following table.
DDB
VABC Select x VA VB VC Selection
0 VA1 VB1 VC1
1 VA2 VB2 VC2
The change of VT input is accepted only if the DDB status change is effective for a minimum of 20 ms. The
selected three-phase voltage is only displayed when VT Switch Mode is enabled.
Single-Phase Voltage Input Switching
There are two single-phase voltages associated with the System Check function. These are Vsc1 and Vsc2.
The selection of voltage Vsc1 is controlled by the combined status of two DDBs, Vsc1 Select x1 and Vsc1
Select 1x as shown in the following table.
DDB
Vsc1 Select x1
DDB
Vsc1 Select 1x Vsc1 Selection
0 0 Vcs1
0 1 Vcs2
1 0 Vcs3
1 1 Unused
The selection of voltage Vsc2 is controlled by the combined status of two DDBs, Vsc2 Select x1 and Vsc2
Select 1x as shown in the following table.
DDB
Vsc2 Select x1
DDB
Vsc2 Select 1x Vsc2 Selection
0 0 Vcs2
0 1 Vcs3
1 0 Vcs1
1 1 Unused
The selected single-phase voltages are only displayed when VT Switch Mode is enabled.
42 Px4x-92LE--TM-EN-1.1
8 IED ALARMS
IEDs that use the IEC 61850-9-2LE interface have additional alarms.
Illegal Channel Map Alarm (9-2 Cfg Alarm)
This alarm highlights discrepancies in assignments of analogue channels in the IED. For example, there are
two sets of three-phase current inputs in the P546; if the user has assigned both the current inputs to the
same Logical Node, the IED raises an Illegal Channel Map Alarm. For further information see the
Applications chapter.
Quality Alarm (9-2 Sample Alarm)
This alarm is raised if any of the following conditions exist:
One or more of the Sampled Value frames received are not synchronised as required by the IED
configuration.
One or more of the Sampled Value frames expected are not received.
One or more of the Sampled Value frames received are of Invalid quality.
One or more of the Sampled Value frames received are of Questionable quality and the IED is
configured not to accept such Sampled Value frames.
One or more of the Sampled Value frames received has a test flag, and the IED is configured to inhibit
protection functions when receiving frames with a test flag.
One or more of the Sampled Value frames received does not have a test flag, and the IED is
configured to receive only frames with a test flag.
Sampled Values received have a nominal frequency different to that set in the IED.
The secondary current or voltage exceeds the acceptable limit.
Px4x-92LE--TM-EN-1.1 43
9 P546
9.1 CURRENT DIFFERENTIAL FUNCTION
The feeder differential function uses a P546 at each end of the protected circuit. It can be configured in two-
ended or three-ended schemes depending on the application. The IEDs send local current information to the
remote ends. The decisions whether to trip are made locally after calculating the bias and differential
currents based on the received currents.
For the current differential function to work correctly, Sampled Values from each end of the feeder must be
synchronised to correspond to the same time instant. This also applies to any other quantities derived from
samples such as Fourier values. This is essential to properly evaluate bias and differential currents.
Otherwise it could result in false differential currents and unwanted operation of the differential scheme.
In a differential scheme with conventional P546 IEDs, either:
time stamps plus current information are exchanged between the IEDs
all the IEDs in the scheme are synchronised to 1 PPS GPS inputs.
When the IEDs in the scheme have an IEC 61850-9-2LE interface, the synchronisation must account for
delays in receiving Sampled Values over the Process Bus network. This is not important for conventional
IEDs where the primary CTs are directly wired to the IEDs analogue inputs. The following diagram shows
P546 IEDs at both line ends of the Process Bus. The Merging Units and the Sampled Value distribution
networks at End A and End B are independent of each other. Therefore the Sampled Values may arrive at
the P546 IEDs with different delays.
Process Bus
Feeder End A
IEC 61850-9-2LE
IEC 61850
MU 2
IEC 61850
MU 1
IEC 61850
MU 1
IEC 61850
MU 2
IEC 61850
MU 3
Process Bus
IEC 61850-9-2LE
Feeder End B
End to End
Communications
P546 P546
E01036
P594
1 PPS
P594
1 PPS
Figure 7: Two-ended P546 scheme with IEC 61850-9-2LE IEDs at both feeder ends
To synchronise the Sampled Values across multiple P546 IEDs with IEC 61850-9-2LE interfaces, all must be
synchronised using a 1 PPS GPS signal from a P594. This applies for all IEDs in the scheme when one or
more of the feeder ends uses Sampled Value inputs.
44 Px4x-92LE--TM-EN-1.1
The following conditions are also necessary for the feeder differential function to work correctly:
All P546 IEDs in the scheme must work in GPS Synchronised mode and must have 1 PPS GPS
inputs from the P594.
At all line ends, the Merging Units in the feeder differential scheme must use a reference time clock for
synchronisation. For example, IEEE 1588 or GPS synchronised 1PPS.
The GPS sources for the P546 IEDs and the Merging Units must be synchronised as they may not be
common.
The first Sampled Value frame from the Merging Units for each second has a sequence count of 0.
This corresponds to a zero time offset from the start of the second.
The P546 uses the sample count in the Sampled Value frames, plus its own 1PPS GPS synchronisation
input, to calculate delays in the Process Bus. The P546 then phase shifts the current vectors to time-align
them before performing bias and differential currents calculations. The delay is recalculated every second to
adapt to any changes in the Process Bus, enhancing the security of the protection scheme.
IEC 61850
MU 2
IEC 61850
MU 1
P594
End to End
Communications
P546
P546
E01037
P546
1 PPS
P594
1 PPS
P594
1 PPS
Process Bus
IEC 61850-9-2LE
Figure 8: Conventional and non-conventional P546 IEDs combined in a current differential scheme
The current differential scheme is inhibited at all feeder ends if any of the following conditions occur:
The Sampled Value frames received at the P546 are not 1 PPS GPS synchronised.
The 1PPS input to the P546 is not GPS synchronised.
There is a delay of 100 ms or more between the receipt of a Sampled Value frame with SmpCnt 0,
and the 1 PPS input pulse to the P546 indicating the start of the second.
Px4x-92LE--TM-EN-1.1 45
When the GPS synchronisation recovers in any of these cases, the current differential scheme inhibit is
removed on the next occurrence of the SmpCnt 0 in the Sampled Value frames.
The P546 uses a special setting for commissioning tests with IEC 61850-9-2LE using local 1 PPS
synchronisation. See the Configuration chapter.
46 Px4x-92LE--TM-EN-1.1
APPLICATION EXAMPLES
CHAPTER 5
Chapter 5 - Application Examples Px4x-92LE
48 Px4x-92LE--TM-EN-1.1
1 APPLICATION EXAMPLES
This chapter provides typical examples of applications for the product.
In This Chapter
Application Examples 49
Overview 50
P446 51
P546 53
P645 57
P746 59
Bay Architecture 60
Voltage Input Switching 63
Px4x-92LE Chapter 5 - Application Examples
Px4x-92LE--TM-EN-1.1 49
2 OVERVIEW
The IEC 61850-9-2LE interface allows measurement signals to be transferred on a common bus, known as
the Process Bus. These signals may originate from standard CTs and VTs, or from NCITs. Information from
both types of measurement devices is sampled by merging units and is transferred on the Process Bus.
In a fully digital substation, digital interfaces are used for all items of primary plant. This includes the
switchgear such as circuit breakers, isolators and earth switches, in addition to the CTs and VTs. In the
present MiCOM implementation, IEC 61850-8-1 GOOSE messages on the Station Bus port can be used to
receive binary status information from the switchgear and send controls or commands. Additional IEC
61850-8-1 GOOSE messages can be configured in the MiCOM IEDs which use the IEC 61850-9-2LE
interface.
50 Px4x-92LE--TM-EN-1.1
3 P446
The IED which has the the IEC 61850-9-2LE interface also has all the functionality for analogue CT and VT
inputs.
E01048
IEC 61850-9-2LE
IEC 61850-8-1
IEC 61850-8-1 Interface
BUS 1
LINE
LINE
BUS 2
Neutral current
from parallel line
if present
I
M
I
E SEN
V
REF
V
REF
V
I
IED
Figure 9: Overview of functionality
3.1 SAMPLED VALUE DISTRIBUTION
The IED provides up to eight Logical Nodes for receiving the Sampled Values. This allows several different
arrangements of Merging Units in the substation. There are seven analogue input groups on the IED. These
are:
[IA1 IB1 IC1] [IA2 IB2 IC2] [VA VB VC] [INSEN] [IM] [Vsc1] [Vsc2]
In the following diagram, the IED receives Sampled Values from two merging units. The IED has two Logical
Nodes, one receiving the analogue input groups [IA1 IB1 IC1] and [VA VB VC], the other receiving input
groups [IA2 IB2 IC2] and [Vsc1].
Px4x-92LE--TM-EN-1.1 51
Merging
Unit 1
Ethernet
Switch
E01038
Merging
Unit 2
IA1, IB1, IC1
VA, VB, VC
IA2, IB2, IC2
VSC1
IED with
IEC 61850 9-2LE
Interface
Figure 10: IED receiving Sampled Values from two merging units
In the following diagram, the IED receives Sampled Values from four merging units. The number of merging
units can vary depending on application requirements, such as the substation layout and the inputs required
by the IED.
Merging
Unit 3
Ethernet
Switch
E01039
Merging
Unit 4
IA2, IB2, IC2
Vsc1
IM
Vsc2
Merging
Unit 1
Merging
Unit 2
IA1, IB1, IC1
INSEN
VA, VB, VC
IED with
IEC 61850 9-2LE
Interface
Figure 11: IED receiving Sampled Values from four merging units
52 Px4x-92LE--TM-EN-1.1
4 P546
The P546 with the IEC 61850-9-2LE interface is intended for use as a P543, P544, P545 or P546 in
schemes where a Sampled Value interface is required on the protection device. However, unlike the P543
and P545, the P546 can be used on plain feeders only and does not cover transformer feeder applications.
E01048
IEC 61850-9-2LE
IEC 61850-8-1
BUS 1
LINE
LINE
BUS 2
Neutral current
from parallel line
if present
I
M
I
E SEN
V
REF
V
REF
V
I
IED
Figure 12: Overview of P546 functionality
The IED provides up to eight Logical Nodes for receiving the Sampled Values. This allows several different
arrangements of Merging Units in the substation. There are seven analogue input groups on the IED. These
are:
[IA1 IB1 IC1] [IA2 IB2 IC2] [VA VB VC] [INSEN] [IM] [Vsc1] [Vsc2]
In the following diagram, the IED receives Sampled Values from two merging units. The IED has two Logical
Nodes, one receiving the analogue input groups [IA1 IB1 IC1] and [VA VB VC], the other receiving input
groups [IA2 IB2 IC2] and [Vsc1].
Px4x-92LE--TM-EN-1.1 53
Merging
Unit 1
Ethernet
Switch
E01038
Merging
Unit 2
IA1, IB1, IC1
VA, VB, VC
IA2, IB2, IC2
VSC1
IED with
IEC 61850 9-2LE
Interface
Figure 13: IED receiving Sampled Values from two merging units
In the following diagram, the IED receives Sampled Values from four merging units. The number of merging
units can vary depending on application requirements, such as the substation layout and the inputs required
by the IED.
Merging
Unit 3
Ethernet
Switch
E01039
Merging
Unit 4
IA2, IB2, IC2
Vsc1
IM
Vsc2
Merging
Unit 1
Merging
Unit 2
IA1, IB1, IC1
INSEN
VA, VB, VC
IED with
IEC 61850 9-2LE
Interface
Figure 14: IED receiving Sampled Values from four merging units
4.2 CURRENT DIFFERENTIAL SCHEMES
Schemes with IEDs which use the IEC 61850-9-2LE interface can be two or three-ended. This is the same
as with conventional P546 relays. The schemes always require GPS synchronisation with 1 PPS inputs from
P594s to IEDs at all feeder ends.
The IEC 61850-9-2LE standard allows IEDs with Sampled Value inputs to be mixed with IEDs with
conventional inputs. This allows protected feeders to link an existing substation which has conventional
54 Px4x-92LE--TM-EN-1.1
equipment with a substation where the current transformers are all non-conventional or the relays have
Sampled Value inputs.
Process Bus
Feeder End A
IEC 61850-9-2LE
IEC 61850
MU 2
IEC 61850
MU 1
IEC 61850
MU 1
IEC 61850
MU 2
IEC 61850
MU 3
Process Bus
IEC 61850-9-2LE
Feeder End B
End to End
Communications
P546 P546
E01036
P594
1 PPS
P594
1 PPS
Figure 15: Two-ended scheme with Sampled Value unputs
Px4x-92LE--TM-EN-1.1 55
IEC 61850
MU 2
IEC 61850
MU 1
P594
End to End
Communications
P546
P546
E01037
P546
1 PPS
P594
1 PPS
P594
1 PPS
Process Bus
IEC 61850-9-2LE
Figure 16: Three-ended scheme with analogue and Sampled Value unputs
The current differential protection requires GPS 1 PPS synchronisation, and is inhibited if synchronisation is
lost at any one feeder end. Therefore it is recommended that appropriate backup protection is enabled in the
IEDs to ensure coverage of faults if the GPS signal fails. This backup protection should use only Local 1
PPS synchronisation of the Sampled Value inputs.
Note:
Use a P594 with version D firmware to meet the requirements of Local 1 PPS and Global 1 PPS signals for sample
synchronisation.
56 Px4x-92LE--TM-EN-1.1
5 P645
The P645 with the IEC 61850-9-2LE interface is intended for use as a P642, P643 or P645 in applications
where a Sampled Value interface is required. The relay is based on P645 firmware version 03 with MiCOM
P40 Cybersecurity. See the relevant relay's technical manual for descriptions of its protection and non-
protection functions.
E01047
P645
I-HV
V
IN-HV
IN-LV
IN-TV
I-LV
I-TV
I-TV
IEC 61850-9-2LE
IEC 61850-8-1
Figure 17: Overview of P645 functionality
The following diagram shows a typical P645 application for a three-winding transformer. The IED receives
Sampled Values from three different merging units. The HV winding currents and the optional three-phase
voltage input are received from MU1, the LV winding currents from MU2 and the tertiary currents from MU3.
The winding neutral currents, where required for functions such as restricted earth fault, can also be received
through the same merging units.
Px4x-92LE--TM-EN-1.1 57
Merging
Unit 3
Ethernet
Switch
E01042
IA5, IB5, IC5
IY3
Merging
Unit 1
Merging
Unit 2
IA1, IB1, IC1
IY2
VA, VB, VC
IY1
IA3, IB3, IC3 IED with
IEC 61850 9-2LE
Interface
Figure 18: IED receiving sampled from three merging units
Merging
Unit 3
Ethernet
Switch
E01043
Merging
Unit 4
IA3, IB3, IC3
IM
Merging
Unit 1
Merging
Unit 2
IA1, IB1, IC1
IY1
Merging
Unit 5
IA4, IB4, IC4
IA2, IB2, IC2
IA5, IB5, IC5
IY2
IED with
IEC 61850 9-2LE
Interface
Figure 19: IED receiving Sampled Values from five merging units
58 Px4x-92LE--TM-EN-1.1
6 P746
The P746 with the IEC 61850-9-2LE interface is intended for applications where a Sampled Value interface
is required. The IED only supports applications with a maximum of six CT inputs. This is the one-box mode.
The P746 with the IEC 61850-9-2LE interface does not support the three-box mode. The IED is based on
P746 firmware version 03 with MiCOM P40 Cybersecurity. See the relevant relay's technical manual for
descriptions of its protection and non-protection functions.
The following diagram shows a typical P746 application where all six three-phase current inputs are used.
Where required, the optional voltage input can be combined in one of the six merging units shown or it can
use a separate dedicated merging unit.
Merging
Unit 4
Ethernet
Switch
E01044
Merging
Unit 5
IA4, IB4, IC4
Merging
Unit 2
Merging
Unit 3
IA2, IB2, IC2
Merging
Unit 6
IA5, IB5, IC5
IA3, IB3, IC3
IA6, IB6, IC6
Merging
Unit 1
IA1, IB1, IC1
VA, VB, VC
IED with
IEC 61850 9-2LE
Interface
Figure 20: IED receiving sampled from six merging units
Px4x-92LE--TM-EN-1.1 59
7 BAY ARCHITECTURE
IEDs with an IEC 61850-9-2LE interface are intended for general use in substation automation applications.
The following diagram shows an example Ethernet architecture adapted to a substation Process Bus.
The P446 and P546 are used for protection and the C264 is the Bay Controller. This would be typical of
transmission bays. In this example, each IED receives Sampled Values from a separate Analogue Merging
Unit (AMU). Each Merging Unit is connected to a separate CT. the IEDs and AMUs are connected point-to-
point. Point-to-point connections do not need switches but need one Merging Unit for each IED. Alternatively
Sampled Values could be shared from one Merging Unit to several IEDs using an Ethernet Switch.
The diagram also shows a network architecture for digital signals. The IEDs and Digital Merging Units (DMU)
have redundant interfaces such as the IEC 62439 Parallel Redundancy Protocol. The network uses two
Hxxx switches to create two independent LANs. For example, a trip signal or control command from IED 1
reaches DMU 1 through both LANs. This ensures redundancy to trip or control the CB.
In this example, the Sampled Value network is completely independent of the network for IEC 61850-8-1
GOOSE. This is analogous to conventional protection schemes where the AC wiring between CTs, VTs and
IED inputs is fully independent from DC wiring for binary inputs or outputs, and interlocks.
60 Px4x-92LE--TM-EN-1.1
CB
I
E
D

1
P
5
4
6
-
9
-
2
L
E
-
8
-
1

P
R
P
I
E
D

2
P
4
4
6
-
9
-
2
L
E
-
8
-
1

P
R
P
B
C
U
C
2
6
4
-
9
-
2
L
E
-
8
-
1

P
R
P
D
M
U

1
-
8
-
1

P
R
P
A
M
U

1
-
9
-
2
L
E
D
M
U

2
-
8
-
1

P
R
P
H xxx
P594
A
M
U

2
-
9
-
2
L
E
E
A
M
U

3
-
9
-
2
L
E
D
A
B
C
E01049
H xxx
B
D
A
Figure 21: Example of Bay Architecture with IEC 61850-9-2LE IEDs
Key:
A: 1 PPS distribution to the P546 and Analogue Merging Units.
B: Point-to-point connections for Sampled Values.
C: Sampled values for other bay functions such as busbar protection or bay control units.
D: Network with redundancy for tripping or control signals.
E: Status and trips, physical signals.
AMU: Analogue Merging Unit with CT and VT inputs, and an IEC 61850-9-2LE output.
DMU: Digital Merging Unit with binary inputs and outputs, and a redundant IEC 61850-8-1 GOOSE interface.
Hxxx: MiCOM ALSTOM Ethernet switches.
Px4x-92LE--TM-EN-1.1 61
7.1 ARRANGEMENT OF THE STATION AND PROCESS BUSES
The system architecture can be arranged so that different types of information are organised into their
respective groups. For example, GOOSE messages can be sent to one segment (Process Bus) and reports
to another (Station Bus). Segregating the network into segments ensures that Process Bus data and Station
Bus data do not interfere with each other and the bandwidth can be optimised.
The following diagram shows an Ethernet switch which routes the Reports received from the IED to the
clients on the Station Bus. The reports are not present on the Process Bus segment of the network. The
switch filters out the IEC 61850 GOOSE messages that are not relevant for the Station Bus, such as the
switchgear status from the DMU, or trip commands from the IED to the DMU.
For further information on how to filter MAC multicast addresses, see the switch documentation.
H xxx
E
I
E
D
-
9
-
2
L
E
-
8
-
1

P
R
P
F
E01050
Figure 22: Integration of an IED with the Station Bus
Key:
E: Station Bus. Reports, waveform records.
F: Process Bus. IEC 61850 GOOSE.
62 Px4x-92LE--TM-EN-1.1
8 VOLTAGE INPUT SWITCHING
The following diagram shows an example of three-phase voltage switching. In this case the feeders do not
have individual voltage transformers. Therefore the feeder protection uses the voltage available from busbar
voltage transformers for distance protection and other voltage-dependent functions.
Merging Units convert Voltages VT1 and VT2 to Sampled Values. Protection devices can then use the two
independent IEC 61850-9.2LE Sampled Value data streams. In the example, the P446 is configured to
receive both data streams. This is set in the IEC61850-9.2LE setting menu, with the VT Switch Mode
enabled. By default the IED uses VA1 VB1 VC1 for voltage-dependent functions. If VT1 fails, the operator
can switch the voltage input to VA2 VB2 VC2 (VT2). This is done by changing the status of the DDB VABC
Select x.
The check synchronising voltages can be switched. This is useful in breaker-and-a-half schemes or other
busbar arrangements where the VT is used for a voltage check. A feeder may not be on the busbar and may
be on one of the other bays in service when the synchronizing check is needed.
E01051
IEC 61850
Merging Unit 1
IEC 61850
Merging Unit 2
VT1
VT2
SV frame with
VA2 VB2 VC2
SV frame with
VA1 VB1 VC1
To feeder protection P446
Figure 23: Example of three-phase voltage switching
The following diagram shows an application of switching the check synchronizing voltage. VT1 provides the
main three-phase voltage VA VB VC for Feeder 1. The VTs on feeders on the busbar VT2, VT3 and VT4 can
be configured as Vcs1, Vcs2 and Vcs3 respectively. These can be made available to the Feeder 1 protection
as Vsc1/Vsc2 using the appropriate DDBs.
Px4x-92LE--TM-EN-1.1 63
E01052
VT1 VT2 VT3 VT4
FEEDER 1 FEEDER 2 FEEDER 3 FEEDER 4
Figure 24: Application of switching the check synchronizing voltage
64 Px4x-92LE--TM-EN-1.1
SCHEME LOGIC
CHAPTER 6
Chapter 6 - Scheme Logic Px4x-92LE
66 Px4x-92LE--TM-EN-1.1
1 CHAPTER OVERVIEW
Alstom Grid products are supplied with pre-loaded Fixed Scheme Logic (FSL) and Programmable Scheme
Logic (PSL). The FSL schemes cannot be modified. They have been individually designed to suit the model
in question. Each model also provides default PSL schemes, which have also been designed to suit each
model. If these schemes suit your requirements, you do not need to take any action. However, if you want to
change the input-output mappings, or to implement custom scheme logic, you can change these, or create
new PSL schemes using the PSL editor.
This chapter provides details of the in-built FSL schemes and the default PSL schemes.
Chapter Overview 67
Programmable Scheme Logic 68
P446, P546, P841B 69
P645 70
P746 71
Px4x-92LE Chapter 6 - Scheme Logic
Px4x-92LE--TM-EN-1.1 67
2 PROGRAMMABLE SCHEME LOGIC
IEDs using the IEC 61850-9-2LE interface keep all features but have additional PSL settings.
Virtual Inputs and Outputs
IEDs using an IEC 61850-9-2LE interface have additional virtual inputs and virtual outputs, as shown in the
following table. These additional inputs and outputs are triggers for GOOSE messages to and from the IED.
The GOOSE Control Blocks can be configured using the IEC 61850 IED Configurator software tool, which is
part of MiCOM S1 AGILE. The additional inputs and outputs make it easier to apply the IEDs in full Digital
Substations where switchgear status, controls and commands are exchanged as GOOSE messages
between the IEDs and Merging Units.
Standard Virtual
Inputs
Standard Virtual
Outputs
Enhanced Virtual
Inputs
Enhanced Virtual
Outputs
P446 32 32 64 64
P546 32 32 64 64
P645 64 32 64 48
P746 64 32 128 128
P841B 32 32 64 64
Additional DDB Signals
The additional virtual inputs and outputs are mapped as new DDBs in the IEDs PSL. There are also
additional DDB signals linked to the alarms.
68 Px4x-92LE--TM-EN-1.1
3 P446, P546, P841B
3.1 DDB SIGNALS TABLE
Ordinal English Text Source Description
340 9-2 Sample Alarm Software Abnormal state of IEC 61850-9-2LE sample.
341 C Diff Sync Fail Software
The IEC 61850-9-2LE sample Global sync has failed, inhibiting
the current differential function.
342 9-2LE Cfg Alarm Software Error in IEC 61850-9-2LE configuration.
343 Invalid Setting Software
This DDB issues an alarm when Phase Diff is set to 'Enabled' but
GPS Sync is set to 'GPS Disabled'.
991 VABC Select x PSL Switch three-phase voltage between two designated LNs
992 Vsc1 Select x1 PSL Switch Vsc1 between three designated LN Bit 1
993 Vsc1 Select 1x PSL Switch Vsc1 between three designated LN Bit 0
994 Vsc2 Select x1 PSL Switch Vsc2 between three designated LN Bit 1
995 Vsc2 Select 1x PSL Switch Vsc2 between three designated LN Bit 0
1792-1823 Virtual Input 33-64 Software These are additional virtual Inputs.
1824-1855 Quality VIP 33 -64 Software These are additional virtual inputs that provide Quality attributes.
1856-1887 PubPres VIP 33 -64 Software
These are are additional virtual inputs that indicate if the publisher
is present.
1888-1919 Virtual Output33-64 PSL These are additional GOOSE outputs.
Px4x-92LE--TM-EN-1.1 69
4 P645
is present.
1754-1769 Virtual Output33-48 PSL These are additional GOOSE outputs
70 Px4x-92LE--TM-EN-1.1
5 P746
586-599 PubPres VIP 115-128 Software
is present.
951-1007 Quality VIP 65-121 Software These are additional virtual inputs that provide Quality attributes.
1044-1103 Virtual Output 33-92 PSL These are additional GOOSE outputs
is present.
1508-1614 Quality VIP 122-128 Software These are additional virtual inputs that provide Quality attributes.
Px4x-92LE--TM-EN-1.1 71
72 Px4x-92LE--TM-EN-1.1
COMMISSIONING INSTRUCTIONS
CHAPTER 7
Chapter 7 - Commissioning Instructions Px4x-92LE
74 Px4x-92LE--TM-EN-1.1
1 CHAPTER OVERVIEW
Chapter Overview 75
General Guidelines 76
Commissioning Test Equipment 77
Check Connections 78
IED With One Logical Node Configured 79
IED With Two or More Logical Nodes Configured 80
P645, P746 81
P546 82
Px4x-92LE Chapter 7 - Commissioning Instructions
Px4x-92LE--TM-EN-1.1 75
2 GENERAL GUIDELINES
Warning:
Before working on the equipment, check the equipment ratings and read the Safety
Information chapter.
Connect the device to the network. Check the Link and Activity LEDs are functioning. Check the IP address
is correct.
This section shows typical network connections.
76 Px4x-92LE--TM-EN-1.1
3 COMMISSIONING TEST EQUIPMENT
This is a typical list of equipment required for testing the IEC 61850-9-2LE interface in the IED.
IED test kit capable of generating 2 or 3 sets of IEC 61850-9-2LE Sampled Values and GOOSE data
sets.
Or conventional current or voltage source with Merging Unit to generate Sampled Values
Ethernet switch(es)
Fibre optic cables
Specific for P546
GPS synchronisation on the IED test kit which can generate Sampled Value frames with Global 1 PPS
or Local 1 PPS synchronisation. If using Merging Units, they also need GPS synchronisation.
Px4x-92LE--TM-EN-1.1 77
4 CHECK CONNECTIONS
1. De-energise the IED.
2. Visually inspect the connectors and check the external wiring is correct.
Only use the RJ45 port for temporary connections during commissioning tests on the relay. For any
protection scheme tests including field connection to the Merging Units, use the fibre ports. See the Harware
Description chapter.
78 Px4x-92LE--TM-EN-1.1
5 IED WITH ONE LOGICAL NODE CONFIGURED
The settings for the IEC 61850-9-2LE interface are in the IED menu IEC 61850-9.2LE. See the Settings
chapter.
1. If necessary, isolate or block any outgoing trips from the IED. If physical contacts from the IED are
wired in the scheme, from the main IED menu select Test Mode.
2. Connect the IED's IEC 61850-9-2LE port to the Sampled Value source. If necessary this can be routed
through an Ethernet switch.
3. In the IED menu setting IEC 61850-9.2LE > Physical Link, select 'Fibre Optic' for receiving Sampled
Values.
4. Check that the Logical Node name in the IED matches the name in the Sampled Value source (test kit
or Merging Unit). Make any changes in the source Logical Node names. This prevents mismatches in
Logical Node names when the IED is put into service when testing existing schemes.
5. Set the IED Synchro Alarm to 'No SYNC CLK' so the IED accepts Sampled Value frames with or
without synchronisation.
6. Generate Sampled Value frames with the rated current and voltage as required in the IEDs Logical
Node configuration.
7. In the MEASUREMENTS menu, check the magnitudes and phase angles are displayed correctly. The
display may be in primary or secondary values. Also the IEDs CT ratio or VT ratio settings affect the
display. A typical accuracy of 1% can be expected for magnitudes.
8. Change the Logical Node name configured in the test kit. Check the data cell SAV Absence displays
'0' for the Logical Node configured in the IED. Check that all MEASUREMENTS displays for voltage or
current are zero.
9. Depending on the scheme, use the Synchro Alarm setting to return the IED to service. Re-enable the
IED trip outputs. If the RJ45 port was used for testing, change the setting IEC 61850-9.2LE > Physical
Link to 'Fibre Optic'.
Px4x-92LE--TM-EN-1.1 79
6 IED WITH TWO OR MORE LOGICAL NODES CONFIGURED
The settings for the IEC 61850-9-2LE interface are in the IED menu IEC 61850-9.2LE.
1. If necessary, isolate or block any outgoing trips from the IED. If physical contacts from the IED are
wired in the scheme, from the main IED menu select Test Mode.
2. Connect the IED's IEC 61850-9-2LE port to an Ethernet switch, which is connected to the Sampled
Value sources. In the IED menu setting IEC 61850-9.2LE > Physical Link, select 'Fibre Optic' for
receiving Sampled Values.
3. Check that the Logical Node name in the IED matches the name in the Sampled Value source (test kit
or Merging Unit). Make any changes in the source Logical Node names. This prevents mismatches in
Logical Node names when the IED is put into service when testing existing schemes.
4. Set the IED Synchro Alarm to 'Local 1PPS' so the IED accepts Sampled Value frames with local or
global synchronisation.
5. Check that the Sampled Value source (test kit or Merging Unit) is GPS synchronised.
6. Check the receipt of Sampled Value frames one by one for each Logical Node configured in the IED.
Repeat the following steps for each Logical Node, configuring them one by one in the Sampled Value
source(s).
1. Generate Sampled Value frames with the rated current and voltage as required in the IEDs Logical
Node configuration. You can check the receipt of Sampled Value frames for the configured Logical
Node.
2. In the MEASUREMENTS menu, check the magnitudes and phase angles are displayed correctly. The
display may be in primary or secondary values. Also the IEDs CT ratio or VT ratio settings affect the
display. A typical accuracy of 1% can be expected for magnitudes.
3. Change the Logical Node name configured in the test kit. Check the data cell SAV Absence displays
'0' for the Logical Node configured in the IED. Check that all MEASUREMENTS displays for voltage or
current are zero.
If the GPS signal is lost, repeat the following steps for each Logical Node.
1. Check the data cell 9-2 Sample Alarm.
2. Turn off the GPS to the Sampled Value source and turn it on again. Binary flags for respective Logical
Node should indicate '1' for loss of GPS and return to '0' when the GPS is healthy.
3. Depending on the scheme, use the Synchro Alarm setting to return the IED to service. Re-enable the
IED trip outputs. If the RJ45 port was used for testing, change the setting IEC 61850-9.2LE > Physical
Link to 'Fibre Optic'.
80 Px4x-92LE--TM-EN-1.1
7 P645, P746
7.1 DIFFERENTIAL PROTECTION FUNCTION TESTING
In conventional IEDs, differential protection such as transformer differential protection can be tested using a
single three-phase current source. When testing IEDs with an IEC 61850-9-2LE interface, the test equipment
should be able to generate at least two Logical Nodes. If the IEDs receive Sampled Value frames
corresponding to one configured Logical Node only, a 9-2 Sample Alarm is raised. Single end infeed cases
can be simulated by making the current magnitudes zero in one of the Logical Nodes.
Px4x-92LE--TM-EN-1.1 81
8 P546
8.1 COMISSIONING THE GPS FUNCTIONALITY
The P546 needs a 1PPS GPS input to function correctly. See the IED manual for GPS synchronisation tests.
Use a P594 with version D firmware to comply with IEC 61850-9-2LE requirements for Local 1PPS and
Global 1PPS signals.
8.1.1 STRENGTH OF P594 OPTICAL SIGNAL AT IED
1. Put the P594 in Test Cycle Mode. See the P594 manual.
2. Check the optical fibre cable to the P594 transmitter is connected corrrectly.
3. Disconnect the other end of the cable from the IED and measure the received signal strength.
4. Record the value. It should be -16.8 dBm to -25.4 dBm.
5. Reconnect the optical fibre to the IED.
8.1.2 CHECKING THE GPS SYNCHRONISATION SIGNAL AT THE IED
1. In the P594 menu, set Test Cycle Mode to 'Disable'.
2. Connect the transmit fibre from the P594 to the IED's GPS port.
3. At the IED, set PROT COMMS/IM64 > GPS Sync Enabled to 'Enable'. This enables GPS
synchronisation.
4. Select MEASUREMENTS 4 > Channel Status. If the IED receives the GPS synchronisation signal,
the display reads **11******** (where * is a dont care state for this test). This means both the Local
GPS and Remote GPS are received.
5. To check the GPS failure condition, disconnect the fibre from the P594 and check the display reverts
to **00********.
6. Reconnect the fibre and check the display reads **11********.
8.1.3 COMMISSIONING MODE
Global synchronisation is needed for a current differential scheme to function correctly. The protection
function is blocked if global synchronisation is not present. As IED test kits may not be able to generate
Sampled Value frames with global synchronisation, the IED has a commissioning mode which allows the
differential function to be tested with local synchronisation alone.
1. In the COMMISSIONING menu, set SAV Test Mode (0F19) to '1 = Local Sync Only'. The current
differential protection function then operates for Sampled Value frames received with both Local 1
PPS and Global 1 PPS synchronisation.
2. Test the current differential protection function using a test kit synchronised to GPS, sending Sampled
Value frames with Local 1 PPS synchronisation.
3. When the commissioning tests are complete, set the SAV Test Mode to '0 = Disabled' before the IED
is returned to service. The current differential protection operates only with Global 1 PPS
synchronisation.
4. Check the Merging Unit's maximum delay and if necessary adjust the Merging Unit's delay setting.
82 Px4x-92LE--TM-EN-1.1
TECHNICAL SPECIFICATIONS
CHAPTER 8
Chapter 8 - Technical Specifications Px4x-92LE
84 Px4x-92LE--TM-EN-1.1
1 CHAPTER OVERVIEW
This chapter describes the technical specifications of the product.
Chapter Overview 85
Interfaces 86
Px4x-92LE Chapter 8 - Technical Specifications
Px4x-92LE--TM-EN-1.1 85
2 INTERFACES
2.1 100 BASE FX TRANSMITTER CHARACTERISTICS
Parameter Sym Min. Typ. Max. Unit
Output Optical Power BOL 62.5/125
m
NA = 0.275 Fibre EOL
PO
-19
-20
-16.8 -14 dBm avg.
Output Optical Power BOL 50/125 m
NA = 0.20 Fibre EOL
PO
-22.5
-23.5
-20.3 -14 dBm avg.
Optical Extinction Ratio
10
-10
%
dB
Output Optical Power at Logic "0"
State
PO -45 dBm avg.
Conditions: TA = 0C to 70C, VCC = 4.75 V to 5.25 V
2.2 100 BASE FX RECEIVER CHARACTERISTICS
Parameter Sym Min. Typ. Max. Unit
Input Optical Power Minimum at
Window Edge
PIN Min. (W) -33.5 31 dBm avg.
Input Optical Power Minimum at
Eye Center
PIN Min. (C) -34.5 -31.8 Bm avg.
Input Optical Power Maximum PIN Max. -14 -11.8 dBm avg.
Conditions: TA = 0C to 70C, VCC = 4.75 V to 5.25 V
2.3 ETHERNET PORT COPPER
Ethernet port (copper)
Main Use Service port only. Not for permanent connection.
Standard IEEE 802.3 10BaseT/100BaseTX
Connector RJ45
Cable type Screened twisted pair (STP)
Isolation 1.5 kV
Supported Protocols IEC 61850
Constraints Maximum cable length 10m
Chapter 8 - Technical Specifications Px4x-92LE
86 Px4x-92LE--TM-EN-1.1
WIRING DIAGRAMS
APPENDIX A
Appendix A - Wiring Diagrams Px4x-92LE
88 Px4x-92LE--TM-EN-1.1
1 APPENDIX OVERVIEW
This chapter contains the wiring diagrams for all possible situations.
Appendix Overview 89
P446 with IEC 61850-9-2LE Interface Configuration 1 90
P841B with IEC 61850-9-2LE Interface Configuration 1 115
Px4x-92LE Appendix A - Wiring Diagrams
Px4x-92LE--TM-EN-1.1 89
2 P446 WITH IEC 61850-9-2LE INTERFACE CONFIGURATION 1
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W02334
Figure 25: P446 distance 80TE with NCIT 24 inputs and 32 outputs. Part 1 of 2
90 Px4x-92LE--TM-EN-1.1
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1
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1
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8
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7
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5
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4
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3
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1
4
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9
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1
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1
3
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1
4
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1
7
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1
6
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5
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8
M
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4
4
6
(
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C
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F
A
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2

T
R
I
P
1
0
P
4
4
6
0
4
-
2
W02335
Figure 26: P446 distance 80TE with NCIT 24 inputs and 32 outputs. Part 2 of 2
Px4x-92LE--TM-EN-1.1 91
1
.

F
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2
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0
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6
R
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7
R
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A
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8
N
1
5
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8
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1
7
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6
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2
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4
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1
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2
R
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3
R
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4
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6
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8
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7
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4
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5
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1
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2
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3
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1
78 2456 3 1
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B
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1
0
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4
4
6
0
5
-
1
W02336
Figure 27: P446 distance 80TE with NCIT 24 inputs, 8 standard outputs and 12 high-break outputs.
Part 1 of 2
92 Px4x-92LE--TM-EN-1.1
(
P
A
R
T
)
M
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C
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P
4
4
6
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7
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1
8
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5
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1
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1
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3
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1
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8
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9
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5
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6
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7
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3
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4
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1
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2
D
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1
8
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1
5
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1
6
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1
7
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1
4
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1
3
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1
1
N
1
2
R
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8
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6
R
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7
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1
3
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1
2
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1
1
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1
4
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4
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7
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9
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8
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6
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5
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3
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1
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4
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9
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1
8
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1
7
R
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1
6
R
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1
5
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94 Px4x-92LE--TM-EN-1.1
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Part 2 of 2
Px4x-92LE--TM-EN-1.1 95
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7
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7
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6
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5
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1
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P
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.

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2
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1
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9
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1
5
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1
6
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1
3
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1
4
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+
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8
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7
C
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1
5
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4
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1
8
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1
7
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1
6
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L
A
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1
4
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L
A
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1
3
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A
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1
5
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A
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1
6
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L
A
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1
8
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A
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1
7
R
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L
A
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2
0
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1
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2
2
R
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A
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2
3
R
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1
9
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9
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1
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1
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1
3
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1
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1
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6
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8
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7
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5
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1
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1
7
M
1
8
M
1
6
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1
4
M
1
5
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1
3
M
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1
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1
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5
4
6

(
P
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4
R
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6
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3
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1
0
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1
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-
+
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9
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8
-
+
O
P
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5
O
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T
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6
O
P
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4
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7
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6
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- -
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4
G
5
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2
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1
+
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6
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4
8
5
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2
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1
8
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1
7
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1
8
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1
7
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7
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2
8
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2
9
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3
0
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3
1
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1
0
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1
4
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1
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1
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7
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9
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6
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2
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4
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3

R
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A
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5
R
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4
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7
R
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6
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9
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1
1
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1
0
R
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A
Y

1
2
N
1
6
M
8
M
9
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7
M
5
M
6
M
4
M
2
M
3
M
1
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1
8
N
1
7
N
1
0
N
1
3
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1
5
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1
4
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2
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1
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7
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9
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8
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W
A
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1
1
.

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.

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(
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(
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1
78 2456 3 1
R
J
4
5
R
X
-
R
X
+
T
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+
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1
0
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B
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9
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2

L
E
S
K
6
1
0
P
5
4
6
0
7
-
1
Figure 31: P546 current differential 80TE with NCIT 24 inputs and 32 outputs. Part 1 of 2
96 Px4x-92LE--TM-EN-1.1
S
E
E

N
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T
E

1
S
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1
F
1
7
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:
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1
8
O
P
T
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1
8
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M
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2
4
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3
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2
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1
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0
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1
9
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O
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1
7
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O
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M
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E
8
E
1
3
+ +- -
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6
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1
4
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5
+ - -+ +
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1
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1
2
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9
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5
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1
6
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4
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3
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2
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1
1
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1
0
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9
C
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8
O
P
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7
F
6
+ - + - -+
F
1
4
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1
6
F
1
5
F
1
2
F
1
3
+ - -+ +
F
1
0
F
1
1
F
9
F
7
F
8
+- - + -
F
5
F
4
F
3
F
2
F
1
+ +- -
G
1
6
G
1
8
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1
7
G
1
4
G
1
5
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2
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6
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5
O
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4
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3
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1
+++ - - +
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1
1
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1
3
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1
2
G
8
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9
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1
0
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5
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6
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7
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3
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4
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2
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1
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1
7
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1
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1
8
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3
2
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2
9
R
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3
1
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0
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2
7
R
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2
8
K
1
2
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1
5
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1
7
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1
6
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1
4
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1
3
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8
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2
4
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6
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2
5
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2
2
R
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2
3
K
4
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5
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3
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2
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1
8
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1
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1
6
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1
5
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1
7
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1
2
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1
3
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1
4
R
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L
A
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2
0
R
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1
R
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1
8
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1
7
R
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1
9
R
E
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1
6
L
5
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9
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1
0
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1
1
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6
L
7
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8
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2
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3
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4
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1
8
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1
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M
i
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5
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6
(
P
A
R
T
)
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5
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4
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1
3
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1
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1
2
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1
4
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5
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6
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7
R
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M
2
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7
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1
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R
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C
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R
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C
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4
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8
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6
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2
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1
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1

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A
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1

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T
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2

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2

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2

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R
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1

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R
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1

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R
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P

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C
B
1

T
R
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C
N
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1

T
R
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C
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1

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1

F
A
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1

T
R
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G
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N
E
R
A
L
A
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A
R
M
S
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G
N
A
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L
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F
A
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6
4

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T
R
I
P
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Z
1
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T
T
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1
0
P
5
4
6
0
7
-
2
Figure 32: P546 current differential 80TE with NCIT 24 inputs and 32 outputs. Part 2 of 2
Px4x-92LE--TM-EN-1.1 97
E
8
O
P
T
O

2
0
C
O
N
N
E
C
T
I
O
N
C
O
M
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2
4
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2
3
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T
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2
2
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2
1
E
1
8
+
E
1
5
E
1
7
E
1
6
+
-
E
1
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2
-
+
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1
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9
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O

1
9
O
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O

1
8
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1
7
E
3
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6
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7
-
+
E
4
E
5
+
- -
E
2
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1
+
-
+
O
P
T
O

1
5
O
P
T
O

1
6
C
O
N
N
E
C
T
I
O
N
C
O
M
M
O
N
F
1
7
F
1
8
F
1
6
F
1
5
F
1
4
F
1
3
+
-
+
-
C
O
N
N
E
C
T

T
O

P
5
9
4
R
X
1
R
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2
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1
0
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1
2
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1
1
O
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1
3
O
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1
4
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1
0
F
1
2
F
1
1
F
9
-
+
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F
6
F
7
F
8
F
5
F
4
-
+
-
+
O
P
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O

7
O
P
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8
C
O
N
N
E
C
T
I
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C
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M
M
O
N
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9
G
1
7
F
3
F
2
G
1
8
F
1
+
- -
G
1
6
G
1
5
G
1
4
G
1
3
++
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+
C
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O
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1
0
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9
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8
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1
6
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R
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2
1
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1
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2
4
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2
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6
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6
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1
5
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1
3
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1
4
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M
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P
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4
6

(
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2
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6
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7
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4
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4
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7
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9
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6
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M
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78 2456 3 1
R
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B
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1
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4
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0
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-
1
Figure 33: P546 current differential 80TE with NCIT 24 inputs, 16 standard outputs and 8 high-break
98 Px4x-92LE--TM-EN-1.1
M
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P
5
4
6
(
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9
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7
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8
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1
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5
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1
6
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4
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3
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1
2
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1
0
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9
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C
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O
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8
O
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7
F
6
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1
4
+ - +
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1
6
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1
5
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1
3
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2
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1
0
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1
1
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9
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8
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7
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5
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4
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2
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3
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1
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1
6
+
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1
8
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1
7
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1
5
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1
4
O
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4
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6
O
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5
O
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3
O
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2
O
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1
+++ -
G
1
2
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1
3
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1
1
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9
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1
0
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8
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5
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6
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4
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3
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1
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1
-
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1
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2
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1
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1
6
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R
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2
4
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1
2
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1
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8
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1
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9
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8
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1
7
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1
6
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1
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1
4
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1
6
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1
5
M
1
3
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1
1
M
1
2
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9
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1
0
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8
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6
M
7
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5
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3
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4
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2
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1
8
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1
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1
7
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1
5
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1
6
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1
4
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1
R
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1
5
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4
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1
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7
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6
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1
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Px4x-92LE--TM-EN-1.1 99
*
C
O
N
N
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C
T

T
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P
5
9
4
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1
R
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2
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(
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5
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6
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7
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M
M
S
P
1
7
-
N
O
T
E

2
E
I
A
4
8
5
/
A
C

O
R

D
C
A
U
X

S
U
P
P
L
Y
x
V K
B
U
S
P
O
R
T
N
O
T
E

3
I
N
P
U
T
S

&

O
U
T
P
U
T
S
C
U
R
R
E
N
T

L
O
O
P
C
L
I
O
D
1
5
1
m
A
2
0
m
A
1
m
A
2
0
m
A
2
0
m
A
1
m
A
2
0
m
A
1
m
A
D
2
2
D
2
6
D
2
8
D
2
9
D
2
4
D
2
5
D
1
8
D
2
0
D
2
1
D
1
6
D
1
7
I
N
P
U
T

4
I
N
P
U
T

3
I
N
P
U
T

2
I
N
P
U
T

1
1
m
A
2
0
m
A
1
m
A
2
0
m
A
1
m
A
2
0
m
A
1
m
A
2
0
m
A
D
7
D
1
1
D
1
3
D
1
4
D
9
D
1
0
D
3
D
5
D
6
D
2
D
1
O
U
T
P
U
T

3
O
U
T
P
U
T

4
O
U
T
P
U
T

1
O
U
T
P
U
T

2
B
1
B
2
8
B
3
0
B
2
9
B
9
B
5
B
7
B
8
B
6
B
3
B
4
B
2
R
T
D

1
0
R
T
D

2
R
T
D

3
R
T
D

1
P
O
W
E
R

S
U
P
P
L
Y

V
E
R
S
I
O
N

2
4
-
4
8
V

(
N
O
M
I
N
A
L
)

D
.
C
.

O
N
L
Y
*
M
i
C
O
M

P
6
4
5

(
P
A
R
T
)
L
1
5
L
1
6
L
3
L
1
1
L
1
2
L
8
L
4
L
7
-+ +- ++ - -
H
I
G
H

B
R
E
A
K
C
O
N
T
A
C
T
S
R
E
L
A
Y

1
7
R
E
L
A
Y

1
9
R
E
L
A
Y

1
8
R
E
L
A
Y

2
0
78 2456 3 1
R
J
4
5
R
X
-
R
X
+
T
X
+
T
X
-
1
0
0

B
A
S
E
-
T
X
1
0
0

B
A
S
E
-
F
X
R
X
T
X
I
E
C

6
1
8
5
0
-
9
-
2

L
E
I
E
C

6
1
8
5
0
-
9
-
2

L
E
S
K
6
2
.

F
O
R

C
O
M
M
S

O
P
T
I
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N
S

S
E
E

D
R
A
W
I
N
G

1
0
P
x
4
0
0
1
.
P
I
N

T
E
R
M
I
N
A
L

(
P
.
C
.
B
.

T
Y
P
E
)
N
O
T
E
S
:
1
.
3
.

F
O
R

0
-
1
0
m
A
,

0
-
2
0
m
A
,

4
-
2
0
m
A

R
A
N
G
E

U
S
E

2
0
m
A

I
N
P
U
T
S

&

O
U
T
P
U
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S
F
O
R

0
-
1
m
A

R
A
N
G
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1
m
A

I
N
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S

&

O
U
T
P
U
T
S
.
O
P
T
I
O
N
A
L
O
P
T
I
O
N
A
L
1
0
P
6
4
5
1
2
-
1
Figure 37: P645 current differential 5 bias input transformer differential 80TE with 4-pole VT inputs,
with NCIT, 24 inputs, 20 outputs plus CLIO and RTD . Part 1 of 1
102 Px4x-92LE--TM-EN-1.1
G
1
6
+-+ + - ++ - - -- + +- + -+-+ + - ++ - - -- + +- + -
F
1
1
O
P
T
O

1
4
O
P
T
O

1
5
O
P
T
O

1
6
C
O
M
M
O
N
C
O
N
N
E
C
T
I
O
N
F
1
7
F
1
8
F
1
4
F
1
6
F
1
5
F
1
3
F
1
2
C
O
M
M
O
N
O
P
T
O

1
0
O
P
T
O

9
O
P
T
O

1
1
O
P
T
O

1
3
O
P
T
O

1
2
C
O
N
N
E
C
T
I
O
N
F
9
F
1
0
F
8
F
6
F
7
F
5
F
3
F
4
F
2
G
1
8
F
1
G
1
7
G
4
O
P
T
O

2
O
P
T
O

3
O
P
T
O

5
O
P
T
O

4
O
P
T
O

6
O
P
T
O

7
O
P
T
O

8
G
1
0
G
1
3
G
1
5
G
1
4
G
1
2
G
1
1
G
7
G
9
G
8
G
5
G
6
O
P
T
O

1
G
2
G
3
G
1
M
i
C
O
M

P
6
4
5

(
P
A
R
T
)
M
i
C
O
M

P
6
4
5

(
P
A
R
T
)
E
A
R
T
H
C
A
S
E

N
1
2
N
1
4
N
1
3
N
1
6
N
1
8
N
1
7
N
1
5
M
1
M
3
M
2
M
5
M
7
M
6
M
4
M
9
M
1
1
M
1
0
M
1
2
M
1
4
M
1
3
M
1
6
M
1
8
M
1
7
M
1
5
M
8
R
E
L
A
Y

1
2
R
E
L
A
Y

1
6
R
E
L
A
Y

1
3
R
E
L
A
Y

1
4
R
E
L
A
Y

1
5
R
E
L
A
Y

9
R
E
L
A
Y

1
1
R
E
L
A
Y

1
0
R
E
L
A
Y

6
R
E
L
A
Y

7
R
E
L
A
Y

8
P
1
2
P
1
3
N
1
N
3
N
2
P
1
4
N
5
N
7
N
6
N
9
N
1
1
N
1
0
N
8
N
4
P
1
1
R
E
L
A
Y

2
R
E
L
A
Y

3
R
E
L
A
Y

5
R
E
L
A
Y

4
C
O
N
T
A
C
T
C
O
N
T
A
C
T
W
A
T
C
H
D
O
G

W
A
T
C
H
D
O
G

R
E
L
A
Y

1
D
3
0
-
M
1
0
-
M
7
M
9
M
8
+ +
4
8
V

D
C

F
I
E
L
D

V
O
L
T
A
G
E

O
U
T
1
0
P
x
4
0
0
1
*
M
1
M
2
+ -
M
1
8
M
1
6
S
C
N
+
S
E
E

D
R
A
W
I
N
G
C
O
M
M
S
M
1
7
-
N
O
T
E

2
E
I
A
4
8
5
/
A
C

O
R

D
C
A
U
X

S
U
P
P
L
Y
x
V K
B
U
S
P
O
R
T
N
O
T
E

3
I
N
P
U
T
S

&

O
U
T
P
U
T
S
C
U
R
R
E
N
T

L
O
O
P
C
L
I
O
D
1
5
1
m
A
2
0
m
A
1
m
A
2
0
m
A
2
0
m
A
1
m
A
2
0
m
A
1
m
A
D
2
2
D
2
6
D
2
8
D
2
9
D
2
4
D
2
5
D
1
8
D
2
0
D
2
1
D
1
6
D
1
7
I
N
P
U
T

4
I
N
P
U
T

3
I
N
P
U
T

2
I
N
P
U
T

1
1
m
A
2
0
m
A
1
m
A
2
0
m
A
1
m
A
2
0
m
A
1
m
A
2
0
m
A
D
7
D
1
1
D
1
3
D
1
4
D
9
D
1
0
D
3
D
5
D
6
D
2
D
1
O
U
T
P
U
T

3
O
U
T
P
U
T

4
O
U
T
P
U
T

1
O
U
T
P
U
T

2
B
1
B
2
8
B
3
0
B
2
9
B
9
B
5
B
7
B
8
B
6
B
3
B
4
B
2
R
T
D

1
0
R
T
D

2
R
T
D

3
R
T
D

1
P
O
W
E
R

S
U
P
P
L
Y

V
E
R
S
I
O
N

2
4
-
4
8
V

(
N
O
M
I
N
A
L
)

D
.
C
.

O
N
L
Y
*
L
1
5
L
1
6
L
3
L
1
1
L
1
2
L
8
L
4
L
7
-+ +- ++ - -
H
I
G
H

B
R
E
A
K
C
O
N
T
A
C
T
S
R
E
L
A
Y

1
7
R
E
L
A
Y

1
9
R
E
L
A
Y

1
8
R
E
L
A
Y

2
0
R
E
L
A
Y

2
2
R
E
L
A
Y

2
1
R
E
L
A
Y

2
3
R
E
L
A
Y

2
4
-+ +- ++ - -
K
1
6
K
1
5
K
1
2
K
1
1
K
8
K
7
K
4
K
3
H
I
G
H

B
R
E
A
K
C
O
N
T
A
C
T
S
78 2456 3 1
R
J
4
5
R
X
-
R
X
+
T
X
+
T
X
-
1
0
0

B
A
S
E
-
T
X
1
0
0

B
A
S
E
-
F
X
R
X
T
X
I
E
C

6
1
8
5
0
-
9
-
2

L
E
I
E
C

6
1
8
5
0
-
9
-
2

L
E
S
K
6
2
.

F
O
R

C
O
M
M
S

O
P
T
I
O
N
S

S
E
E

D
R
A
W
I
N
G

1
0
P
x
4
0
0
1
.
P
I
N

T
E
R
M
I
N
A
L

(
P
.
C
.
B
.

T
Y
P
E
)
N
O
T
E
S
:
1
.
3
.

F
O
R

0
-
1
0
m
A
,

0
-
2
0
m
A
,

4
-
2
0
m
A

R
A
N
G
E

U
S
E

2
0
m
A

I
N
P
U
T
S

&

O
U
T
P
U
T
S
F
O
R

0
-
1
m
A

R
A
N
G
E

U
S
E

1
m
A

I
N
P
U
T
S

&

O
U
T
P
U
T
S
.
O
P
T
I
O
N
A
L
O
P
T
I
O
N
A
L
1
0
P
6
4
5
1
3
-
1
Figure 38: P645 current differential 5 bias input transformer differential 80TE with 4-pole VT inputs,
with NCIT, 16 inputs, 24 outputs plus CLIO and RTD . Part 1 of 1
Px4x-92LE--TM-EN-1.1 103
N
1
4
P
O
W
E
R

S
U
P
P
L
Y

V
E
R
S
I
O
N

2
4
-
4
8
V

(
N
O
M
I
N
A
L
)

D
.
C
.

O
N
L
Y
*
P
1
7
M
1
0
M
1
8
M
1
4
M
1
5
M
1
7
M
1
6
M
1
1
M
1
3
M
1
2
P
8
P
1
0
P
9
P
7
P
2
1
0
P
x
4
0
0
1
S
E
E

D
R
A
W
I
N
G
*
P
1
S
C
N
P
1
6
P
1
8
M
3
M
7
M
8
M
9
M
4
M
6
M
5
N
1
8
M
2
M
1
N
1
5
N
1
7
N
1
6
-
V
x
A
C

O
R

D
C
A
U
X

S
U
P
P
L
Y
4
8
V

D
C

F
I
E
L
D

V
O
L
T
A
G
E

O
U
T
-- + + + -
E
I
A
4
8
5
/
P
O
R
T
K
B
U
S
+
C
O
N
T
A
C
T
W
A
T
C
H
D
O
G

R
E
L
A
Y

1
P
1
3
N
1
0
N
1
1
N
1
3
N
1
2
N
7
N
8
N
9
N
3
N
4
N
6
N
5
P
1
4
N
2
N
1
P
1
2
P
1
1
G
3
F
1
7
F
1
8
F
1
F
9
F
1
3
F
1
5
F
1
6
F
1
4
F
1
1
F
1
2
F
1
0
F
5
F
7
F
8
F
6
F
3
F
4
F
2
G
1
1
G
1
5
G
1
7
G
1
8
G
1
6
G
1
3
G
1
4
G
1
2
G
7
G
9
G
1
0
G
8
G
5
G
6
G
4
G
1
G
2
C
O
M
M
S

O
P
T
I
O
N
S
1
0
P
x
4
0
0
1
S
E
E

D
R
A
W
I
N
G
C
O
N
N
E
C
T
I
O
N
C
O
M
M
O
N
O
P
T
O

2
O
P
T
O

1
+ + - + - + - + - - + - + - - + + + - + - + - + - - + - + - - +
C
O
N
T
A
C
T
W
A
T
C
H
D
O
G

R
E
L
A
Y

2
R
E
L
A
Y

3
R
E
L
A
Y

4
R
E
L
A
Y

5
R
E
L
A
Y

6
R
E
L
A
Y

7
R
E
L
A
Y

8
R
E
L
A
Y

9
R
E
L
A
Y

1
0
R
E
L
A
Y

1
1
R
E
L
A
Y

1
2
R
E
L
A
Y

1
3
R
E
L
A
Y

1
4
R
E
L
A
Y

1
5
R
E
L
A
Y

1
6
O
P
T
O

4
O
P
T
O

3
O
P
T
O

6
O
P
T
O

5
O
P
T
O

7
O
P
T
O

8
O
P
T
O

1
6
C
O
N
N
E
C
T
I
O
N
C
O
M
M
O
N
O
P
T
O

1
5
O
P
T
O

1
4
O
P
T
O

1
3
O
P
T
O

1
2
O
P
T
O

1
1
O
P
T
O

1
0
O
P
T
O

9
M
i
C
O
M

P
7
4
6

(
P
A
R
T
)
M
i
C
O
M

P
7
4
6

(
P
A
R
T
)
R
X
-
R
X
+
T
X
+
T
X
-
R
J
4
5
1
0
0

B
A
S
E
-
T
X
I
E
C

6
1
8
5
0
-
9
-
2

L
E
S
K
6
78 2456 3 1
R
X
T
X
1
0
0

B
A
S
E
-
F
X
I
E
C

6
1
8
5
0
-
9
-
2

L
E
1
0
P
7
4
6
1
2
-
1
Figure 39: P746 busbar 80TE with NCIT, 16 inputs, 16 outputs. Part 1 of 1
104 Px4x-92LE--TM-EN-1.1
N
9
M
1
8
M
1
7
M
1
6
M
1
4
M
1
1
M
1
3
M
1
2
M
1
5
R
E
L
A
Y

1
6
R
E
L
A
Y

1
4
R
E
L
A
Y

1
5
M
1
M
1
0
M
7
M
8
M
9
M
6
M
3
M
4
M
2
M
5
R
E
L
A
Y

1
1
R
E
L
A
Y

1
2
R
E
L
A
Y

1
3
R
E
L
A
Y

1
0
R
E
L
A
Y

9
N
1
4
N
1
8
N
1
5
N
1
7
N
1
6
N
1
0
N
1
1
N
1
2
N
1
3
R
E
L
A
Y

7
R
E
L
A
Y

8
R
E
L
A
Y

6
R
E
L
A
Y

5
P
1
3
P
1
4
N
4
N
8
N
7
N
6
N
5
N
2
N
1
N
3
R
E
L
A
Y

2
R
E
L
A
Y

3
R
E
L
A
Y

4
C
O
N
T
A
C
T
W
A
T
C
H
D
O
G

R
E
L
A
Y

1
P
1
2
P
1
1
W
A
T
C
H
D
O
G

C
O
N
T
A
C
T
P
O
W
E
R

S
U
P
P
L
Y

V
E
R
S
I
O
N

2
4
-
4
8
V

(
N
O
M
I
N
A
L
)

D
.
C
.

O
N
L
Y
-+ +- ++ - -
H
I
G
H

B
R
E
A
K
C
O
N
T
A
C
T
S
* K
1
6
K
1
5
K
1
2
K
1
1
R
E
L
A
Y

2
8
R
E
L
A
Y

2
7
K
8
K
7
K
4
K
3
R
E
L
A
Y

2
6
R
E
L
A
Y

2
5
V
4
8
V

D
C

F
I
E
L
D

V
O
L
T
A
G
E

O
U
T
*
+
P
7
P
1
0
P
9
P
8
-- +
P
2
P
1
+ -
A
C

O
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D
C
A
U
X

S
U
P
P
L
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x
P
O
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B
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4
8
5
/
S
E
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D
R
A
W
I
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1
0
P
x
4
0
0
1
-
P
1
7
P
1
8
S
C
N
M
1
6
+
L
1
3
R
E
L
A
Y

2
4
R
E
L
A
Y

2
3
L
1
8
L
1
7
L
1
6
L
1
5
L
1
4
L
3
R
E
L
A
Y

1
9
R
E
L
A
Y

1
8
R
E
L
A
Y

2
2
R
E
L
A
Y

2
1
R
E
L
A
Y

2
0
L
8
L
1
2
L
1
1
L
1
0
L
9
L
7
L
5
L
4
L
6
R
E
L
A
Y

1
7
L
2
L
1
+ + - + - + - + - - + - + - - + + + - + - + - + - - + - + - - +
O
P
T
O

6
O
P
T
O

1
3
F
1
0
O
P
T
O

1
6
O
P
T
O

1
5
C
O
M
M
O
N
O
P
T
O

1
4
C
O
N
N
E
C
T
I
O
N
F
1
4
F
1
8
F
1
6
F
1
5
F
1
7
F
1
2
F
1
1
F
1
3
O
P
T
O

8
C
O
N
N
E
C
T
I
O
N
C
O
M
M
O
N
O
P
T
O

7
O
P
T
O

1
2
O
P
T
O

1
1
O
P
T
O

1
0
O
P
T
O

9
F
2
F
6
F
9
F
8
F
7
F
5
F
4
F
3
G
1
6
F
1
G
1
8
G
1
7
G
1
5
G
1
2
G
1
4
G
1
3
O
P
T
O

1
O
P
T
O

5
O
P
T
O

4
O
P
T
O

3
O
P
T
O

2
G
1
1
G
8
G
1
0
G
9
G
7
G
4
G
6
G
5
G
3
G
2
G
1
M
i
C
O
M

P
7
4
6

(
P
A
R
T
)
M
i
C
O
M

P
7
4
6

(
P
A
R
T
)
C
O
M
M
S

O
P
T
I
O
N
S
S
E
E

D
R
A
W
I
N
G
1
0
P
x
4
0
0
1
R
X
-
R
X
+
T
X
+
T
X
-
R
J
4
5
1
0
0

B
A
S
E
-
T
X
I
E
C

6
1
8
5
0
-
9
-
2

L
E
S
K
6
78 2456 3 1
R
X
T
X
1
0
0

B
A
S
E
-
F
X
I
E
C

6
1
8
5
0
-
9
-
2

L
E
1
0
P
7
4
6
1
5
-
1
Figure 40: P746 busbar 80TE with NCIT, 16 inputs, 8 standard outputs, 8 high-break outputs. Part 1 of
1
Px4x-92LE--TM-EN-1.1 105
*
-
4
8
V

D
C

F
I
E
L
D

V
O
L
T
A
G
E

O
U
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P
7
P
9
P
1
0
P
8
+- +
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2
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1
V
x
+ -
A
C

O
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D
C
A
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P
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D
R
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D
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1
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x
4
0
0
1
P
O
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B
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4
8
5
/
P
1
8
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N
P
1
6
+
P
1
7
-
C
O
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M
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O
P
T
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S
1
0
P
x
4
0
0
1
E
1
0
E
1
8
E
1
4
E
1
6
E
1
5
E
1
7
E
1
2
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1
1
E
1
3
E
3
E
8
E
9
E
7
E
4
E
5
E
6
E
1
E
2
L
1
1
L
1
5
L
1
7
L
1
8
L
1
6
L
1
4
L
1
3
L
1
2
L
2
L
6
L
8
L
1
0
L
9
L
7
L
3
L
4
L
5
L
1
+ + - + - + - + - - + - + - - +
C
O
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M
O
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C
O
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N
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C
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I
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O
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1
7
O
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1
8
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1
9
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2
0
O
P
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2
1
O
P
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2
2
O
P
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2
3
O
P
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2
4
P
O
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S
U
P
P
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V
E
R
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2
4
-
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(
N
O
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.
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.

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N
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R
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1
5
M
1
6
M
1
7
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1
5
M
1
8
R
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L
A
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1
6
N
1
3
M
5
M
6
M
9
M
8
M
7
M
1
2
M
1
3
M
1
1
M
1
4
M
1
0
R
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L
A
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1
3
R
E
L
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1
4
R
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1
2
R
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L
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1
1
N
1
6
N
1
7
N
1
5
M
1
M
2
N
1
8
M
4
M
3
N
1
4
R
E
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1
0
R
E
L
A
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9
R
E
L
A
Y

8
R
E
L
A
Y

7
N
3
N
5
N
6
N
4
N
9
N
8
N
7
N
1
2
N
1
1
N
1
0
R
E
L
A
Y

4
R
E
L
A
Y

6
R
E
L
A
Y

5
R
E
L
A
Y

3
R
E
L
A
Y

2
P
1
1
P
1
2
N
1
N
2
P
1
4
P
1
3
C
O
N
T
A
C
T
W
A
T
C
H
D
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C
O
N
T
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C
T
R
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1
W
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C
H
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R
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L
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2
4
R
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L
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2
3
R
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2
2
R
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L
A
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1
9
R
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L
A
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2
1
R
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L
A
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2
0
R
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L
A
Y

1
8
R
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L
A
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1
7
+ + - + - + - + - - + - + - - + + + - + - + - + - - + - + - - +
O
P
T
O

6
F
1
0
O
P
T
O

1
3
C
O
N
N
E
C
T
I
O
N
O
P
T
O

1
4
C
O
M
M
O
N
O
P
T
O

1
5
O
P
T
O

1
6
F
1
4
F
1
7
F
1
5
F
1
6
F
1
8
F
1
3
F
1
1
F
1
2
F
2
O
P
T
O

9
O
P
T
O

1
0
O
P
T
O

1
1
O
P
T
O

1
2
F
6
F
7
F
8
F
9
F
3
F
4
F
5
O
P
T
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7
C
O
M
M
O
N
C
O
N
N
E
C
T
I
O
N
O
P
T
O

8
G
1
6
G
1
7
G
1
8
F
1
G
1
3
G
1
4
G
1
2
G
1
5
O
P
T
O

2
O
P
T
O

3
O
P
T
O

4
O
P
T
O

5
G
9
G
1
0
G
8
G
1
1
G
5
G
6
G
4
G
7
O
P
T
O

1
G
1
G
2
G
3
M
i
C
O
M

P
7
4
6

(
P
A
R
T
)
M
i
C
O
M

P
7
4
6

(
P
A
R
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)
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X
-
R
X
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+
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X
-
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4
5
1
0
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6
1
8
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9
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6
78 2456 3 1
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0
P
7
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6
1
6
-
1
106 Px4x-92LE--TM-EN-1.1
-+ +- ++ - -
R
E
L
A
Y

2
0
L
1
6
R
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L
A
Y

1
9
L
1
1
L
1
2
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1
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1
7
R
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L
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1
8
L
4
L
7
L
8
L
3
H
I
G
H

B
R
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A
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C
O
N
T
A
C
T
S
+ + - + - + - + - - + - + - - +
E
8
C
O
N
N
E
C
T
I
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1
8
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1
7
C
O
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M
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1
4
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1
6
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1
5
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1
3
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2
4
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2
3
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1
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1
2
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1
1
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9
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2
2
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2
1
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4
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7
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5
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6
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2
0
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9
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1
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1
8
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1
7
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1
1
R
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1
5
R
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1
6
* M
1
6
M
1
7
M
1
5
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1
8
R
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1
3
R
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1
4
R
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1
2
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1
1
R
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1
0
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9
R
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8
R
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7
R
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4
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6
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5
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1
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1
3
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1
2
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1
3
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1
1
M
1
4
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1
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5
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6
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9
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8
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7
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8
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2
2
R
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3
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R
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3
+ + - + - + - + - - + - + - - + + + - + - + - + - - + - + - - +
F
7
F
1
5
O
P
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1
6
C
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M
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E
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F
1
8
F
1
6
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7
O
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2
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1
5
O
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O

1
4
O
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T
O

1
3
F
1
1
F
1
2
F
1
3
F
1
4
F
9
F
8
F
1
0
G
8
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E
C
T
I
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C
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M
O
N
O
P
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O

1
1
O
P
T
O

1
0
O
P
T
O

9
F
5
F
4
F
3
F
6
F
1
G
1
8
G
1
7
F
2
O
P
T
O

5
O
P
T
O

8
O
P
T
O

7
O
P
T
O

6
G
1
5
G
1
4
G
1
3
G
1
6
G
1
1
G
1
0
G
9
G
1
2
O
P
T
O

1
O
P
T
O

4
O
P
T
O

3
O
P
T
O

2
G
4
G
7
G
6
G
5
G
3
G
2
G
1
M
i
C
O
M

P
7
4
6

(
P
A
R
T
)
M
i
C
O
M

P
7
4
6

(
P
A
R
T
)
R
X
-
R
X
+
T
X
+
T
X
-
R
J
4
5
1
0
0

B
A
S
E
-
T
X
I
E
C

6
1
8
5
0
-
9
-
2

L
E
S
K
6
78 2456 3 1
R
X
T
X
1
0
0

B
A
S
E
-
F
X
I
E
C

6
1
8
5
0
-
9
-
2

L
E
1
0
P
7
4
6
1
7
-
1
Figure 42: P746 busbar 80TE with NCIT, 16 inputs, 24 standard outputs, 4 high-break outputs. Part 1
of 1
Px4x-92LE--TM-EN-1.1 107
+ + - + - + - + - - + - + - - + + + - + - + - + - - + - + - - +
F
7
O
P
T
O

1
3
O
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1
4
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1
5
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1
2
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M
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1
6
F
1
5
F
1
7
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1
6
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1
8
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1
1
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1
4
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1
3
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1
2
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1
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8
F
9
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8
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P
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6
O
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7
O
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8
O
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5
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9
O
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1
0
O
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1
1
C
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M
M
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C
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C
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F
6
F
3
F
4
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5
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2
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1
7
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1
8
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1
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1
6
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1
3
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4
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1
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9
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2
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4
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1
G
4
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5
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6
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7
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1
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2
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3
+ + - + - + - + - - + - + - - +
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1
3
-+ +- ++ - -
C
O
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A
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H
I
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B
R
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A
K
R
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A
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1
6
L
1
6
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1
1
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1
5
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1
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8
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7
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4
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1
5
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1
4
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8
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3
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1
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1
8
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1
3
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1
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6
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2
3
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2
4
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2
2
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4
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6
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5
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7
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8
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-+ +- ++ - -
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2
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-
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.
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4
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6
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2
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1
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1
2
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1
P
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4
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1
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1
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-+ +- ++ - -
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1
6
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2
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1
5
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1
9
R
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L
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2
0
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7
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4
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7
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8
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8
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7
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B
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4
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5
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M
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(
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M
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C
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6
78 2456 3 1
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6
1
8
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1
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P
7
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6
1
8
-
1
108 Px4x-92LE--TM-EN-1.1
1
0
P
7
4
6
1
9
-
1
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E
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D
R
A
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1
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2
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1
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3
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1
5
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1
4
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1
6
* M
1
8
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1
7
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1
4
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1
3
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1
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5
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1
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9
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8
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5
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6
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7
R
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3
R
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4
N
1
5
M
3
M
4
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2
M
6
M
5
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1
8
M
1
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1
7
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1
6
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1
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1
1
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1
2
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1
4
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1
3
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7
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8
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9
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1
R
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2
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O
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1
4
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2
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1
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4
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1
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1
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1
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2
1
L
1
0
-
1
0
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4
0
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1
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1
7
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D
R
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W
I
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M
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O
P
T
I
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S
L
1
5
L
1
6
L
1
8
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1
7
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1
2
L
1
3
L
1
4
L
1
1
R
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L
A
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2
3
R
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L
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2
4
R
E
L
A
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2
2
L
5
L
7
L
9
L
8
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6
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1
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4
L
3
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2
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2
0
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A
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1
9
R
E
L
A
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1
7
R
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L
A
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1
8
+ + - + - + - + - - + - + - - + + + - + - + - + - - + - + - - +
+ + - + - + - + - - + - + - - +
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P
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1
8
O
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1
7
O
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2
0
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1
9
O
P
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O

2
2
O
P
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2
1
O
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2
4
O
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2
3
C
O
M
M
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C
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7
F
1
5
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1
6
C
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C
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1
8
F
1
6
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1
7
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1
5
O
P
T
O

1
4
O
P
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1
2
O
P
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O

1
3
F
1
1
F
1
2
F
1
3
F
1
4
F
9
F
8
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1
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8
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8
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1
1
O
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1
0
C
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C
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9
F
5
F
4
F
3
F
6
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1
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1
8
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2
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8
O
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7
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5
O
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6
G
1
5
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1
4
G
1
3
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1
6
G
1
1
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1
0
G
9
G
1
2
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1
7
E
1
8
E
1
3
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1
5
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1
6
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1
4
E
9
E
1
1
E
1
2
E
1
0
O
P
T
O

4
O
P
T
O

3
O
P
T
O

1
O
P
T
O

2
G
4
G
7
G
6
G
5
G
3
G
2
G
1
E
4
E
6
E
5
E
7
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2
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1
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3
D
5
C
O
N
N
E
C
T
I
O
N
C
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M
M
O
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P
T
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3
1
O
P
T
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3
2
O
P
T
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2
9
O
P
T
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3
0
O
P
T
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2
7
O
P
T
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2
8
D
1
3
D
1
8
D
1
4
D
1
6
D
1
5
D
1
7
D
9
D
1
0
D
1
2
D
1
1
D
8
D
7
D
6
O
P
T
O

2
5
O
P
T
O

2
6
D
1
D
3
D
2
D
4
+ + - + - + - + - - + - + - - +
M
i
C
O
M

P
7
4
6

(
P
A
R
T
)
M
i
C
O
M

P
7
4
6

(
P
A
R
T
)
R
X
-
R
X
+
T
X
+
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X
-
R
J
4
5
1
0
0

B
A
S
E
-
T
X
I
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6
1
8
5
0
-
9
-
2

L
E
S
K
6
78 2456 3 1
R
X
T
X
1
0
0

B
A
S
E
-
F
X
I
E
C

6
1
8
5
0
-
9
-
2

L
E
S
E
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D
R
A
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I
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1
0
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4
6
0
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S

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S
Y
S
T
E
M
of 1
Px4x-92LE--TM-EN-1.1 109
C
O
M
M
S

O
P
T
I
O
N
S
S
E
E

D
R
A
W
I
N
G
1
0
P
x
4
0
0
1
+ + - + - + - + - - + - + - - + + + - + - + - + - - + - + - - +
G
5
O
P
T
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1
0
F
1
2
O
P
T
O

1
4
O
P
T
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1
5
C
O
N
N
E
C
T
I
O
N
C
O
M
M
O
N
O
P
T
O

1
6
F
1
6
F
1
7
F
1
8
F
1
4
F
1
3
F
1
5
O
P
T
O

1
1
O
P
T
O

1
3
O
P
T
O

1
2
F
1
0
F
8
F
9
F
1
1
F
6
F
4
F
5
F
7
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1
3
O
P
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7
O
P
T
O

8
O
P
T
O

9
C
O
N
N
E
C
T
I
O
N
C
O
M
M
O
N
F
2
G
1
8
F
1
F
3
G
1
6
G
1
4
G
1
5
G
1
7
O
P
T
O

3
O
P
T
O

4
O
P
T
O

6
O
P
T
O

5
G
9
G
1
2
G
1
0
G
1
1
G
8
G
6
G
7
O
P
T
O

2
O
P
T
O

1
G
1
G
2
G
3
G
4
+ + - + - + - + - - + - + - - + + + - + - + - + - - + - + - - +
E
5
O
P
T
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2
6
D
1
2
O
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3
0
C
O
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C
T
I
O
N
D
1
6
O
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3
2
D
1
8
D
1
7
C
O
M
M
O
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D
1
5
D
1
4
D
1
3
O
P
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3
1
O
P
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O

2
8
D
1
0
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1
1
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9
D
8
O
P
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2
9
D
7
D
6
D
5
D
4
O
P
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2
7
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1
3
C
O
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N
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C
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I
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C
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M
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3
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2
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1
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1
8
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2
5
E
1
4
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1
6
E
1
5
E
1
7
O
P
T
O

2
3
O
P
T
O

2
4
E
9
E
1
0
E
1
2
E
1
1
O
P
T
O

2
1
O
P
T
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110 Px4x-92LE--TM-EN-1.1
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1
Px4x-92LE--TM-EN-1.1 111
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78 2456 3 1
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of 1
112 Px4x-92LE--TM-EN-1.1

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Px4x-92LE--TM-EN-1.1 113
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7
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1
114 Px4x-92LE--TM-EN-1.1
27 P841B WITH IEC 61850-9-2LE INTERFACE CONFIGURATION 1
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1
Figure 50: P841B autoreclose 80TE with NCIT, 24 inputs, 32 outputs. Part 1 of 2
Px4x-92LE--TM-EN-1.1 115
K
1
1
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1
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1
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8
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6
-
2
Figure 51: P841B autoreclose 80TE with NCIT, 24 inputs, 32 outputs. Part 2 of 2
116 Px4x-92LE--TM-EN-1.1
E
8
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-
1
Figure 52: P841B autoreclose 80TE with NCIT, 24 inputs, 16 standard outputs, 8 high-break outputs.
Part 1 of 2
Px4x-92LE--TM-EN-1.1 117
M
i
C
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P
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1
(
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2
Part 2 of 2
118 Px4x-92LE--TM-EN-1.1
F
9
F
1
1
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1
3
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-
1
Part 1 of 2
Px4x-92LE--TM-EN-1.1 119
M
i
C
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M

P
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1
(
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9
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7
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-
E
4
+
-
E
2
E
1
F
1
8
F
1
5
+
-
F
1
6
F
1
7
+
-
F
1
4
F
1
3
O
P
T
O

1
2
O
P
T
O

1
4
O
P
T
O

1
3
O
P
T
O

1
1
O
P
T
O

1
0
C
O
N
N
E
C
T
I
O
N
C
O
M
M
O
N

O
P
T
O

9
O
P
T
O

7
O
P
T
O

8
O
P
T
O

6
F
3
F
1
0
-
+
F
1
2
F
1
1
-
+
F
9
F
8
+
- -
F
7
F
6
+
-
F
5
F
4
+
-
F
2
F
1
+
G
1
8
G
1
7
G
1
4
-
+
G
1
5
G
1
6
-
+
G
1
3
G
1
2
O
P
T
O

1
O
P
T
O

5
O
P
T
O

4
O
P
T
O

3
O
P
T
O

2
G
2
G
7
+
- -
G
1
1
G
1
0
+
-
G
8
G
9
++
-
G
6
G
5
-
+
G
4
G
3
-
G
1
K
4
+
K
1
6
+
K
1
2
K
1
5
- +
K
1
1
K
8
- +
K
7
-
R
E
L
A
Y

1
9
R
E
L
A
Y

2
0
R
E
L
A
Y

1
8
+
K
3
-
L
1
6
L
1
5
-
L
1
1
L
1
2
+ -
L
8
+
L
7
L
4
- +
L
3
M
1
6
- +
M
1
2
M
1
5
- +
M
1
1
-
R
E
L
A
Y

1
6
R
E
L
A
Y

1
7
R
E
L
A
Y

1
5
R
E
L
A
Y

1
4
R
E
L
A
Y

1
3
R
E
L
A
Y

1
1
R
E
L
A
Y

1
2
M
7
M
8
+ -
M
4
+ -
M
3
N
1
4
N
1
8
N
1
7
N
1
5
N
1
6
N
1
1
N
1
3
N
1
2
N
1
0
N
9
R
E
L
A
Y

9
R
E
L
A
Y

1
0
R
E
L
A
Y

8
R
E
L
A
Y

7
R
E
L
A
Y

6
R
E
L
A
Y

5
N
3
N
7
N
8
N
6
N
4
N
5
P
1
4
N
2
N
1
P
1
3
P
1
2
P
1
1
D
E
F
A
U
L
T

S
E
T
T
I
N
G
R
E
L
A
Y

4
R
E
L
A
Y

3
R
E
L
A
Y

2
W
A
T
C
H
D
O
G

W
A
T
C
H
D
O
G

C
O
N
T
A
C
T
R
E
L
A
Y

1
C
O
N
T
A
C
T
C
U
S
T
O
M
E
R

S
E
T
T
I
N
G
C
B
1

E
X
T

T
R
I
P

B
C
B
2

E
X
T

T
R
I
P

B
C
B
2

E
X
T

T
R
I
P

C
C
B
1

E
X
T

T
R
I
P

C
C
B
2

E
X
T

T
R
I
P

A
N
O
T

U
S
E
D
C
B
1

E
X
T

T
R
I
P

A
C
B
2

H
E
A
L
T
H
Y
C
U
S
T
O
M
E
R

S
E
T
T
I
N
G
C
B
1

A
U
X
C

5
2
-
B
N
O
T

U
S
E
D
C
B
2

C
L
O
S
E

M
A
N
C
B
1

H
E
A
L
T
H
Y
M
C
B
/
V
T
S
C
B
1

C
L
O
S
E

M
A
N
C
B
1

A
U
X
A

5
2
-
B
C
B
1

A
U
X
B

5
2
-
B
C
B
2

A
U
X
B

5
2
-
B
C
B
2

A
U
X
C

5
2
-
B
N
O
T

U
S
E
D
N
O
T

U
S
E
D
R
E
S
E
T

L
E
D
S
C
B
2

A
U
X
A

5
2
-
B
N
O
T

U
S
E
D
B
A
R
D
E
F
A
U
L
T

S
E
T
T
I
N
G
N
O
T

U
S
E
D
C
B
1

T
R
I
P

C
C
N
T
L

C
B
2

C
L
O
S
E
C
N
T
L

C
B
1

C
L
O
S
E
A
R
I
P
G
E
N
E
R
A
L

A
L
A
R
M
A
N
Y

T
R
I
P
A
N
Y

S
T
A
R
T
A
R

L
O
C
K
O
U
T
C
B
1

T
R
I
P

A
C
B
1

T
R
I
P

B
C
B
2

T
R
I
P

A
C
B
2

T
R
I
P

B
C
B
2

T
R
I
P

C
C
B
1

T
R
I
P

A
C
B
1

T
R
I
P

B
C
B
1

T
R
I
P

C
C
B
2

T
R
I
P

A
C
B
2

T
R
I
P

B
C
B
2

T
R
I
P

C
H
I
G
H

B
R
E
A
K
H
I
G
H

B
R
E
A
K
C
O
N
T
A
C
T
S
C
O
N
T
A
C
T
S
C
O
N
T
A
C
T
S
H
I
G
H

B
R
E
A
K
1
0
P
8
4
1
0
8
-
2
Part 2 of 2
120 Px4x-92LE--TM-EN-1.1
Index
1
100 Base FX Receiver Characteristics 86
100 Base FX Transmitter Characteristics 86
A
Appendix Overview 89
Application Examples 47, 49
Arrangement of the Station and Process Buses 62
B
Back Cover 124
Bay Architecture 60
Benefits of IEC 61850 34
Board Connections 14
C
Channel mappings for SAV Test, SAV Questionable,
SAV Invalid 23, 26, 29
Chapter Overview 3, 13, 19, 67, 75, 85, 33
Check Connections 78
Checking the GPS Synchronisation Signal at the IED
82
Comissioning the GPS functionality 82
Commissioning Instructions 73
Commissioning Mode 82
Commissioning Test Equipment 77
Current Differential Function 44
Current Differential Schemes 54
D
Data Quality 38
Data Resampling 36
DDB Signals Table 69, 70, 71
Differential Protection Function Testing 81
E
Ethernet Port Copper 86
F
Foreword 4
G
General Guidelines 76
H
Hardware Design 11
I
IEC 61850 34
IEC 61850 Interoperability 34
IED Alarms 43
IED With One Logical Node Configured 79
IED With Two or More Logical Nodes Configured 80
Impact of Data Quality on Protection Functions 38
Interfaces 86
Introduction 1
Introduction to IEC 61850-9-2LE 34
L
Location in IED 15
O
Operation 31
Overview 50
P
P446 51
P446 with IEC 61850-9-2LE Interface Configuration
1 90
2 91
3 92
4 93
5 94
6 95
P446, P546, P841B 20
P546 44
1 96
2 97
3 98
4 99
5 100
6 101
P645 24
1 102
2 103
P645, P746 81
P746 27
Px4x-92LE Index
Px4x-92LE--TM-EN-1.1 121
1 104
10 113
11 114
2 105
3 106
4 107
5 108
6 109
7 110
8 111
9 112
P841B Ordering Options 9
P841B with IEC 61850-9-2LE Interface Configuration
1 115
2 116
3 117
4 118
5 119
6 120
Process Bus Performance 41
Programmable Scheme Logic 68
S
Sample Loss Data 41
Sampled Value Alignment 37
Sampled Value Distribution 51, 57, 59
Scheme Logic 65
Settings and Records 17
Settings Table 20, 24, 27
Strength of P594 Optical Signal at IED 82
T
Technical Specifications 83
V
Virtual CT and VT Ratio Settings 30
Voltage Input Switching 63
VT Switching 42
W
Wiring Diagrams 87
Index Px4x-92LE
122 Px4x-92LE--TM-EN-1.1
Alstom Grid
- ALSTOM 2013. All rights reserved.
Information contained in this document is
indicative only. No representation or warranty is
given or should be relied on that it is complete or
correct or will apply to any particular project. This
will depend on the technical and commercial
circumstances. It is provided without liability and
is subject to change without notice.
Reproduction, use or disclosure to third parties,
without express written authority, is strictly
prohibited.
Alstom Grid Worldwide Contact Centre
www.alstom.com/grid/contactcentre/
Tel: +44 (0) 1785 250 070
www.alstom.com

Px4x - 9 2LE TM EN 001

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