BootCamp SystemVerilog

Objective:
Boost your career by developing depth of knowledge into verification with SystemVerilog
Increase your competitiveness by gaining deeper knowledge and experience with
SystemVerilog
Develop strong experience with SystemVerilog and apply it to your work environment
Learn the ability to find and locate bugs quickly with SystemVerilog

Compare:
Compare our program with any other program available and youll find that VeriFast offers
the most cost effective and in-depth solution available.
Other programs are typically 1 5 days in duration. At VeriFast, we dont believe a few days
is a sufficient learning environment. Our competitors offer a crash course (information
dump) where you dont learn lasting verification techniques.
We believe in a learning environment which spans several weeks in duration where you
apply your knowledge in a highly hands-on environment with high quality simulation tools
whereby real-world verification challenges are taught and solved.

General Information:
BootCamp-SystemVerilog is a 6-8 week program where youll develop actual depth of
verification experience with SystemVerilog.
Lecture time is approximately 6 8 hours per week.
Total lecture time is approximately 50 hours.
Additional hands-on lab/homework assignments are approximately 50 hours.
Total time invested is approximately 100 hours over an 8 week program.
Lectures are live and accessed via our VeriFast virtual web classroom.
o You can take the course from any location as long as you have highly reliable
internet connectivity.
VeriFast will provide you access to our EDA License Server for three additional months
beyond your class program for continued learning and practice.

Training Content:
BootCamp-SystemVerilog includes Language fundamentals and Advanced concepts such as:
Along with modules , other Containers like
o Program
o Interface
o Checker
o Config
Advanced data types and its dos and Donts
Process control with fork-join, events
Modport and clocking blocks in interface and virtual interface


Interprocess communication with mailbox,semaphores
Advanced Constraints
Advanced Class handling
Detailed functional coverage concepts
Direct Programming Interface (DPI)

Labs & Exercises Content:
Labs are geared to solidify understanding of key concepts of SystemVerilog
Boot camp includes complex labs providing you with real-world experience. Lab examples:
o Write program block
o Use checkers in different flavors in monitors
o Write abstract and pure virtual classes
o Derive from and create new classes to create stimulus,monitors
o Create advanced constraints for stimus
o Communicate with C using DPI
o Write functional coverage for testbench
Final Project (Optional):
o Build a real life SV testbench with instructor guidance
o Build an SV testbench from scratch
o Gain hands-on experience with SV testbench

Prerequisites:
BS or MS in Electrical Engineering, Computer Engineering, VLSI or Equivalent
Working experience with Verilog for at least one project or basic SystemVerilog knowledge
is preferred

EDA Tools:
Questasim from Mentor Graphics
VeriFast is a Questasim Vanguard partner

Dates:
First day of class is Saturday June 7, 2014
Lectures/Class Times:
o Saturdays from 8am 1pm (Pacific Time)
o Wednesdays from 7pm 9pm (Pacific Time)
Much of the Wednesday lecture time is devoted to Q&A regarding
homework assignments.

Pricing:


$2,495.00 USD


Contact:
info@verifasttech.com
www.verifasttech.com
Mike Chandler @ 408-348-2399