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Welcome

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LabVIEW 2014
Whats New in LabVIEW 2014

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Accurate Data Acquisition With


the Latest Technology

Extended Deployment Options


for Built-in Analysis Routines

13 Coding Productivity
Enhancing Features

Acquire, analyze, and visualize any data set to make


informed decisions fast.

Expanded Interface Development


and Deployment Options

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Global Solutions to Mine


and Search Data

Innovate With a
Community

Accurate Data Acquisition With


the Latest Technology

Extended Deployment Options


for Built-in Analysis Routines

13 Coding Productivity
Enhancing Features

Acquire, analyze, and visualize any data set to make


informed decisions fast.

Expanded Interface Development


and Deployment Options

italy.ni.com/labview-developer-tour

Global Solutions to Mine


and Search Data

Innovate With a
Community

Unrivaled Integration with the Latest Technology


Standalone CompactDAQ
Software Designed Oscilliscope
System on a Module (SoM)

New Hardware Products

Performance CompactRIO
USB3 CVS

VirtualBench
.

italy.ni.com/labview-developer-tour

Accurate Data Acquisition With


the Latest Technology

Extended Deployment Options


for Built-in Analysis Routines

13 Coding Productivity
Enhancing Features

Acquire, analyze, and visualize any data set to make


informed decisions fast.

Expanded Interface Development


and Deployment Options

italy.ni.com/labview-developer-tour

Global Solutions to Mine


and Search Data

Innovate With a
Community

Application-Specific LabVIEW Suites

NI LabVIEW Embedded
Control and Monitoring Suite

NI LabVIEW HIL and


Real-Time Test Suite

LabVIEW Embedded Control


and Monitoring Suite

LabVIEW Automated Test


Suite

LabVIEW HIL and Real-Time


Test Suite

Includes NI LabVIEW Real-Time


and FPGA Modules

Includes NI TestStand and


Switch Executive

Includes NI VeriStand and LabVIEW


Real-Time and FPGA Modules

The Tools You Need

Convenient USB Install

New LabVIEW Suites group


LabVIEW Professional with all the
tools you will likely need for your
application

Suites are distributed on a USB 3.0


flash drive with all the software and
drivers you need already included

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Value Added to Existing LabVIEW Editions


Full Edition
Make advanced control
applications through included
PID and Fuzzy Logic palettes

Professional Edition
Trace low-level bugs,
validate coding practices,
and manipulate data
through the now included:
VI Analyzer Toolkit
Unit Test Framework Toolkit
Desktop Execution Trace Toolkit
Database Connectivity Toolkit
Report Generation Toolkit
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LabVIEW Taskbar Icon

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10

LabVIEW Taskbar Icon

Users upgrade every 1-3 years

years between LabVIEW upgrades

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LabVIEW Taskbar Icon

Users upgrade every 1-3 years


Identical task bar icons create confusion

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12

New Taskbar Icon

Easily Differentiate between LabVIEW versions


Suggested by 500+ Idea Exchange Kudos

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13

New Taskbar Icon

32-bit

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64-bit

14

LabVIEW 64-Bit vs 32-Bit Applications


LabVIEW 64-Bit

LabVIEW 32-Bit

You can run the LabVIEW 32-bit


Development System, Run-Time
Engine, or executables on a 64-bit PC

You cannot run the LabVIEW 64-bit


Development System, Run-Time
Engine, or executables on a 32-bit PC

Not all LabVIEW modules and toolkits All LabVIEW modules and toolkits are
are available for LabVIEW 64-bit
available for LabVIEW 32-bit

I have both LabVIEW 32-bit and


You cannot install LabVIEW 64-bit on
LabVIEW 64-bit installed on the same a 32-bit machine
64-bit machine
64-bit LabVIEW on an 64-bit OS
supports as much RAM as the OS
supports
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64-bit for Mac and Linux Desktop OS

Windows

Mac OS X
Linux

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Run Algorithms and Models on NI Linux Real-Time


Add-on Modules with LabVIEW Real-Time Capability

Native LabVIEW solution


No code generation or 3rd party software required

MathScript RT Module
Re-use .m scripts that you developed in
MathWorks Inc. MATLAB or GNU Octave

Control Design & Simulation Module


Move beyond PID for advanced control and
dynamic system simulation
Model your system with the included System
Identification Toolkit
MATLAB is a registered trademark of The MathWorks, Inc..
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17

Vision Development Module includes Powerful IP


Proven Image Technology
Leverage over 50 FPGA image
processing functions to design high
performance vision systems and
pass images between CPU and
FPGA

CPU

Improved Usability
Prototype and generate code using
Vision Assistant to design high
performance vision systems
FPGA

Find Data Easier


Automatically search an entire
image for 1D Barcodes and perform
decoding
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18

Data Scenario Antarctica Weather Data

Valuable Data Source

Challenging Data Set

60+ weather stations


30+ years of remote data
9000+ measurement files
Insight into climate change
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19

Custom ASCII format


Info in file name
Null data values
Inconsistent delimiters

Accurate Data Acquisition With


the Latest Technology

Extended Deployment Options


for Built-in Analysis Routines

13 Coding Productivity
Enhancing Features

Acquire, analyze, and visualize any data set to make


informed decisions fast.

Expanded Interface Development


and Deployment Options

italy.ni.com/labview-developer-tour

Global Solutions to Mine


and Search Data

20

Innovate With a
Community

Accurate Data Acquisition With


the Latest Technology

Extended Deployment Options


for Built-in Analysis Routines

13 Coding Productivity
Enhancing Features

Acquire, analyze, and visualize any data set to make


informed decisions fast.

Expanded Interface Development


and Deployment Options

italy.ni.com/labview-developer-tour

Global Solutions to Mine


and Search Data

21

Innovate With a
Community

Growing LabVIEW Ecosystem


LabVIEW Tools Network
3,000,000 add-ons downloaded
Over 250 add-ons

User Community
Over 10,000 certified users
Over 800 alliance partners
80+ registered user groups

Connectivity
Over 10,000 instrument drivers
Any bus, any protocol, any platform
Integration with third-party languages
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22

Engineering Impact Award:


Condividi le tue applicazioni
Racconta come hai realizzato i tuoi progetti di
maggior successo grazie a NI
Fai conoscere le tue applicazioni e potrai
avere visibilit sul sito e sulle newsletter NI, e
sulle riviste di settore!
Scarica il kit autori su
italy.ni.com/premio-misura-automazione

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23

LabSocket by Bergmans Mechatronics


New on the LabVIEW Tools Network

Automatically creates interactive HTML5 interfaces from


LabVIEW front panels
Access on any modern mobile or desktop browser

LabVIEW

Web Browser

Download evaluation at ni.com/labviewtools/labsocket


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Spreadsheet Toolkits
New on the LabVIEW Tools Network

Spreadsheet Express

XLR8

by Aledyne Engineering

by DATA AHEAD

Automate advanced Excel data


processing and charting

Read and write .xls files without


the need for Excel

Download evaluation at:

Download evaluation at:

ni.com/labviewtools/spreadsheetexpress

ni.com/labviewtools/xlr8

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Phone, Email, Forum Support From Applications Engineers


Save Time Troubleshooting

Exclusive Training day and Tutoring online


Increase Proficiency at Your Pace

Future Software Updates and Upgrades


Always Leverage the Latest Technologies

Download Older Versions of Software


Ensure Quick Access to Existing Software

LabVIEW World Magazine


Free annual subscription

The NI Software Maintenance Programs (Standard Service Program, Software


Contract, Volume License Agreement) lower the total cost of ownership and get
you on the path to success faster.
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26

Software Service Renewal Policy


Purchase

Renewal

nth Year

Today
Ontime

Inactive > 60 days

20% of software price

50% of software price

Inactive < 60 days


30% of software price

Auto-Renewal
o
o

Get auto-invoiced for renewals


Price-freezing

Multi-Year
o
o

(Software Contract Formula)

Discount

Get a discount for service contract spanning multiple years


Eliminate potential of future budget issues

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Advanced Programming with


NI-DAQmx

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Agenda

Anatomy of DAQ Device


NI DAQmx driver
Transfer data: From I/O to LabVIEW
Triggering
Counter
Syncronization

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Anatomy of a DAQ Device

Bus/CPU

Contains all circuitry necessary


for completing a DAQ task

Sensors

Clock and timing circuitry


On-board FIFOs
Signal routing
Triggering, Buffers, etc.

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Actuators

Anatomy of a DAQ Device

Bus/CPU

Contains all circuitry necessary


for completing a DAQ task

Sensors

Clock and timing circuitry


On-board FIFOs
Signal routing
Triggering, Buffers, etc.

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Actuators

Anatomy of a DAQ Device


Analog
Input
0010110
Analog Output
1010010
Digital
1101011
Counter

Bus/CPU

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Actuators

Sensors

Data Transfer bus can be USB, PCI,


PCI Express, PXI, PXI Express

DAQ Circuitry: System Timing Controller

NI-STC - ASIC
Bus
Master
DMA
IRQ
Engines

Input/
Output
Lines

Input /
Output
Timing
Engines

Triggers

Counters

RTSI /
PFI

Routing

Bus
Interface

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Measurements Modules

33

Bridging the Hardware and Software Gap with NI-DAQmx


NI-DAQmx is a single, free hardware driver that supports
various development languages and hundreds of NI data
acquisition hardware platforms.

The mark LabWindows is used under a license from Microsoft Corporation.


Windows is a registered trademark of Microsoft Corporation in the United States and other countries.

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DAQmx Function Architecture

DLLs common to all ADEs


Results in similar API for all ADEs

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Overview of NI-DAQmx VIs Primary Functions

Configure
Channel

Configure
Timing

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DAQmx Main Functions

Specific Property Node

Configure
Start
Triggering Acquisition

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Read
Data

Clear
Task

Data Transfer for Buffered Operation


Input Rate

Onboard FIFO Bus Interface

ADE (Application)
Memory

PC Buffer

RAM

LabVIEW

INPUT OPERATION
OUTPUT OPERATION

RAM

Onboard FIFO

Output Rate

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PC
Buffer

ASIC
37

ADE (Application)
Memory

How does NI-DAQmx determine PC buffer size?

Rate sets rate of acquisition (sampling rate)

NI-DAQmx automatically determines PC buffer size based on rate

Sample Rate

Buffer
Size

No rate specified

10 kS

0-100 S/s

1 kS

100-10,000 S/s

10 kS

10,0001,000,000
S/s

100 kS

> 1,000,000 S/s

1 MS

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You can also manually set the buffer size


using the DAQmx Configure Input Buffer VI

38

Possible Errors of Data Transfer: Bottleneck!!!


Input Rate

Onboard FIFO Bus Interface

PC Buffer

RAM

ADE (Application)
Memory

LabVIEW

Error -200361 Onboard memory overflow


FIFO will be overwritten:
Decrease the Samples per Channel per Second rate
Purchase a device with a larger FIFO

Error -200279 Overwrite error

Purchase a faster computer with a faster bus

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Each action needs a cause or


stimulus.
Triggering
Stimulus is here!
Nothing happens
Action
Start of Action

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Action caused by Triggering

Produces an action based on a stimulus

Ex: generate a waveform after receiving a digital pulse

NI-DAQmx supports several different trigger action types:


Start
Begin acquisition
Begin generation

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Reference
Acquisition starts with
software
Circular buffer is used
until reference trigger is
received
Returns pre- and posttrigger samples

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Pause
Pause when a trigger is
low
Resume when a trigger
is high

Action caused by Triggering

Produces an action based on a stimulus

Ex: generate a waveform after receiving a digital pulse

NI-DAQmx supports several different trigger action types:


Start
Begin acquisition
Begin generation

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Reference
Acquisition starts with
software
Circular buffer is used
until reference trigger is
received
Returns pre- and posttrigger samples

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Pause
Pause when a trigger is
low
Resume when a trigger
is high

Trigger Actions Reference Triggering

Acquisition starts as soon as software is started


Data in the buffer keeps getting overwritten (first
in first out) until the reference trigger is received
Typically only for finite input operations
Start acquire

Pre-trigger
data

Post-trigger
data

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Reference
Trigger

Counters....
What can I do with?
Edge counting
Single pulse and pulse train generation
Pulse, semi-period, and period width measurement
Frequency measurement
Position and velocity measurement

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Gate

A. What is a Counter?

To count based on the comparison of input signals (gate, source)


To generate pulses based upon inputs and register values

Parts of a Counter

Out

Two basic functions

Source

Count
Reg

Count Register
Source
Gate
Out

Terminology

Terminal Count
Resolution
Timebase

Maximum Rise/Fall Time = 50 ns

+5.0 V

+2.0 V
+0.8 V
0V

high

TTL
indeterminate
low
Minimum Pulse Width = 10 ns

Counter gate and source are PFI pins!!!!


DAQmx enables you to route them if assigned PFI are already in use!

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Edge Counting Non Buffered


Simple Edge Counting
Gate
Your Signal

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Sourc
Count Register
e
Source

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Out

Edge Counting Non Buffered


Time Edge Counting
Gate
Timebase

Sourc
Count Register
e
Source

Out

Time elapsed = (count) x (timebase period)

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Edge Counting Non Buffered


Gate Edge Counting
Gate
Timebase

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Sourc
Count Register
e
Source

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Out

Edge Counting Continuous Buffered

Device latches the number of edges counted onto each active edge
of the sample clock and stores the number in the buffer

Clock can be an external signal or Timebase

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Edge Counting Continuous Buffered

Device latches the number of edges counted onto each active edge
of the sample clock and stores the number in the buffer

Clock can be an external signal or Timebase

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Pulse Measurement
(Period, Semi, Pulse Width)
Gate

Signal

Out

Source

Single or Continuous

Count Register

Timebase

Source
Period

Semi Period

Pulse Period

Armed

Gate

Semi

Armed

Pulse Width

Semi

Width

Armed

Source

Source

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Gate

Gate

Source

2
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Pulse Measurement
(Period, Semi, Pulse Width)
Gate

Signal

Out

Source

Single or Continuous

Count Register

Timebase

Source
Pulse Width

Width

Armed

Gate

Armed

Armed

Source

Source

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Gate

Gate

Source

2
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Pulse Generation
Gate

Out
Single Pulse
Count Register

Source

Timebase

Pulse Period
Pulse Frequency
Initial
Delay

High
Time

Finite Pulse Train


Continuous Pulse

Low
Time

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Duty Cycle

53

= High Time + Low Time


=

1
Pulse Period
High Time
Pulse Period

Pulse Generation
Gate

Out
Single Pulse
Count Register

Timebase
DAQmx Create Virtual Channel

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Source

DAQmx Create Virtual Channel

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Finite Pulse Train


Continuous Pulse

DAQmx Create Virtual Channel

Measurement : Quadrature Encoder


Light
Sensor
Shaft

Light
Source
Code Track
Channel A
Channel B

Rotating Disk

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Frequency Measurement
Does perform Period measurement and take the inverse???? Not always
precise!!

Low Frequency with 1Counter


Gate

Source

Signal

Count Register

Timebase

Source
Good when (f < timebase / 100)
Can see large error at high
frequencies due to phenomenon
called quantization error

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Out
Single or Continuous

Frequency Measurement
High Frequency with 2 Counters
CTR 0: Pulse Train Generation

CTR 1: Period Measurement

Gate

Out
CTR 0

CTR 1

Source
Internal timebase

Source
Signal being measured

Good when f ~ timebase


Edge Counting during a
know period of Time
created as multiple of the
timebase period.

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Frequency Measurement
Large Range with 2 Counters
CTR 0: Pulse Train Generation

CTR 1: Period Measurement


Gate

Out
CTR 0

CTR 1

Source
Signal being measured

Source
Internal timebase

Good for large range frequencies


Divide the unknown signal down
to a slower frequency
Perform period measurement on
that slower frequency

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Synchronization

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Time-Based Synchronization
Signal-Based

Share Physical Clocks / Triggers


Time-Based

Generate Signals

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Share Time

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Generate Signals

Requirements for Synchronization


1.

Simultaneous Start - Triggers

2.

Software-Timed Start
Hardware-Timed Start

Not drifting

Sharing Master Timebase


Sharing Master Sample Clock

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Sharing Singnals between Devices

RTSI
o

PXI Backplane Clocks


PXI_Trig
o

Similar to RTSI, uses PXI backplane

PXI Star Trigger


o

7 Lines. External Cable

Direct Connection to from Slot 2 controller

Chassis PFI Lines, Chassis Sync Modules

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Export Signals to Terminals - Routing

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Export Signals to Terminals - Routing

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Simultaneous Start

Software Timed Start


Sample Clock 1

Significant
Variability and
Time Delay Due
to OS

Sample Clock 2

Hardware Timed Start


Master Device
Sharing Triggers

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Timing Engine
Slave Device
Timing Engine

Methods to Synchronize Multiple Devices


Sharing Sample Clock
o

Sample Clock derived from master timebase or externally sourced


Master Device
ADC

Output
Delay
Routing
Delay

Sample Clock
Source
Slave Device
Input
Delay

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ADC

No Drift
Triggering not usually required
Skew resulting from clock routing delays
Devices must be running at same rate
Convert Clocks not Synchronized (MUXed boards)
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Methods to Synchronize Multiple Devices


1.

Timebase* + Trigger
Sharing a Master Timebase

Prevents phase discrepancies


Allows for different rates derived from the timebase

Sharing a Start Trigger

Verifies that tasks start synchronously

Master Device
Output
Delay

ADC

Routing
Delay

Timebase

Slave Device
Input
Delay

*Also known as a Reference Clock


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ADC

Coffee Break

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Moving from LabVIEW Desktop


to RT and FPGA programming

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Changing from the LabVIEW/DAQ Mindset

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The LabVIEW RIO Architecture

Analog Input
Processor

FPGA

Analog Output
Digital I/O
Custom I/O

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DAQ vs Intelligent Instruments


MIO DAQ

SW Designed Instruments

I/O Programming

Fixed ASIC for timing and


triggering

Open FPGA for timing and


triggering

Analog I/O

Multiplexed, shared sample


clock

Simultaneous or independent
operation

Digital I/O

Up to 32 lines,
Correlated DIO

Up to 160 lines,
hardware timed

Onboard Counters

4 purpose counters

Custom counters on any digital


line

High Speed Control

Jitter, Software Timed

RT OS and
FPGA Determinism

Digital Communiction
Protocols

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Open FPGA for digital timing


and protocol simulation

DAQmx for DIO

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1 - Using the LabVIEW Project

Development PC

CompactRIO

Testbench: simulate
FPGA logic

Analyze FPGA
Data

Acquire I/O

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2 - LabVIEW FPGA I/O Nodes

Directly connected to I/O pins


Use I/O Nodes to acquire and generate data
Data rates are defined by the Analog and Digital modules
With DAQmx, you get multiple samples per loop iteration
With LabVIEW FPGA, the FPGA acquires one data value
per loop iteration.

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2 - LabVIEW FPGA I/O Nodes

Digital Line Writes/reads Boolean


value to/from digital line
Digital Port (grouping of digital lines)
Writes/reads unsigned
integer value to/from digital port
Analog I/O Writes/reads data to/from
an analog channel

R Series Integer values


CompactRIO Fixed-point values

Other

Motion
CAN

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3 - Fixed-Point Math
Floating Point: 0.5*0.5=0.25
Fixed Point: 1.1 (2^0 + 2^-1)

sign=+ | integer =1 | fraction = 1]

Rational
Number

Fixed-Point
Equivalent

Bits represented

1.5

0001.1000

8 total bits, 4 integer bits

1.5

00000001.10000000

16 total bits, 8 integer bits

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4 - Understanding Clocks

A While Loop will execute at the rate specified in the


Loop Timer function, either in ticks, ms, or s.

A Timed Loop on FPGA runs at 40MHz by default, based on the Onboard Clock

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4 - Understanding Clocks

The enable chain includes


registers between each node
that store values and execute at
the rising edge of the clock

A Timed Loop on FPGA is called a


Single Cycle Timed Loop (SCTL)

Removes registers
Uses less resources
Code executes in 1 clock cycle
Not all functions are supported*

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5 - Transferring Data to the Processor

The Read/Write Controls method is recommended for


communicating current value data

Acquire I/O

Analyze
FPGA Data

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5 - Transferring Data to the Processor

Direct Memory Access (DMA) FIFOs are an efficient mechanism for


streaming data from the FPGA to RTOS
Does not involve processor resources
FPGA hardware targets have between 3-16 dedicated DMA
channels

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6 - Test and Compile


LabVIEW FPGA
Code

Translation
VHDL
Generation

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Compile VHDL through Xilinx

Synthesis

Optimization
Logic
Reduction

Place&Route
Timing
Verification

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FPGA Logic
Implementation

Bit Stream
Generation
Download &
Run

Desktop Execution Node


Demonstration
Enables users to create test benches for
FPGA VIs
Debugging and verification can be
performed without making any changes to
the FPGA VI

Testbench: simulate
FPGA logic

Desktop

File I/O or
Simulated Signal

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FPGA VI Results

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What is Real-Time?

Real-time does not always mean really fast


Real-time means absolute reliability
Real-time systems have timing constraints that
must be met to avoid failure
Determinism is the ability to complete a task
within a fixed amount of time

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7 - Working with Constrained Resources

EFFECT

Disk Space

Lost Data

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RAM

CPU Bandwidth

Crash

Starvation

85

FPGA Gates

Compile
Failure

8 - Implementing High Priority Tasks


Critical Loop(s)

Auxiliary Loop(s)

Inter-loop
Communication

Deterministic Operations

Non-Deterministic Operations

PID control
Motion control
Shutdown logic
FPGA data transfer

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File I/O
Network communication
Dynamic memory
allocation
Non-deterministic library
or driver calls
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9 - LabVIEW RT Watchdog

Reboots system if the watchdog process is starved


This could occur if:

CPU usage hits 100%


Software is hanging because it ran out of memory

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10 - A Different Model for Development,


Debugging, and Deployment
Web Thin-Client

Component Display
Mobile

Networked Connection
Embedded Device
Touch Panel Computer

Embedded UI
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LabVIEW 2014 Real-Time with Embedded UI


Simplify system complexity by implementing a local HMI on CompactRIO

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Additional Resources

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NI LabVIEW for CompactRIO Developers Guide

ni.com/compactriodevguide
High Performance RIO Developers Guide:
ni.com/hprioguide

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LabVIEW Embedded Training Courses

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92

Next events
SSP Training day
Torino 1 Aprile
Milano 13 Aprile
Padova 16 Aprile
Roma 21 Aprile

NI Days 2015
Milano 12 Marzo

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Thanks ... Questions ?

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