Professional Documents
Culture Documents
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LabVIEW 2014
Whats New in LabVIEW 2014
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13 Coding Productivity
Enhancing Features
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Innovate With a
Community
13 Coding Productivity
Enhancing Features
italy.ni.com/labview-developer-tour
Innovate With a
Community
Performance CompactRIO
USB3 CVS
VirtualBench
.
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13 Coding Productivity
Enhancing Features
italy.ni.com/labview-developer-tour
Innovate With a
Community
NI LabVIEW Embedded
Control and Monitoring Suite
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Professional Edition
Trace low-level bugs,
validate coding practices,
and manipulate data
through the now included:
VI Analyzer Toolkit
Unit Test Framework Toolkit
Desktop Execution Trace Toolkit
Database Connectivity Toolkit
Report Generation Toolkit
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32-bit
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64-bit
14
LabVIEW 32-Bit
Not all LabVIEW modules and toolkits All LabVIEW modules and toolkits are
are available for LabVIEW 64-bit
available for LabVIEW 32-bit
15
Windows
Mac OS X
Linux
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MathScript RT Module
Re-use .m scripts that you developed in
MathWorks Inc. MATLAB or GNU Octave
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CPU
Improved Usability
Prototype and generate code using
Vision Assistant to design high
performance vision systems
FPGA
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19
13 Coding Productivity
Enhancing Features
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Innovate With a
Community
13 Coding Productivity
Enhancing Features
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Innovate With a
Community
User Community
Over 10,000 certified users
Over 800 alliance partners
80+ registered user groups
Connectivity
Over 10,000 instrument drivers
Any bus, any protocol, any platform
Integration with third-party languages
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LabVIEW
Web Browser
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Spreadsheet Toolkits
New on the LabVIEW Tools Network
Spreadsheet Express
XLR8
by Aledyne Engineering
by DATA AHEAD
ni.com/labviewtools/spreadsheetexpress
ni.com/labviewtools/xlr8
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26
Renewal
nth Year
Today
Ontime
Auto-Renewal
o
o
Multi-Year
o
o
Discount
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Agenda
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Bus/CPU
Sensors
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Actuators
Bus/CPU
Sensors
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Actuators
Bus/CPU
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Actuators
Sensors
NI-STC - ASIC
Bus
Master
DMA
IRQ
Engines
Input/
Output
Lines
Input /
Output
Timing
Engines
Triggers
Counters
RTSI /
PFI
Routing
Bus
Interface
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Measurements Modules
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Configure
Channel
Configure
Timing
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Configure
Start
Triggering Acquisition
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Read
Data
Clear
Task
ADE (Application)
Memory
PC Buffer
RAM
LabVIEW
INPUT OPERATION
OUTPUT OPERATION
RAM
Onboard FIFO
Output Rate
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PC
Buffer
ASIC
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ADE (Application)
Memory
Sample Rate
Buffer
Size
No rate specified
10 kS
0-100 S/s
1 kS
100-10,000 S/s
10 kS
10,0001,000,000
S/s
100 kS
1 MS
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PC Buffer
RAM
ADE (Application)
Memory
LabVIEW
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Reference
Acquisition starts with
software
Circular buffer is used
until reference trigger is
received
Returns pre- and posttrigger samples
41
Pause
Pause when a trigger is
low
Resume when a trigger
is high
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Reference
Acquisition starts with
software
Circular buffer is used
until reference trigger is
received
Returns pre- and posttrigger samples
42
Pause
Pause when a trigger is
low
Resume when a trigger
is high
Pre-trigger
data
Post-trigger
data
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Reference
Trigger
Counters....
What can I do with?
Edge counting
Single pulse and pulse train generation
Pulse, semi-period, and period width measurement
Frequency measurement
Position and velocity measurement
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Gate
A. What is a Counter?
Parts of a Counter
Out
Source
Count
Reg
Count Register
Source
Gate
Out
Terminology
Terminal Count
Resolution
Timebase
+5.0 V
+2.0 V
+0.8 V
0V
high
TTL
indeterminate
low
Minimum Pulse Width = 10 ns
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Sourc
Count Register
e
Source
46
Out
Sourc
Count Register
e
Source
Out
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Sourc
Count Register
e
Source
48
Out
Device latches the number of edges counted onto each active edge
of the sample clock and stores the number in the buffer
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Device latches the number of edges counted onto each active edge
of the sample clock and stores the number in the buffer
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Pulse Measurement
(Period, Semi, Pulse Width)
Gate
Signal
Out
Source
Single or Continuous
Count Register
Timebase
Source
Period
Semi Period
Pulse Period
Armed
Gate
Semi
Armed
Pulse Width
Semi
Width
Armed
Source
Source
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Gate
Gate
Source
2
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Pulse Measurement
(Period, Semi, Pulse Width)
Gate
Signal
Out
Source
Single or Continuous
Count Register
Timebase
Source
Pulse Width
Width
Armed
Gate
Armed
Armed
Source
Source
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Gate
Gate
Source
2
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Pulse Generation
Gate
Out
Single Pulse
Count Register
Source
Timebase
Pulse Period
Pulse Frequency
Initial
Delay
High
Time
Low
Time
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Duty Cycle
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1
Pulse Period
High Time
Pulse Period
Pulse Generation
Gate
Out
Single Pulse
Count Register
Timebase
DAQmx Create Virtual Channel
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Source
54
Light
Source
Code Track
Channel A
Channel B
Rotating Disk
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Frequency Measurement
Does perform Period measurement and take the inverse???? Not always
precise!!
Source
Signal
Count Register
Timebase
Source
Good when (f < timebase / 100)
Can see large error at high
frequencies due to phenomenon
called quantization error
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Out
Single or Continuous
Frequency Measurement
High Frequency with 2 Counters
CTR 0: Pulse Train Generation
Gate
Out
CTR 0
CTR 1
Source
Internal timebase
Source
Signal being measured
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Frequency Measurement
Large Range with 2 Counters
CTR 0: Pulse Train Generation
Out
CTR 0
CTR 1
Source
Signal being measured
Source
Internal timebase
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Synchronization
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Time-Based Synchronization
Signal-Based
Generate Signals
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Share Time
61
Generate Signals
2.
Software-Timed Start
Hardware-Timed Start
Not drifting
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RTSI
o
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Simultaneous Start
Significant
Variability and
Time Delay Due
to OS
Sample Clock 2
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Timing Engine
Slave Device
Timing Engine
Output
Delay
Routing
Delay
Sample Clock
Source
Slave Device
Input
Delay
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ADC
No Drift
Triggering not usually required
Skew resulting from clock routing delays
Devices must be running at same rate
Convert Clocks not Synchronized (MUXed boards)
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Timebase* + Trigger
Sharing a Master Timebase
Master Device
Output
Delay
ADC
Routing
Delay
Timebase
Slave Device
Input
Delay
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ADC
Coffee Break
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Analog Input
Processor
FPGA
Analog Output
Digital I/O
Custom I/O
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SW Designed Instruments
I/O Programming
Analog I/O
Simultaneous or independent
operation
Digital I/O
Up to 32 lines,
Correlated DIO
Up to 160 lines,
hardware timed
Onboard Counters
4 purpose counters
RT OS and
FPGA Determinism
Digital Communiction
Protocols
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Development PC
CompactRIO
Testbench: simulate
FPGA logic
Analyze FPGA
Data
Acquire I/O
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Other
Motion
CAN
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3 - Fixed-Point Math
Floating Point: 0.5*0.5=0.25
Fixed Point: 1.1 (2^0 + 2^-1)
Rational
Number
Fixed-Point
Equivalent
Bits represented
1.5
0001.1000
1.5
00000001.10000000
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4 - Understanding Clocks
A Timed Loop on FPGA runs at 40MHz by default, based on the Onboard Clock
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4 - Understanding Clocks
Removes registers
Uses less resources
Code executes in 1 clock cycle
Not all functions are supported*
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Acquire I/O
Analyze
FPGA Data
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Translation
VHDL
Generation
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Synthesis
Optimization
Logic
Reduction
Place&Route
Timing
Verification
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FPGA Logic
Implementation
Bit Stream
Generation
Download &
Run
Testbench: simulate
FPGA logic
Desktop
File I/O or
Simulated Signal
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FPGA VI Results
83
What is Real-Time?
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EFFECT
Disk Space
Lost Data
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RAM
CPU Bandwidth
Crash
Starvation
85
FPGA Gates
Compile
Failure
Auxiliary Loop(s)
Inter-loop
Communication
Deterministic Operations
Non-Deterministic Operations
PID control
Motion control
Shutdown logic
FPGA data transfer
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File I/O
Network communication
Dynamic memory
allocation
Non-deterministic library
or driver calls
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9 - LabVIEW RT Watchdog
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Component Display
Mobile
Networked Connection
Embedded Device
Touch Panel Computer
Embedded UI
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Additional Resources
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ni.com/compactriodevguide
High Performance RIO Developers Guide:
ni.com/hprioguide
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Next events
SSP Training day
Torino 1 Aprile
Milano 13 Aprile
Padova 16 Aprile
Roma 21 Aprile
NI Days 2015
Milano 12 Marzo
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