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PIC16F8X

18-pin Flash/EEPROM 8-Bit Microcontrollers

Devices Included in this Data Sheet:

Pin Diagrams

PIC16F83
PIC16F84
PIC16CR83
PIC16CR84
Extended voltage range devices available
(PIC16LF8X, PIC16LCR8X)

PDIP, SOIC

High Performance RISC CPU Features:
• Only 35 single word instructions to learn
• All instructions single cycle except for program
branches which are two-cycle
• Operating speed: DC - 10 MHz clock input
DC - 400 ns instruction cycle
Device

Program
Memory
(words)

PIC16F83

Data
Data
RAM
EEPROM
(bytes) (bytes)

Max.
Freq
(MHz)

512 Flash

36

64

10

PIC16F84
1 K Flash
PIC16CR83 512 ROM

68
36

64
64

10
10

PIC16CR84 1 K ROM

68

64

10

14-bit wide instructions
8-bit wide data path
15 special function hardware registers
Eight-level deep hardware stack
Direct, indirect and relative addressing modes
Four interrupt sources:
- External RB0/INT pin
- TMR0 timer overflow
- PORTB<7:4> interrupt on change
- Data EEPROM write complete
• 1000 erase/write cycles Flash program memory
• 10,000,000 erase/write cycles EEPROM data memory
• EEPROM Data Retention > 40 years

RA2

•1

18

RA1

RA3

2

17

RA0

RA4/T0CKI

3

16

OSC1/CLKIN

MCLR

4

15

OSC2/CLKOUT

VSS

5

14

VDD

RB0/INT

6

13

RB7

RB1

7

12

RB6

RB2

8

11

RB5

RB3

9

10

RB4

PIC16F8X
PIC16CR8X





Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™) - via two
pins (ROM devices support only Data EEPROM
programming)
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Code-protection
• Power saving SLEEP mode
• Selectable oscillator options






CMOS Flash/EEPROM Technology:

Peripheral Features:

• Low-power, high-speed technology
• Fully static design
• Wide operating voltage range:
- Commercial: 2.0V to 6.0V
- Industrial:
2.0V to 6.0V
• Low power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 15 µA typical @ 2V, 32 kHz
- < 1 µA typical standby current @ 2V

• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
- 25 mA sink max. per pin
- 20 mA source max. per pin
• TMR0: 8-bit timer/counter with 8-bit
programmable prescaler

 1998 Microchip Technology Inc.

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DS30430C-page 1

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PIC16F8X
Table of Contents
1.0 General Description ...................................................................................................................................................................... 3
2.0 PIC16F8X Device Varieties .......................................................................................................................................................... 5
3.0 Architectural Overview.................................................................................................................................................................. 7
4.0 Memory Organization ................................................................................................................................................................. 11
5.0 I/O Ports...................................................................................................................................................................................... 21
6.0 Timer0 Module and TMR0 Register............................................................................................................................................ 27
7.0 Data EEPROM Memory.............................................................................................................................................................. 33
8.0 Special Features of the CPU ...................................................................................................................................................... 37
9.0 Instruction Set Summary ............................................................................................................................................................ 53
10.0 Development Support ................................................................................................................................................................. 69
11.0 Electrical Characteristics for PIC16F83 and PIC16F84.............................................................................................................. 73
12.0 Electrical Characteristics for PIC16CR83 and PIC16CR84........................................................................................................ 85
13.0 DC & AC Characteristics Graphs/Tables.................................................................................................................................... 97
14.0 Packaging Information .............................................................................................................................................................. 109
Appendix A: Feature Improvements - From PIC16C5X To PIC16F8X .......................................................................................... 113
Appendix B: Code Compatibility - from PIC16C5X to PIC16F8X.................................................................................................. 113
Appendix C: What’s New In This Data Sheet................................................................................................................................. 114
Appendix D: What’s Changed In This Data Sheet ......................................................................................................................... 114
Appendix E: Conversion Considerations - PIC16C84 to PIC16F83/F84 And PIC16CR83/CR84.................................................. 115
Index ................................................................................................................................................................................................. 117
On-Line Support................................................................................................................................................................................. 119
Reader Response .............................................................................................................................................................................. 120
PIC16F8X Product Identification System ........................................................................................................................................... 121
Sales and Support.............................................................................................................................................................................. 121

To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of
time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you
find any information that is missing or appears in error, please use the reader response form in the back of this data
sheet to inform us. We appreciate your assistance in making this a better document.

DS30430C-page 2

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 1998 Microchip Technology Inc.

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PIC16F8X
1.0

GENERAL DESCRIPTION

The PIC16F8X is a group in the PIC16CXX family of
low-cost, high-performance, CMOS, fully-static, 8-bit
microcontrollers. This group contains the following
devices:



PIC16F83
PIC16F84
PIC16CR83
PIC16CR84

All PICmicro™ microcontrollers employ an advanced
RISC architecture. PIC16F8X devices have enhanced
core features, eight-level deep stack, and multiple
internal and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with a separate
8-bit wide data bus. The two stage instruction pipeline
allows all instructions to execute in a single cycle,
except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set is
used to achieve a very high performance level.
PIC16F8X microcontrollers typically achieve a 2:1 code
compression and up to a 4:1 speed improvement (at 20
MHz) over other 8-bit microcontrollers in their class.
The PIC16F8X has up to 68 bytes of RAM, 64 bytes of
Data EEPROM memory, and 13 I/O pins. A timer/
counter is also available.
The PIC16CXX family has special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP
oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power saving.
The user can wake the chip from sleep through several
external and internal interrupts and resets.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lockup.

Table 1-1 lists the features of the PIC16F8X. A simplified block diagram of the PIC16F8X is shown in
Figure 3-1.
The PIC16F8X fits perfectly in applications ranging
from high speed automotive and appliance motor
control to low-power remote sensors, electronic locks,
security devices and smart cards. The Flash/EEPROM
technology makes customization of application
programs (transmitter codes, motor speeds, receiver
frequencies, security codes, etc.) extremely fast and
convenient. The small footprint packages make this
microcontroller series perfect for all applications with
space limitations. Low-cost, low-power, high
performance, ease-of-use and I/O flexibility make the
PIC16F8X very versatile even in areas where no
microcontroller use has been considered before
(e.g., timer functions; serial communication; capture,
compare and PWM functions; and co-processor
applications).
The serial in-system programming feature (via two
pins) offers flexibility of customizing the product after
complete assembly and testing. This feature can be
used to serialize a product, store calibration data, or
program the device with the current firmware before
shipping.

1.1

Family and Upward Compatibility

Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for PIC16C5X devices can be easily ported to
PIC16F8X devices (Appendix B).

1.2

Development Support

The PIC16CXX family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A “C” compiler and fuzzy
logic support tools are also available.

The devices with Flash program memory allow the
same device package to be used for prototyping and
production. In-circuit reprogrammability allows the
code to be updated without the device being removed
from the end application. This is useful in the
development of many applications where the device
may not be easily accessible, but the prototypes may
require code updates. This is also useful for remote
applications where the code may need to be updated
(such as rate information).

 1998 Microchip Technology Inc.

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DS30430C-page 3

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com  1998 Microchip Technology Inc. SOIC Peripherals Timer Module(s) Features PIC16F84 Maximum Frequency of Operation (MHz) All PICmicro™ Family devices have Power-on Reset. SOIC 18-pin DIP.agelectronica. SOIC 18-pin DIP.0-6.com PIC16F8X TABLE 1-1 PIC16F8X FAMILY OF DEVICES PIC16CR83 PIC16F83 Clock Memory PIC16CR84 10 10 10 10 Flash Program Memory 512 — 1K — EEPROM Program Memory — — — — ROM Program Memory — 512 — 1K Data Memory (bytes) 36 36 68 68 Data EEPROM (bytes) 64 64 64 64 TMR0 TMR0 TMR0 TMR0 Interrupt Sources 4 4 4 4 I/O Pins 13 13 13 13 Voltage Range (Volts) 2. All PIC16F8X Family devices use serial programming with clock pin RB6 and data pin RB7.com . selectable Watchdog Timer.0-6. SOIC 18-pin DIP. DS30430C-page 4 www.0 2.0 2.agelectronica.0-6.agelectronica.www.com www.0 2.0 Packages 18-pin DIP.0-6. selectable code protect and high I/O current capability.agelectronica. www.

com PIC16F8X 2. or by device programmers. as in PIC16F84. 1. 2. F. When discussing memory maps and other architectural features. 2.4 ROM Devices Some of Microchip’s devices have a corresponding device where the program memory is a ROM. Serial programming allows each device to have a unique number which can serve as an entry-code. please contact your Microchip Regional Sales Office.agelectronica.3 Serialized Quick-TurnaroundProduction (SQTP SM ) Devices Microchip offers the unique programming service where a few user-defined locations in each device are programmed with different serial numbers. For information on submitting a QTP code. Depending on application and production requirements the proper device option can be selected using the information in this section.0 PIC16F8X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. even though the device can be erased and reprogrammed. Flash Devices These devices are offered in the lower cost plastic package. 4.com DS30430C-page 5 www.agelectronica. LF. These devices have Flash program memory and operate over an extended voltage range. There are four device “types” as indicated in the device number. The user may program this information into the Data EEPROM. The devices have all Flash locations and configuration options already programmed by the factory.com www. The serial numbers may be random. These devices give a cost savings over Microchip’s traditional user programmed devices (EPROM. please contact your Microchip Regional Sales Office. LCR. EEPROM). such as Microchip's PICSTART® Plus or PRO MATE® II programmers. CR. These devices have ROM program memory and operate over an extended voltage range. www.agelectronica. pseudo-random or sequential. as in PIC16LCR84.2 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for factory production orders. These devices have Flash program memory and operate over the standard voltage range. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. For information on submitting a SQTP code. For information on submitting a ROM code.com . Certain code and prototype verification procedures do apply before production shipments are available. as in PIC16CR83. When placing orders. ROM devices (PIC16CR8X) do not allow serialization information in the program memory space. This allows the same device to be used for prototype development and pilot programs as well as production. A further advantage of the electrically-erasable Flash version is that it can be erased and reprogrammed incircuit. 3.www. as in PIC16LF84. 2. the use of F and CR also implies the LF and LCR versions. please use the “PIC16F8X Product Identification System” at the back of this data sheet to specify the correct part number.1 2.  1998 Microchip Technology Inc.agelectronica. These devices have ROM program memory and operate over the standard voltage range. password or ID number. please contact your Microchip Regional Sales Office. 2.

www.agelectronica.www.com  1998 Microchip Technology Inc.com PIC16F8X NOTES: DS30430C-page 6 www.com .agelectronica.agelectronica.agelectronica.com www.

The full 14-bit wide program memory bus fetches a 14-bit instruction in a single cycle.com PIC16F8X 3. subtraction. It is not an addressable register. To begin with. The PIC16F83 and PIC16CR83 address 512 x 14 of program memory. All special function registers including the program counter are mapped in the data memory. the ALU may affect the values of the Carry (C). PIC16CXX devices contain an 8-bit ALU and working register. PIC16CXX opcodes are 14-bits wide.www. arithmetic operations are two's complement in nature. shift and logical operations.agelectronica. Consequently. In two-operand instructions. the operand is either the W register or a file register. all instructions execute in a single cycle except for program branches. The W register is an 8-bit working register used for ALU operations. A simplified block diagram for the PIC16F8X is shown in Figure 3-1. The ALU is 8-bits wide and capable of addition. typically one operand is the working register (W register).agelectronica. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). This architecture has the program and data accessed from separate memories. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16CXX simple yet efficient. It performs arithmetic and Boolean functions between data in the working register and any register file. The PIC16CXX can directly or indirectly address its register files or data memory. All program memory is internal. and Zero (Z) bits in the STATUS register. The ALU is a general purpose arithmetic unit.agelectronica. Depending on the instruction executed.agelectronica. So the device has a program memory bus and a data memory bus. www. its corresponding pin description is shown in Table 3-1. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory (accesses over the same bus). and the PIC16F84 and PIC16CR84 address 1K x 14 program memory. the learning curve is reduced significantly.com DS30430C-page 7 www. Unless otherwise mentioned.  1998 Microchip Technology Inc. and the other operand is a file register or an immediate constant. in subtraction. Digit Carry (DC). An orthogonal (symmetrical) instruction set makes it possible to carry out any operation on any register using any addressing mode. The C and DC bits operate as a borrow and digit borrow out bit. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. In addition. respectively. In single operand instructions. enabling single word instructions.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. See the SUBLW and SUBWF instructions for examples.com .com www. the PIC16CXX uses a Harvard architecture.

com MCLR VDD.com .com PIC16F8X FIGURE 3-1: PIC16F8X BLOCK DIAGRAM Data Bus 13 Program Bus 8 Program Counter Flash/ROM Program Memory PIC16F83/CR83 512 x 14 PIC16F84/CR84 1K x 14 8 Level Stack (13-bit) 14 EEPROM Data Memory RAM File Registers PIC16F83/CR83 36 x 8 PIC16F84/CR84 68 x 8 7 EEDATA RAM Addr EEPROM Data Memory 64 x 8 EEADR Addr Mux Instruction reg 7 Direct Addr 5 TMR0 Indirect Addr FSR reg RA4/T0CKI STATUS reg 8 MUX Power-up Timer Instruction Decode & Control Timing Generation Oscillator Start-up Timer 8 ALU Power-on Reset Watchdog Timer I/O Ports RA3:RA0 W reg RB7:RB1 RB0/INT OSC2/CLKOUT OSC1/CLKIN DS30430C-page 8 www.agelectronica. www.agelectronica. VSS  1998 Microchip Technology Inc.www.agelectronica.com www.agelectronica.

www. OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1.com DS30430C-page 9 www. RA3 2 2 I/O TTL RA4/T0CKI 3 3 I/O ST Can also be selected to be the clock input to the TMR0 timer/counter. RB5 11 11 I/O TTL Interrupt on change pin. MCLR 4 4 I/P ST Master clear (reset) input/programming voltage input. www.agelectronica. In RC mode. Serial programming data. Legend: I= input O = output I/O = Input/Output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Output is open drain type.  1998 Microchip Technology Inc. Connects to crystal or resonator in crystal oscillator mode. RB6 12 12 I/O TTL/ST (2) RB7 13 13 I/O TTL/ST (2) VSS 5 5 P — Ground reference for logic and I/O pins. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.com www.com PIC16F8X TABLE 3-1 PIC16F8X PINOUT DESCRIPTION DIP No.com .agelectronica.agelectronica. This pin is an active low reset to the device. VDD 14 14 P — Positive supply for logic and I/O pins. PORTA is a bi-directional I/O port. OSC1/CLKIN 16 16 I OSC2/CLKOUT 15 15 O — Oscillator crystal output. RB0/INT 6 6 I/O TTL/ST (1) RB1 7 7 I/O TTL RB0/INT can also be selected as an external interrupt pin. Serial programming clock. SOIC No.agelectronica. Interrupt on change pin. RB2 8 8 I/O TTL RB3 9 9 I/O TTL RB4 10 10 I/O TTL Interrupt on change pin. Interrupt on change pin. RA0 17 17 I/O TTL RA1 18 18 I/O TTL RA2 1 1 I/O TTL Pin Name I/O/P Type Buffer Type Description ST/CMOS (3) Oscillator crystal input/external clock source input. and denotes the instruction cycle rate.

DS30430C-page 10 www. Q3 and Q4). GOTO) then two cycles are required to complete the instruction (Example 3-1). Internally. Data memory is read during Q2 (operand read) and written during Q4 (destination write). Q3. and Q4 cycles. the fetched instruction is latched into the “Instruction Register” in cycle Q1. If an instruction causes the program counter to change (e. Q2.agelectronica.com . Q2. FIGURE 3-2: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase clock Q3 Q4 PC PC OSC2/CLKOUT (RC mode) EXAMPLE 3-1: Fetch INST (PC) Execute INST (PC-1) PC+2 Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) INSTRUCTION PIPELINE FLOW 1. BIT3 Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle. due to the pipelining.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1.. MOVLW 55h 2. The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle.www. Q3 and Q4. CALL SUB_1 4. Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1.agelectronica.agelectronica. This instruction is then decoded and executed during the Q2.com  1998 Microchip Technology Inc.agelectronica. In the execution cycle. The instruction is decoded and executed during the following Q1 through Q4.com PIC16F8X 3.com www. the program counter (PC) is incremented every Q1. www. except for any program branches. However. BSF PC+1 PORTA.g. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. each instruction effectively executes in one cycle. MOVWF PORTB 3. The clocks and instruction execution flow is shown in Figure 3-2. the instruction is fetched from the program memory and latched into the instruction register in Q4.1 Clocking Scheme/Instruction Cycle 3. A fetch cycle begins with the Program Counter (PC) incrementing in Q1.

com DS30430C-page 11 www.0.agelectronica. and 1C20h will be the same instruction.com .agelectronica. C20h.com www. For the PIC16F83 and PIC16CR83. For example.1 FIGURE 4-1: PROGRAM MEMORY MAP AND STACK PIC16F83/CR83 PC<12:0> 13 CALL.agelectronica. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module. the first 512 x 14 (0000h-01FFh) are physically implemented (Figure 4-1). The reset vector is at 0000h and the interrupt vector is at 0004h. This memory is not directly mapped into the data memory. so that access to each block can occur during the same oscillator cycle. www. 1020h. 4. for the PIC16F84 locations 20h. but is indirectly mapped. 1420h. That is. the first 1K x 14 (0000h-03FFh) are physically implemented (Figure 4-2). RETURN RETFIE. an indirect address pointer specifies the address of the data EEPROM memory to read/write. RETLW Stack Level 1 • • • Stack Level 8 User Memory Space 4. 1820h. The data memory area also contains the data EEPROM memory. Reset Vector 0000h Peripheral Interrupt Vector 0004h 1FFh Program Memory Organization The PIC16FXX has a 13-bit program counter capable of addressing an 8K x 14 program memory space.0 There are two memory blocks in the PIC16F8X. More details on the EEPROM memory can be found in Section 7. Each block has its own bus.www. 1FFFh FIGURE 4-2: PROGRAM MEMORY MAP AND STACK PIC16F84/CR84 PC<12:0> 13 CALL.com PIC16F8X MEMORY ORGANIZATION The data memory can further be broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the “core” are described here. These are the program memory and the data memory. 820h. RETLW Stack Level 1 • • • Stack Level 8 0000h 0004h User Memory Space Reset Vector Peripheral Interrupt Vector 3FFh 1FFFh  1998 Microchip Technology Inc. The 64 bytes of data EEPROM memory have the address range 0h-3Fh. Accessing a location above the physically implemented address will cause a wraparound. 420h. RETURN RETFIE. For the PIC16F84 and PIC16CR84.agelectronica.

Each Bank extends up to 7Fh (128 bytes).5).agelectronica. Banking requires the use of control bits for bank selection.5).agelectronica. The entire data memory can be accessed either directly using the absolute address of each register file or indirectly through the File Select Register (FSR) (Section 4. while the second is the General Purpose Registers (GPR) area. This is for both the SFR area and the GPR area. The first twelve locations of each Bank are reserved for the Special Function Registers. The first is the Special Function Registers (SFR) area.com PIC16F8X 4. Those associated with the core functions are described in this section. The special function registers can be classified into two sets. www.com www.agelectronica.2 Data Memory Organization 4. Bank 0 is selected by clearing the RP0 bit (STATUS<5>). Each GPR is 8 bits wide and is accessed either directly or indirectly through the FSR (Section 4. core and peripheral. Those related to the operation of the peripheral features are described in the section for that specific feature. Data memory is partitioned into two banks which contain the general purpose registers and the special function registers. Indirect addressing uses the present value of the RP1:RP0 bits for access into the banked areas of data memory.com . Figure 4-2 and Table 4-1) are used by the CPU and Peripheral functions to control the device operation. As an example.2.com  1998 Microchip Technology Inc.1 GENERAL PURPOSE REGISTER FILE The data memory is partitioned into two areas. Portions of data memory are banked.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (Figure 4-1.www. Instructions MOVWF and MOVF can move values from the W register to any location in the register file (“F”). The GPR addresses in bank 1 are mapped to addresses in bank 0. These registers are static RAM. and vice-versa. These control bits are located in the STATUS Register. The banked areas of the SFR are for the registers that control the peripheral functions. The remainder are General Purpose Registers implemented as static RAM.2. addressing location 0Ch or 8Ch will access the same GPR.agelectronica. Figure 4-1 and Figure 4-2 show the data memory map organization. The SFRs control the operation of the device. Setting the RP0 bit selects Bank 1. The GPR area is banked to allow greater than 116 bytes of general purpose RAM. DS30430C-page 12 www. 4. All devices have some amount of General Purpose Register (GPR) area.

com CFh D0h 7Fh FFh Bank 0 Bank 1 Unimplemented data memory location. Note 1: Not a physical register.(1) 01h TMR0 02h Indirect addr.agelectronica.(1) 07h File Address Indirect addr.www.com www. www.agelectronica.(1) 80h 87h 08h EEDATA EECON1 88h 08h EEDATA EECON1 88h 09h EEADR EECON2(1) 89h 09h EEADR EECON2(1) 89h 0Ah PCLATH PCLATH 8Ah 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Bh INTCON INTCON 8Bh 8Ch 0Ch 0Ch 36 General Purpose registers (SRAM) Mapped (accesses) in Bank 0 2Fh 30h 8Ch 68 General Purpose registers (SRAM) AFh B0h Mapped (accesses) in Bank 0 4Fh 50h 7Fh FFh Bank 0 Bank 1 Unimplemented data memory location. DS30430C-page 13 www.com . Note 1: Not a physical register. read as '0'. read as '0'.agelectronica.agelectronica.com PIC16F8X FIGURE 4-1: REGISTER FILE MAP PIC16F83/CR83 File Address FIGURE 4-2: REGISTER FILE MAP PIC16F84/CR84 File Address File Address 80h 00h Indirect addr.  1998 Microchip Technology Inc.(1) OPTION 81h 01h TMR0 OPTION 81h PCL PCL 82h 02h PCL PCL 82h 03h STATUS STATUS 83h 03h STATUS STATUS 83h 04h FSR FSR 84h 04h FSR FSR 84h 05h PORTA TRISA 85h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 06h PORTB TRISB 86h 87h 07h 00h Indirect addr.

---- ---.com . u = unchanged.com  1998 Microchip Technology Inc.agelectronica.---- ---0 x000 ---0 q000 ---.= unimplemented read as '0'.---- ---.---- ---0 0000 ---0 0000 0000 000x 0000 000u — — — 88h EECON1 89h EECON2 0Ah PCLATH — — — 0Bh INTCON GIE EEIE T0IE EEIF WRERR WREN WR RD EEPROM control register 2 (not a physical register) Write buffer for upper 5 bits of the PC (1) INTE RBIE T0IF INTF RBIF Legend: x = unknown.www. read as '0' 07h 08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu 09h EEADR EEPROM address register xxxx xxxx uuuu uuuu 0Ah PCLATH — — — 0Bh INTCON GIE EEIE T0IE Write buffer for upper 5 bits of the PC (1) INTE RBIE T0IF INTF ---0 0000 ---0 0000 RBIF 0000 000x 0000 000u ---. but the contents of PC<12:8> is never transferred to PCLATH. read as '0' ---.com PIC16F8X TABLE 4-1 Address REGISTER FILE SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets (Note3) Bank 0 00h INDF Uses contents of FSR to address data memory (not a physical register) ---.agelectronica. www. q = value depends on condition.---- IRP RP1 TO RP0 PD Z DC C Indirect data memory address pointer 0 Unimplemented location.---- ---.com www.agelectronica. 3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. PCLATH is a slave register for PC<12:8>.---- ---.---- 1111 1111 1111 1111 0000 0000 0000 0000 0001 1xxx 000q quuu Bank 1 80h INDF 81h OPTION_ REG 82h PCL 83h STATUS (2) 84h FSR 85h TRISA 86h TRISB 87h Uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 PD Z DC C Low order 8 bits of Program Counter (PC) IRP RP1 RP0 TO Indirect data memory address pointer 0 — — — PORTA data direction register xxxx xxxx uuuu uuuu ---1 1111 ---1 1111 PORTB data direction register 1111 1111 1111 1111 Unimplemented location. The contents of PCLATH can be transferred to the upper byte of the program counter. Note 1: The upper byte of the program counter is not directly accessible.---- ---. . DS30430C-page 14 www. 2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset.---- 01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h PCL Low order 8 bits of the Program Counter (PC) 0000 0000 0000 0000 03h STATUS (2) 0001 1xxx 000q quuu 04h FSR xxxx xxxx uuuu uuuu 05h PORTA — — — RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu ---.agelectronica.

1FFh) Each bank is 128 bytes. See the SUBLW and SUBWF instructions for examples. then the write to these three bits is disabled. the result of an instruction with the STATUS register as destination may be different than intended. The specified bit(s) will be updated according to device logic STATUS REGISTER (ADDRESS 03h.com . A subtraction is executed by adding the two’s complement of the second operand. in subtraction.agelectronica. These bits are set or cleared according to device logic. this bit is loaded with either the high or low order bit of the source register. Note 2: The C and DC bits operate as a borrow and digit borrow out bit. 1 (00h .  1998 Microchip Technology Inc.agelectronica.com PIC16F8X 4. BSF. RP1 should be maintained clear. This leaves the STATUS register as 000u u1uu (where u = unchanged). If the STATUS register is the destination for an instruction that affects the Z.2.17Fh) 11 = Bank 3 (180h . Furthermore. 3 (100h . CLRF STATUS will clear the upper-three bits and set the Z bit. DC or C bits. For rotate (RRF. Only bit RP0 is used by the PIC16F8X. Therefore.com www. Note 3: When the STATUS register is the destination for an instruction that affects the Z. Note 1: The IRP and RP1 bits (STATUS<7:6>) are not used by the PIC16F8X and should be programmed as cleared. bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 00 = Bank 0 (00h . bit 4: TO: Time-out bit 1 = After power-up.com DS30430C-page 15 www.FFh) 1 = Bank 2. For example. since this may affect upward compatibility with future products.1FFh) The IRP bit is not used by the PIC16F8X. then the write to these three bits is disabled. respectively. the TO and PD bits are not writable. CLRWDT instruction. or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (for ADDWF and ADDLW instructions) (For borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (for ADDWF and ADDLW instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note:For borrow the polarity is reversed. IRP should be maintained clear. read as ‘0’ .n = Value at POR reset IRP: Register Bank Select bit (used for indirect addressing) 0 = Bank 0. the STATUS register can be the destination for any instruction. www. SWAPF and MOVWF instructions should be used to alter the STATUS register (Table 9-2) because these instructions do not affect any status bit.7Fh) 01 = Bank 1 (80h . As with any register. the RESET status and the bank select bit for data memory.agelectronica. Use of these bits as general purpose R/W bits is NOT recommended. RLF) instructions.1 STATUS REGISTER The STATUS register contains the arithmetic status of the ALU.www. FIGURE 4-1: R/W-0 IRP bit7 bit 7: Only the BCF.2.agelectronica.FFh) 10 = Bank 2 (100h . 83h) R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit0 R = Readable bit W = Writable bit U = Unimplemented bit. DC or C bits.

www.2. the external INT interrupt. read as ‘0’ .agelectronica.agelectronica. and the weak pull-ups on PORTB.com  1998 Microchip Technology Inc.agelectronica.com PIC16F8X 4. FIGURE 4-1: R/W-1 RBPU bit7 Note: When the prescaler is assigned to the WDT (PSA = '1').2.com . TMR0.com www. OPTION_REG REGISTER (ADDRESS 81h) R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit0 bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled (by individual port latch values) bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to TMR0 R = Readable bit W = Writable bit U = Unimplemented bit.2 OPTION_REG REGISTER The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler. TMR0 has a 1:1 prescaler assignment.agelectronica.n = Value at POR reset bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 DS30430C-page 16 www. www.

please refer to Section 8.2. INTCON REGISTER (ADDRESS 0Bh.agelectronica. www. GIE (INTCON<7>). 8Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x EEIE T0IE INTE RBIE T0IF INTF RBIF bit0 R = Readable bit W = Writable bit U = Unimplemented bit.com .com DS30430C-page 17 www.agelectronica.www. read as ‘0’ .com www.agelectronica.5.agelectronica.n = Value at POR reset GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts Note: For the operation of the interrupt structure. FIGURE 4-1: R/W-0 GIE bit7 bit 7: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit.com PIC16F8X 4.2. bit 6: EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: INTE: RB0/INT Interrupt Enable bit 1 = Enables the RB0/INT interrupt 0 = Disables the RB0/INT interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 overflow interrupt flag bit 1 = TMR0 has overflowed (must be cleared in software) 0 = TMR0 did not overflow bit 1: INTF: RB0/INT Interrupt Flag bit 1 = The RB0/INT interrupt occurred 0 = The RB0/INT interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state  1998 Microchip Technology Inc.3 INTCON REGISTER Note: The INTCON register is a readable and writable register which contains the various enable bits for all interrupt sources.

The stack space is not part of either program or data space and the stack pointer is not readable or writable. The high byte of the PC (PC<12:8>) is not directly readable nor writable and comes from the PCLATH register. These are actions that occur from the execution of the CALL. The use of PCLATH<4:3> as general purpose R/W bits is not recommended since this may affect upward compatibility with future products. RETLW. care should be exercised if the table location crosses a PCL memory boundary (each 256 word block). The low byte is the PCL register.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). For future PIC16F8X program memory expansion.agelectronica.agelectronica. after the stack has been pushed eight times.www.4 The PIC16F8X ignores the PCLATH<4:3> bits. The PCLATH (PC latch high) register is a holding register for PC<12:8>. When doing a table read using a computed GOTO method. Therefore. If a CALL instruction (or interrupt) is executed.com  1998 Microchip Technology Inc. Note: There are no status bits to indicate stack overflow or stack underflow conditions.com www. If the stack is effectively popped nine times.agelectronica. there must be another two bits to specify the program memory page. That is. These paging bits come from the PCLATH<4:3> bits (Figure 4-1). PCLATH Note: PCH 12 11 10 PCL 0 8 7 PC GOTO. which are used for program memory pages 1. When doing a CALL or a GOTO instruction. and RETFIE instructions.3 Program Counter: PCL and PCLATH The Program Counter (PC) is 13-bits wide. FIGURE 4-1: LOADING OF PC IN DIFFERENT SITUATIONS PCH 12 PCL 8 7 0 INST with PCL as dest PC 8 PCLATH<4:0> 5 ALU result manipulation of the PCLATH<4:3> is not required for the return instructions (which “pops” the PC from the stack). Stack The PIC16FXX has an 8 deep x 13-bit wide hardware stack (Figure 4-1). Refer to the application note “Implementing a Table Read” (AN556). This occurs during a CALL. RETLW or a RETFIE instruction execution. the user must ensure that these page bits (PCLATH<4:3>) are programmed to the desired program memory page. Note: 4. The stack is “popped” in the event of a RETURN.3.3. The entire 13-bit PC is “pushed” onto the stack when a CALL instruction is executed or an interrupt is acknowledged.com . 4. the entire 13-bit PC is “pushed” onto the stack (see next section). The high bits of PC are loaded from PCLATH as shown in Figure 4-1.2 There are no instruction mnemonics called push or pop. the ninth push overwrites the value that was stored from the first push. which is a readable and writable register. PROGRAM MEMORY PAGING The PIC16F83 and PIC16CR83 have 512 words of program memory. CALL 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 4.1FFFh). The PIC16F84 and PIC16CR84 have 1K of program memory. This 11-bit address range allows a branch within a 2K program memory page size. the PC value is the same as the value from the first pop. The tenth push overwrites the second push (and so on).agelectronica. RETURN.com PIC16F8X 4. www. The contents of PCLATH are transferred to the upper byte of the program counter when the PC is loaded with a new value. PCLATH is not affected by a push or a pop operation. GOTO or a write to PCL. The stack operates as a circular buffer. DS30430C-page 18 www. 2 and 3 (0800h . or the vectoring to an interrupt address. The CALL and GOTO instructions have an 11-bit address range.

The INDF register is not a physical register. Reading INDF itself indirectly (FSR = 0) will produce 00h. HOW TO CLEAR RAM USING INDIRECT ADDRESSING movlw movwf clrf incf btfss goto 0x20 FSR INDF FSR FSR. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer).clear INDF register .NO. as shown in Figure 4-1.agelectronica.agelectronica.4 NEXT . Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). continue An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>). This is indirect addressing.com .www.5 Indirect Addressing.com www.  1998 Microchip Technology Inc.initialize pointer .agelectronica.com DS30430C-page 19 www. 2: PIC16F84 and PIC16CR84 devices 3: For memory map detail see Figure 4-1.inc pointer .YES. www.com PIC16F8X 4. INDF and FSR Registers A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2. However. to RAM . EXAMPLE 4-2: EXAMPLE 4-1: NEXT INDIRECT ADDRESSING • • • • Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h • Increment the value of the FSR register by one (FSR = 06) • A read of the INDF register now will return the value of 0Ah. clear next CONTINUE : .agelectronica.all done? . IRP is not used in the PIC16F8X. FIGURE 4-1: DIRECT/INDIRECT ADDRESSING Indirect Addressing Direct Addressing RP1 RP0 6 bank select from opcode 0 IRP location select 7 bank select 00 01 10 11 not used not used Bank 2 Bank 3 (FSR) 0 location select 00h 00h 0Bh 0Ch Data Memory (3) Addresses map back to Bank 0 2Fh (1) 30h (1) 4Fh (2) 50h (2) 7Fh 7Fh Bank 0 Bank 1 Note 1: PIC16F83 and PIC16CR83 devices.

www.com PIC16F8X NOTES: DS30430C-page 20 www. www.agelectronica.com .com  1998 Microchip Technology Inc.agelectronica.agelectronica.agelectronica.com www.

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PIC16F8X
5.0

I/O PORTS

EXAMPLE 5-1:

The PIC16F8X has two ports, PORTA and PORTB.
Some port pins are multiplexed with an alternate function for other features on the device.

5.1

PORTA and TRISA Registers

PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. All other RA port pins
have TTL input levels and full CMOS output drivers. All
pins have data direction bits (TRIS registers) which can
configure these pins as output or input.
Setting a TRISA bit (=1) will make the corresponding
PORTA pin an input, i.e., put the corresponding output
driver in a hi-impedance mode. Clearing a TRISA bit
(=0) will make the corresponding PORTA pin an output,
i.e., put the contents of the output latch on the selected
pin.
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.

INITIALIZING PORTA

CLRF

PORTA

BSF
MOVLW

STATUS, RP0
0x0F

MOVWF

TRISA

FIGURE 5-2:

;
;
;
;
;
;
;
;
;
;
;

Initialize PORTA by
setting output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA4 as outputs
TRISA<7:5> are always
read as '0'.

BLOCK DIAGRAM OF PIN RA4

Data
bus
WR
PORT

D

Q

CK

Q

N
VSS
WR
TRIS

The RA4 pin is multiplexed with the TMR0 clock input.

D

Q

CK

Q

Schmitt
Trigger
input
buffer

TRIS Latch

FIGURE 5-1:

BLOCK DIAGRAM OF PINS
RA3:RA0

Data
bus

RD TRIS
D

WR
Port

RA4 pin

Data Latch

Q
Q

VDD
CK

Q

D
EN
EN

P
RD PORT

Data Latch
N
D
WR
TRIS

I/O pin

Q
VSS

CK

TMR0 clock input
Note: I/O pin has protection diodes to VSS only.

Q

TRIS Latch

TTL
input
buffer

RD TRIS
Q

D

EN
RD PORT

Note: I/O pins have protection diodes to VDD and VSS.

 1998 Microchip Technology Inc.

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DS30430C-page 21

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PIC16F8X
TABLE 5-1

PORTA FUNCTIONS

Name

Bit0

Buffer Type

RA0
RA1
RA2
RA3
RA4/T0CKI

bit0
bit1
bit2
bit3
bit4

TTL
TTL
TTL
TTL
ST

Function

Input/output
Input/output
Input/output
Input/output
Input/output or external clock input for TMR0.
Output is open drain type.
Legend: TTL = TTL input, ST = Schmitt Trigger input

TABLE 5-2
Address Name

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on
Power-on
Reset

Value on all
other resets

05h

PORTA

RA4/T0CKI

RA3

RA2

RA1

RA0

---x xxxx

---u uuuu

85h

TRISA

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

---1 1111

---1 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'

DS30430C-page 22

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PIC16F8X
5.2

PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' on
any bit in the TRISB register puts the corresponding
output driver in a hi-impedance mode. A '0' on any bit
in the TRISB register puts the contents of the output
latch on the selected pin(s).
Each of the PORTB pins have a weak internal pull-up.
A single control bit can turn on all the pull-ups. This is
done by clearing the RBPU (OPTION_REG<7>) bit.
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The pins value in input mode
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of the pins are
OR’ed together to generate the RB port
change interrupt.

FIGURE 5-3:

BLOCK DIAGRAM OF PINS
RB7:RB4

This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)

Read (or write) PORTB. This will end the mismatch condition.
Clear flag bit RBIF.

A mismatch condition will continue to set the RBIF bit.
Reading PORTB will end the mismatch condition, and
allow the RBIF bit to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression (see AN552 in the
Embedded Control Handbook).
Note 1: For a change on the I/O pin to be
recognized, the pulse width must be at
least TCY (4/fOSC) wide.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.

FIGURE 5-4:

BLOCK DIAGRAM OF PINS
RB3:RB0
VDD

RBPU(1)

VDD
RBPU(1)

weak
P pull-up
Data Latch

Data bus

D

WR Port

Q
I/O
pin(2)

CK

Data bus
WR Port

WR TRIS

WR TRIS

Q

I/O
pin(2)

CK
TRIS Latch
D
Q

TRIS Latch
D

weak
P pull-up
Data Latch
D
Q

TTL
Input
Buffer

CK

TTL
Input
Buffer

CK

RD TRIS
Q

Latch

RD TRIS

Q
RD Port

D

RD Port

D
EN

EN

Set RBIF

RB0/INT
From other
RB7:RB4 pins

Q

Schmitt Trigger
Buffer

D

RD Port

Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).

EN

2: I/O pins have diode protection to VDD and VSS.
RD Port
Note 1: TRISB = '1' enables weak pull-up
(if RBPU = '0' in the OPTION_REG register).
2: I/O pins have diode protection to VDD and VSS.

 1998 Microchip Technology Inc.

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DS30430C-page 23

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Internal software programmable weak pull-up.com  1998 Microchip Technology Inc.agelectronica. Internal software programmable weak pull-up.com PIC16F8X EXAMPLE 5-1: INITIALIZING PORTB CLRF PORTB BSF MOVLW STATUS.com www.com . RB4 bit4 TTL Input/output pin (with interrupt on change). RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). . u = unchanged. Serial programming clock. . . . Legend: TTL = TTL input. RB2 bit2 TTL Input/output pin. RB0/INT bit0 TABLE 5-4 Address Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets uuuu uuuu 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 81h OPTION_ REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown. RB3 bit3 TTL Input/output pin. Serial programming data.agelectronica. Shaded cells are not used by PORTB.agelectronica. . Internal software programmable weak pull-up.agelectronica. . Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). DS30430C-page 24 www. Internal software programmable weak pull-up. Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. . Internal software programmable weak pull-up. Internal software programmable weak pull-up. Internal software programmable weak pull-up. 2: This buffer is a Schmitt Trigger input when used in serial programming mode.www. RP0 0xCF MOVWF TRISB TABLE 5-3 Name . Initialize PORTB by setting output data latches Select Bank 1 Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs PORTB FUNCTIONS Bit Buffer Type I/O Consistency Function TTL/ST(1) Input/output pin or external interrupt input. ST = Schmitt Trigger. . RB1 bit1 TTL Input/output pin. www. .

2 Any instruction which writes. . the data must be valid at the beginning of the instruction cycle (Figure 5-5). The sequence of instructions should be such that the pin voltage stabilizes (load dependent) before the next instruction which causes that file to be read into the CPU is executed.e. 7 . RP0 . If another bit of PORTB is used as a bi-directional I/O pin (i. execute the bit operation and write the result back to the register. care must be exercised if a write followed by a read operation is carried out on the same I/O port. Therefore. Writing to the port register writes the value to the port latch.agelectronica. a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. at higher clock frequencies. a write followed by a read may be problematic.caused RB7 to be latched as the pin value . However. 10pp ppp 11pp ppp BCF TRISB. For example. etc.agelectronica. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.3. EXAMPLE 5-1: . SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched PC PC + 1 MOVWF PORTB MOVF PORTB. 7 . As long as the pin stays in the input mode. 01pp ppp 11pp ppp BCF PORTB. reads the values of the port pins. operates internally as a read followed by a write operation. the previous state of that pin may be read into the CPU rather than the new state. the content of the data latch is unknown.com www.) on an I/O port.pin values to be 00pp ppp. the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin.TPD) RB7:RB0 www. etc.not connected to other circuitry . Example 5-1 shows the effect of two sequential read-modify-write instructions (e. Reading the port register.PORTB<7:6> have external pull-ups and are . whereas for reading.agelectronica. When using read-modify-write instructions (i.com . 6 .e. Note: data setup time = (0. 10pp ppp 10pp ppp . BCF. 6 . DS30430C-page 25 www. 10pp ppp 11pp ppp BSF STATUS.3 I/O Programming Considerations 5. The resulting high output current may damage the chip.) on a port.agelectronica. The 2nd BCF . no problem occurs.1 BI-DIRECTIONAL I/O PORTS 5. PORT latch PORT pins .W Therefore. Note that: where TCY = instruction cycle TPD = propagation delay Port pin sampled here TPD Instruction executed NOP MOVWF PORTB write to PORTB  1998 Microchip Technology Inc. The BCF and BSF instructions. ---------.Initial PORT settings: PORTB<7:4> Inputs . it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. bit0) and it is defined as an input at this time. A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”.com READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT MOVF PORTB.(high).25TCY . for example.. overwriting the previous content. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. the value of the port pins is read..com PIC16F8X 5. read the register into the CPU. FIGURE 5-5: SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle. and this value is then written to the port latch. if bit0 is switched into output mode later on. When in doubt. PORTB<3:0> Outputs .www..W write to PORTB PC + 2 PC + 3 NOP NOP This example shows a write to PORTB followed by a read from PORTB. Otherwise.Note that the user may have expected the . BSF. .g. “wired-and”). BCF.3.--------BCF PORTB. BSF. BCF TRISB. the desired operation is done to this value.

agelectronica.com .com PIC16F8X NOTES: DS30430C-page 26 www.agelectronica.com  1998 Microchip Technology Inc.www.agelectronica.com www.agelectronica. www.

The prescaler assignment is controlled. When the prescaler (Section 6.W PC+3 MOVF TMR0. in software. 1:256) is software selectable. Counter mode is selected by setting the T0CS bit (OPTION_REG<5>).com . The prescaler is not readable or writable. www.agelectronica.com PC+2 MOVF TMR0.agelectronica. The T0IF bit must be cleared in software by the Timer0 Module interrupt service routine before re-enabling this interrupt. The user can work around this by writing an adjusted value to the TMR0 register. T0SE (OPTION_REG<4>). The TMR0 interrupt (Figure 6-4) cannot wake the processor from SLEEP since the timer is shut off during SLEEP. Restrictions on the external clock input are discussed in detail in Section 6. The interrupt can be masked by clearing enable bit T0IE (INTCON<5>).. PS0 Set bit T0IF on Overflow PSA T0CS Note 1: Bits T0CS. If the TMR0 register is written.2.W T0+1 Instruction Executed  1998 Microchip Technology Inc. 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock 6. Clearing bit T0SE selects the rising edge.com www. PS1. the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3).www.W NT0+1 NT0+2 Read TMR0 reads NT0 + 1 T0 Read TMR0 reads NT0 + 2 DS30430C-page 27 www. The Timer0 module timer/counter has the following features: • • • • • • The prescaler is shared between the Timer0 Module and the Watchdog Timer. the Timer0 module (Figure 6-1) will increment every instruction cycle (without prescaler). 1:4. This overflow sets the T0IF bit (INTCON<2>).agelectronica. PS1. . In timer mode..com PIC16F8X 6. The incrementing edge is determined by the T0 source FIGURE 6-1: TMR0 Interrupt TMR0 BLOCK DIAGRAM Data bus FOSC/4 0 PSout 1 1 RA4/T0CKI pin Programmable Prescaler 8 Sync with Internal clocks 0 TMR0 register PSout (2 cycle delay) T0SE 3 PS2.1 Timer mode is selected by clearing the T0CS bit (OPTION_REG<5>).W NT0 Read TMR0 reads NT0 PC+5 PC+6 MOVF TMR0. In this mode TMR0 will increment either on every rising or falling edge of pin RA4/T0CKI. by control bit PSA (OPTION_REG<3>). 2: The prescaler is shared with the Watchdog Timer (Figure 6-6) FIGURE 6-2: TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC Instruction Fetch TMR0 T0 PC PC+1 MOVWF TMR0 MOVF TMR0. PS2. T0SE.3) is assigned to the Timer0 Module. the prescale value (1:2.0 TIMER0 MODULE AND TMR0 REGISTER edge select bit. Clearing bit PSA will assign the prescaler to the Timer0 Module. The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h.agelectronica.W T0+2 NT0 NT0 Write TMR0 executed Read TMR0 reads NT0 Read TMR0 reads NT0 PC+4 MOVF TMR0.. PS0 and PSA are located in the OPTION_REG register.

4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit. The TMR0 register will roll over 3 Tosc cycles later.agelectronica.agelectronica. 3: CLKOUT is available only in RC oscillator mode.com www.W PC+6 MOVF TMR0.www.agelectronica.agelectronica.com PIC16F8X FIGURE 6-3: TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC Instruction Fetch PC PC+1 MOVWF TMR0 MOVF TMR0.W NT0+1 NT0 Write TMR0 executed FIGURE 6-4: PC+4 MOVF TMR0.W T0+1 T0 TMR0 PC+2 MOVF TMR0.25Tcy. www.W PC+3 Instruction Execute PC+5 MOVF TMR0.com . where Tcy = instruction cycle time. DS30430C-page 28 www. 2: Interrupt latency = 3.com  1998 Microchip Technology Inc.W Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 TMR0 INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) TMR0 timer FEh T0IF bit 4 (INTCON<2>) 1 FFh 00h 01h 02h 1 GIE bit (INTCON<7>) Interrupt Latency(2) INSTRUCTION FLOW PC PC Instruction fetched Inst (PC) Instruction executed Inst (PC-1) PC +1 PC +1 Inst (PC+1) Inst (PC) Dummy cycle 0004h 0005h Inst (0004h) Inst (0005h) Dummy cycle Inst (0004h) Note 1: T0IF interrupt flag is sampled here (every Q1).

the external clock input is the same as the prescaler output. MOVWF 1.  1998 Microchip Technology Inc. BSF 1. The synchronization of pin RA4/T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). When a prescaler is used. it is necessary for T0CKI to have a period of at least 4Tosc (plus a small RC delay) divided by the prescaler value.agelectronica. Figure 6-5 shows the delay from the external clock edge to the timer incrementing. Therefore.agelectronica.. Refer to parameters 40. The external clock requirement is due to internal phase clock (TOSC) synchronization. 6. Refer to the electrical specification of the desired device.agelectronica.com . this counter is being referred to as “prescaler” throughout this data sheet.com When assigned to the Timer0 Module. a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. and vice-versa. Note that there is only one prescaler available which is mutually exclusive between the Timer0 Module and the Watchdog Timer.. it is necessary for T0CKI to be high for at least 2Tosc (plus a small RC delay) and low for at least 2Tosc (plus a small RC delay). there is a small delay from the time the external clock edge occurs to the time the Timer0 Module is actually incremented. DS30430C-page 29 www.3 EXTERNAL CLOCK SYNCHRONIZATION Prescaler When no prescaler is used. When assigned to WDT.com www. it must meet certain requirements.. all instructions writing to the Timer0 Module (e.2 TMR0 INCREMENT DELAY When an external clock input is used for TMR0. Thus.1 6.com PIC16F8X 6.g. The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. An 8-bit counter is available as a prescaler for the Timer0 Module.2. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns.agelectronica.x .etc. Since the prescaler output is synchronized with the internal clocks.. The prescaler is not readable or writable. For the external clock to meet the sampling requirement. For simplicity. CLRF 1. or as a postscaler for the Watchdog Timer (Figure 6-6).2 Using TMR0 with External Clock 6. 41 and 42 in the AC Electrical Specifications of the desired device. Also. www. a prescaler assignment for the Timer0 Module means that there is no prescaler for the Watchdog Timer. Therefore.www.2.) will clear the prescaler. the ripple counter must be taken into account. the external clock input is divided by an asynchronous ripple counter type prescaler so that the prescaler output is symmetrical. there is a delay in the actual incrementing of the TMR0 register after synchronization.

(Duration of Q = Tosc).agelectronica. FIGURE 6-6: BLOCK DIAGRAM OF THE TMR0/WDT PRESCALER Data Bus CLKOUT (= Fosc/4) 0 RA4/T0CKI pin M U X 8 1 M U X 0 1 SYNC 2 Cycles TMR0 register T0SE T0CS 0 Watchdog Timer 1 M U X Set bit T0IF on overflow PSA 8-bit Prescaler 8 8 . www.agelectronica. Prescaler output otherwise. DS30430C-page 30 www.agelectronica. PSA.com . A small clock pulse may be missed by sampling. Therefore. 2: External clock if no prescaler selected. Clock/Prescaler Output After Sampling Increment TMR0 (Q4) TMR0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to TMR0 increment is 3Tosc to 7Tosc.com  1998 Microchip Technology Inc.www.to . Clock Input or Prescaler Out (Note 2) (Note 3) Ext.com PIC16F8X FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Ext. PS2:PS0 are bits in the OPTION_REG register. T0SE.1MUX PS2:PS0 PSA WDT Enable bit 1 0 MUX PSA WDT time-out Note: T0CS.agelectronica. 3: The arrows ↑ indicate where sampling occurs. the error in measuring the interval between two edges on TMR0 input = ± 4Tosc max.com www.

Clear TMR0 .com . To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 6-2.Select TMR0.1 SWITCHING PRESCALER ASSIGNMENT EXAMPLE 6-1: The prescaler assignment is fully under software control (i. www. RP0 TMR0 BSF CLRWDT MOVLW MOVWF BCF STATUS. .3. and Prescaler .  1998 Microchip Technology Inc. This sequence must be taken even if the WDT is disabled. RP0 b'xxxx0xxx' MOVWF BCF OPTION_REG STATUS.agelectronica.Clear WDT and .e.. RP0 b'xxxx1xxx' OPTION_REG STATUS.Bank 1 . new . prescaler .Bank 1 . Shaded cells are not associated with Timer0. prescale value .agelectronica. Note: To avoid an unintended device RESET. the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. RP0 EXAMPLE 6-2: .com DS30430C-page 31 www.Bank 0 REGISTERS ASSOCIATED WITH TIMER0 Name Bit 7 Bit 6 Bit 5 GIE EEIE T0IE Bit 4 Bit 3 Value on Power-on Reset Value on all other resets xxxx xxxx uuuu uuuu Bit 2 Bit 1 Bit 0 T0IF INTF RBIF 0000 000x 0000 0000 1111 1111 ---1 1111 01h TMR0 0Bh INTCON Timer0 module’s register 81h OPTION_ REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 INTE RBIE Legend: x = unknown.Bank 0 CHANGING PRESCALER (WDT→TIMER0) CLRWDT BSF MOVLW STATUS.Select new . prescale value ’ and clock source . .com www. u = unchanged. TABLE 6-1 Address CHANGING PRESCALER (TIMER0→WDT) BCF CLRF STATUS.Clears WDT .agelectronica.agelectronica. it can be changed “on the fly” during program execution).= unimplemented read as '0'. RP0 .www.Bank 0 .com PIC16F8X 6.

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PIC16F8X
NOTES:

DS30430C-page 32

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 1998 Microchip Technology Inc.

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PIC16F8X
7.0

DATA EEPROM MEMORY

The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write
this memory. These registers are:



EECON1
EECON2
EEDATA
EEADR

data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The writetime will vary with voltage and temperature as well as
from chip to chip. Please refer to AC specifications for
exact limits.
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
The device programmer can no longer access
this memory.

7.1

EEDATA holds the 8-bit data for read/write, and EEADR
holds the address of the EEPROM location being
accessed. PIC16F8X devices have 64 bytes of data
EEPROM with an address range from 0h to 3Fh.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM

FIGURE 7-1:

EEADR

The EEADR register can address up to a maximum of
256 bytes of data EEPROM. Only the first 64 bytes of
data EEPROM are implemented.
The upper two bits are address decoded. This means
that these two bits must always be '0' to ensure that the
address is in the 64 byte memory space.

EECON1 REGISTER (ADDRESS 88h)

U

U

U

R/W-0

R/W-x

R/W-0

R/S-0

R/S-x

EEIF

WRERR

WREN

WR

RD

bit7

bit0

R
W
S
U

= Readable bit
= Writable bit
= Settable bit
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset

bit 7:5

Unimplemented: Read as '0'

bit 4

EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started

bit 3

WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0 = The write operation completed

bit 2

WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM

bit 1

WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only
be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete

bit 0

RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software).
0 = Does not initiate an EEPROM read

 1998 Microchip Technology Inc.

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DS30430C-page 33

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PIC16F8X
EECON1 and EECON2 Registers

EECON1 is the control register with five low order bits
physically implemented. The upper-three bits are nonexistent and read as '0's.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion of
the read or write operation. The inability to clear the WR
bit in software prevents the accidental, premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
reset or a WDT time-out reset during normal operation.
In these situations, following reset, the user can check
the WRERR bit and rewrite the location. The data and
address will be unchanged in the EEDATA and
EEADR registers.
Interrupt flag bit EEIF is set when write is complete. It
must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the Data EEPROM write sequence.

7.3

Reading the EEPROM Data Memory

To read a data memory location, the user must write
the address to the EEADR register and then set control
bit RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).

EXAMPLE 7-1:
BCF
MOVLW
MOVWF
BSF
BSF
BCF
MOVF

DATA EEPROM READ

STATUS, RP0
CONFIG_ADDR
EEADR
STATUS, RP0
EECON1, RD
STATUS, RP0
EEDATA, W

DS30430C-page 34

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;
;
;
;
;
;
;

Bank 0

7.4

Writing to the EEPROM Data Memory

To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.

EXAMPLE 7-1:

Required
Sequence

7.2

DATA EEPROM WRITE

BSF
BCF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF

STATUS, RP0
INTCON, GIE
EECON1, WREN
55h
EECON2
AAh
EECON2
EECON1,WR

BSF

INTCON, GIE

;
;
;
;
;
;
;
;
;
;

Bank 1
Disable INTs.
Enable Write
Write 55h
Write AAh
Set WR bit
begin write
Enable INTs.

The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.

Address to read
Bank 1
EE Read
Bank 0
W = EEDATA

 1998 Microchip Technology Inc.

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good programming practice may dictate that the value written to the Data EEPROM should be verified (Example 7-1) to the desired value to be written. there are two code protection bits (Section 8. STATUS.com . power glitch. .agelectronica. Bank 0 For ROM devices. value written STATUS. but reads back as a '0' (due to leakage off the bit).6 BCF : : MOVF BSF Bank 0 Any code can go here 7. Generally the EEPROM write failure will be a bit which was written as a '1'. BTFSS STATUS.agelectronica.5 Write Verify GOTO : : Depending on the application. One for the ROM program memory and one for the Data EEPROM memory.---- — — — EEPROM control register 2 EEIF WRERR WREN WR RD Legend: x = unknown.com www. WREN is cleared. NO. On power-up.  1998 Microchip Technology Inc. . EEDATA. The Total Endurance disk will help determine your comfort level. RP0 . WRITE VERIFY STATUS.agelectronica. . Read the .= unimplemented read as '0'. read (in EEDATA) the same? . Write error . EXAMPLE 7-1: WRITE_ERR REGISTERS/BITS ASSOCIATED WITH DATA EEPROM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets 08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu 09h EEADR EEPROM address register xxxx xxxx uuuu uuuu 88h EECON1 ---0 x000 ---0 q000 89h EECON2 ---. Is difference 0? TABLE 7-1 Address Data EEPROM Operation during Code Protect When the device is code protected. YES. Is the value written (in W reg) and . RP0 . various mechanisms have been built in. RD . . BCF . . www. W . To protect against spurious EEPROM writes.www. This should be used in applications where an EEPROM bit will be stressed near the specification limit. 7.---- ---. the Power-up Timer (72 ms duration) prevents EEPROM write. u = unchanged.1).7 Must be in Bank 0 Bank 1 EECON1. RP0 .com DS30430C-page 35 www. READ BSF Protection Against Spurious Writes The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out. W . q = value depends upon condition. YES. the CPU is able to read and write unscrambled data to the Data EEPROM. Z .com PIC16F8X 7.agelectronica. Also. SUBWF EEDATA. Good write . Continue program There are conditions when the device may not want to write to the data EEPROM memory. or software malfunction. Shaded cells are not used by Data EEPROM.

www.com www.agelectronica. www.agelectronica.com .com  1998 Microchip Technology Inc.agelectronica.agelectronica.com PIC16F8X NOTES: DS30430C-page 36 www.

minimize cost through elimination of external components. which provides a fixed delay of 72 ms (nominal) on power-up only.com www. Several oscillator options are provided to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. intended to keep the chip in reset until the crystal oscillator is stable.agelectronica.  1998 Microchip Technology Inc.Power-on Reset (POR) .agelectronica. A set of configuration bits are used to select the various options. These bits are mapped in program memory location 2007h. www. This space can only be accessed during programming. provide power saving operating modes and offer code protection. With these two timers on-chip. This design keeps the device in reset while the power supply stabilizes.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications.com PIC16F8X 8. SLEEP mode offers a very low current power-down mode. The PIC16F8X has a Watchdog Timer which can be shut off only through configuration bits. One is the Oscillator Start-up Timer (OST).agelectronica. Address 2007h is beyond the user program memory space and it belongs to the special test/configuration memory space (2000h . There are two timers that offer necessary delays on power-up.agelectronica. refer to PIC16C84 EEPROM Memory Programming Specification (DS30189). most applications need no external reset circuitry. These features are: • OSC Selection • Reset .Power-up Timer (PWRT) .com . The other is the Power-up Timer (PWRT). The PIC16F8X has a host of such features intended to maximize system reliability. The user can wake-up from SLEEP through external reset. To find out how to program the PIC16C84.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. It runs off its own RC oscillator for added reliability. Watchdog Timer time-out or through an interrupt.3FFFh).www.Oscillator Start-up Timer (OST) • Interrupts • Watchdog Timer (WDT) • SLEEP • Code protection • ID locations • In-circuit serial programming 8.com DS30430C-page 37 www.

agelectronica.n = Value at POR reset u = unchanged bit 13:8 CP: Program Memory Code Protection bit 1 = Code protection off 0 = Program memory is code protected bit 7 DP: Data Memory Code Protection bit 1 = Code protection off 0 = Data memory is code protected bit 6:4 CP: Program Memory Code Protection bit 1 = Code protection off 0 = Program memory is code protected bit 3 PWRTE: Power-up Timer Enable bit 1 = Power-up timer is disabled 0 = Power-up timer is enabled bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1:0 FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator FIGURE 8-2: CONFIGURATION WORD .PIC16CR83 AND PIC16CR84 R-u R-u R-u R-u R-u R-u R/P-u R-u R-u R-u CP bit13 CP CP CP CP CP DP CP CP CP R-u R-u R-u R-u PWRTE WDTE FOSC1 FOSC0 bit0 R = Readable bit P = Programmable bit .www. www.agelectronica.PIC16F83 AND PIC16F84 R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u R/P-u CP CP CP CP CP CP CP CP CP bit13 R/P-u CP R/P-u R/P-u R/P-u R/P-u PWRTE WDTE FOSC1 FOSC0 bit0 R = Readable bit P = Programmable bit .com .n = Value at POR reset u = unchanged bit 13:4 CP: Code Protection bit 1 = Code protection off 0 = All memory is code protected bit 3 PWRTE: Power-up Timer Enable bit 1 = Power-up timer is disabled 0 = Power-up timer is enabled bit 2 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1:0 FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator DS30430C-page 38 www.agelectronica.com PIC16F8X FIGURE 8-1: CONFIGURATION WORD .agelectronica.com  1998 Microchip Technology Inc.com www.

These values are for design guidance only. XT OR LP OSC CONFIGURATION) C1(1) OSC1 XTAL RF(3) OSC2 C2(1) Note1: 2: 3: To internal logic PIC16FXX See Table 8-1 for recommended values of C1 and C2.2.5% ± 0.2 Oscillator Configurations 8.100 pF 15 .00MT Murata Erie CSA10.33 pF 15 .100 pF 15 . EXTERNAL CLOCK INPUT OPERATION (HS.5V.33 pF 15 . RF varies with the crystal chosen.33 pF XT HS Note : Higher capacitance increases the stability of oscillator but also increases the start-up time.5% None of the resonators had built-in capacitors.33 pF 15 .150 pF 15 . Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications.1 OSCILLATOR TYPES TABLE 8-1 The PIC16F8X can be operated in four different oscillator modes. Since each resonator has its own characteristics.00 KC-P STD XTL 200. XT OR LP OSC CONFIGURATION) OSC1 Clock from ext.33 pF 15 .768K-A Epson C-2 100.33 pF 15 .33 pF Recommended values of C1 and C2 are identical to the ranges tested table.33 pF 68 . The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor 8. Crystals Tested: 32.www.com Panasonic EFO-A455K04B Murata Erie CSA2.5% ± 0. When in XT. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. C1 = C2 ≈ 30 pF is recommended.com PIC16F8X 8. www.0 MHz 4.100 pF 47 .0 MHz 8.33 pF 15 . LP or HS modes.com www. LP or HS modes a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 8-3).0 MHz 8.768 kHz 100 kHz 200 kHz 1.agelectronica.33 pF 15 . OSC1/C1 OSC2/C2 47 . TABLE 8-2 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR SLEEP RS(2) FIGURE 8-4: 455 kHz 2. the user should consult the crystal manufacturer for appropriate values of external components.0 MHz Mode Freq OSC1/C1 OSC2/C2 LP 32 kHz 200 kHz 100 kHz 2 MHz 4 MHz 4 MHz 10 MHz 68 .agelectronica. A series resistor (RS) may be required for AT strip cut crystals. Higher capacitance increases the stability of the oscillator but also increases the start-up time.150 pF 15 . For VDD > 4. Resonators Tested: FIGURE 8-3: CRYSTAL/CERAMIC RESONATOR OPERATION (HS.100 pF 15 . These values are for design guidance only.0 MHz 4.33 pF 15 .33 pF 15 .agelectronica.2.33 pF 100 .33 pF 15 .33 pF 15 .3% ± 0.000 KHz ECS ECS-10-13-2 ECS ECS-20-S-2 ECS ECS-40-S-4 ECS ECS-100-S-4 ± 20 PPM ± 20 PPM ± 20 PPM ± 50 PPM ± 50 PPM ± 50 PPM ± 50 PPM DS30430C-page 39 www. the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 8-4).com .0 MHz 2.00MG Murata Erie CSA8.0 MHz HS Note : CRYSTAL OSCILLATOR / CERAMIC RESONATORS In XT.33 pF 100 .0 MHz 4. Since each crystal has its own characteristics. the user should consult the resonator manufacturer for the appropriate values of external components.0 MHz 10. The PIC16F8X oscillator design requires the use of a parallel cut crystal.00MTZ ± 0.0 MHz 10.5% ± 0.agelectronica.0 MHz 10.0 MHz Epson C-001R32.00MG Murata Erie CSA4. system PIC16FXX Open OSC2  1998 Microchip Technology Inc.33 pF 15 .33 pF 15 .2 CAPACITOR SELECTION FOR CERAMIC RESONATORS Ranges Tested: Mode Freq XT 455 kHz 2.

and the operating temperature. This could be used for external oscillator designs.4 Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance has a greater affect on RC frequency). See the electrical specification section for RC frequency variation from part to part due to normal process variation. The user needs to take into account variation due to tolerance of the external R and C components. the difference in lead frame capacitance between package types also affects the oscillation frequency.agelectronica. See the electrical specification section for variation of oscillator frequency due to VDD for given Rext/Cext values as well as frequency variation due to operating temperature. Furthermore.2. 1 MΩ). Thus.2. and one with parallel resonance. the oscillator becomes sensitive to noise. the oscillator operation may become unstable. and can be used for test purposes or to synchronize other logic (see Figure 3-2 for waveform).com .www. The 10 kΩ potentiometer biases the 74AS04 in the linear region. or stop completely.agelectronica. one with series resonance. Although the oscillator will operate with no external capacitor (Cext = 0 pF).agelectronica. Figure 8-5 shows a parallel resonant oscillator circuit. such as PCB trace capacitance or package lead frame capacitance. The circuit is designed to use the fundamental frequency of the crystal. In addition to this. Two types of crystal oscillator circuits are available. With little or no external capacitance. do not drive the OSC1 pin with an external clock or you may damage the device. we recommend keeping Rext between 5 kΩ and 100 kΩ. For Rext values below 4 kΩ.7k CLKIN 74AS04 10k XTAL 10k 20 pF RC OSCILLATOR For timing insensitive applications the RC device option offers additional cost savings. Figure 8-7 shows how an R/C combination is connected to the PIC16F8X.. The oscillator frequency. The 4.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT 8.g. the oscillation frequency can vary dramatically due to changes in external capacitances. is available on the OSC2/CLKOUT pin.com When the device oscillator is in RC mode. Prepackaged oscillators provide a wide operating range and better stability. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. www. FIGURE 8-7: RC OSCILLATOR MODE VDD FIGURE 8-6: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT 330 kΩ 330 kΩ 74AS04 74AS04 To Other Devices Rext OSC1 Cext PIC16FXX 74AS04 CLKIN Internal clock PIC16FXX VSS Fosc/4 Recommended values: 0. FIGURE 8-5: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT +5V To Other Devices PIC16FXX 10k 74AS04 4. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region.  1998 Microchip Technology Inc.com PIC16F8X 8.com www. The inverter performs a 180-degree phase shift. The RC oscillator frequency is a function of the supply voltage. This circuit is also designed to use the fundamental frequency of the crystal. 20 pF Figure 8-6 shows a series resonant oscillator circuit.7 kΩ resistor provides negative feedback for stability. For very high Rext values (e. the oscillator frequency will vary from unit to unit due to normal process parameter variation. capacitor (Cext) values.1 µF OSC2/CLKOUT 5 kΩ ≤ Rext ≤ 100 kΩ Cext > 20pF XTAL Note: DS30430C-page 40 www. A well-designed crystal oscillator will provide good performance with TTL gates. the resistor (Rext) values. humidity and leakage.agelectronica. especially for low Cext values. divided by 4. we recommend using values above 20 pF for noise and stability reasons.

3 Reset The PIC16F8X differentiates between various kinds of reset: • • • • • Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Figure 8-8 shows a simplified block diagram of the on-chip reset circuit. since this reset is viewed as the resumption of normal operation.www. Table 8-3 gives a description of reset conditions for the program counter (PC) and the STATUS register.agelectronica. Table 8-4 gives a full description of reset states for all registers. The TO and PD bits are set or cleared differently in different reset situations (Section 8.com . MCLR or WDT reset during normal operation and on MCLR reset during SLEEP.com PIC16F8X 8.com www.agelectronica.agelectronica. their status is unknown on a POR reset and unchanged in any other reset.  1998 Microchip Technology Inc. These bits are used in software to determine the nature of the reset. The MCLR reset path has a noise filter to ignore small pulses. www. FIGURE 8-8: Some registers are not affected in any reset condition. They are not affected by a WDT reset during SLEEP.agelectronica. The electrical specifications state the pulse width requirements for the MCLR pin. Most other registers are reset to a “reset state” on POR. SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR WDT Module SLEEP WDT Time_Out Reset VDD rise detect Power_on_Reset S 10-bit Ripple counter R VDD OST/PWRT OST Chip_Reset Q OSC1/ CLKIN PWRT On-chip RC OSC(1) 10-bit Ripple counter Enable PWRT Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.7).com See Table 8-5 Enable OST DS30430C-page 41 www.

---- ---. DS30430C-page 42 www. x = unknown.---- TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h 0000h 0000h STATUS 03h 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu PORTA 05h ---x xxxx ---u uuuu ---u uuuu PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu EEDATA 08h xxxx xxxx uuuu uuuu uuuu uuuu EEADR 09h xxxx xxxx uuuu uuuu uuuu uuuu PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh 0000 000x 0000 000u uuuu uuuu(1) INDF 80h ---.com www.---- OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu PCL 82h 0000h 0000h PC + 1 STATUS 83h 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 84h xxxx xxxx uuuu uuuu uuuu uuuu TRISA 85h ---1 1111 ---1 1111 ---u uuuu TRISB 86h 1111 1111 1111 1111 uuuu uuuu EECON1 88h ---0 x000 ---0 q000 ---0 uuuu EECON2 89h ---.---- ---.agelectronica. Note 1: One or more bits in INTCON will be affected (to cause wake-up). x = unknown. the PC is loaded with the interrupt vector (0004h).com PIC16F8X TABLE 8-3 RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER Program Counter Condition STATUS Register Power-on Reset 000h MCLR Reset during normal operation 000h 000u uuuu MCLR Reset during SLEEP 000h 0001 0uuu WDT Reset (during normal operation) 000h 0000 1uuu WDT Wake-up PC + 1 uuu0 0uuu Interrupt wake-up from SLEEP PC + 1 (1) uuu1 0uuu 0001 1xxx Legend: u = unchanged. 2: When the wake-up is due to an interrupt and the GIE bit is set. .---- ---.agelectronica.---- PC + 1(2) Legend: u = unchanged. Note 1: When the wake-up is due to an interrupt and the GIE bit is set.agelectronica.com  1998 Microchip Technology Inc.com .agelectronica.---- ---.= unimplemented bit read as '0'.---- ---.---- PCLATH 8Ah ---0 0000 ---0 0000 ---u uuuu INTCON 8Bh 0000 000x 0000 000u uuuu uuuu(1) ---. the PC is loaded with the interrupt vector (0004h).www. 3: Table 8-3 lists the reset value for each specific condition. www. q = value depends on condition. TABLE 8-4 Register W RESET CONDITIONS FOR ALL REGISTERS Address Power-on Reset MCLR Reset during: – normal operation – SLEEP WDT Reset during normal operation Wake-up from SLEEP: – through interrupt – through WDT Time-out — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h ---.

8. device operating parameters (voltage.agelectronica. For additional information. The diode D helps discharge the capacitor quickly when VDD powers down. 3: R1 = 100Ω to 1 kΩ will limit any current flowing into MCLR from external capacitor C in the event of an MCLR pin breakdown due to ESD or EOS.6 Oscillator Start-up Timer (OST) The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle delay (from OSC1 input) after the PWRT delay ends (Figure 8-10.1. www. To take advantage of the POR.) must be meet to ensure operation.com DS30430C-page 43 www. See DC parameters for details. This ensures the crystal oscillator or resonator has started and stabilized.com PIC16F8X 8. the device must be held in reset until the operating conditions are met.agelectronica. LP and HS modes and only on Power-on Reset or wake-up from SLEEP. The PWRT delay allows the VDD to rise to an acceptable level (Possible exception shown in Figure 8-13). A minimum rise time for VDD must be met for this to operate properly..2V .www. If these conditions are not met. The chip is kept in reset as long as the PWRT is active. The OST time-out (TOST) is invoked only for XT. Figure 8-11. When the device starts normal operation (exits the reset condition). frequency.. See either Figure 8-1 or Figure 8-2 for the operation of the PWRTE bit for a particular device. can enable/disable the PWRT. Figure 8-11.5 Power-up Timer (PWRT) The Power-up Timer (PWRT) provides a fixed 72 ms nominal time-out (TPWRT) from POR (Figure 8-10. just tie the MCLR pin directly (or through a resistor) to VDD.2V (max leakage current spec on MCLR pin is 5 µA).agelectronica. Figure 8-12 and Figure 8-13). 2: R < 40 kΩ is recommended to make sure that voltage drop across R does not exceed 0. 8.4 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1. This will eliminate external RC components usually needed to create Power-on Reset. refer to Application Note AN607.7V). The Power-up Timer operates on an internal RC oscillator. "Power-up Trouble Shooting. A configuration bit. When VDD rises very slowly. Figure 8-12 and Figure 8-13). temperature. and process variation. See Electrical Specifications for details. In this case (Figure 8-13).com . FIGURE 8-9: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) VDD VDD D R R1 MCLR C PIC16FXX Note 1: External Power-on Reset circuit is required only if VDD power-up rate is too slow. it is possible that the TPWRT time-out and TOST time-out will expire before VDD has reached its final value. temperature.com www." The POR circuit does not produce an internal reset when VDD declines.agelectronica. . PWRTE.  1998 Microchip Technology Inc. an external power-on reset circuit may be necessary (Figure 8-9). The power-up time delay TPWRT will vary from chip to chip due to VDD. A larger voltage drop will degrade VIH level on the MCLR pin.

com PIC16F8X FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30430C-page 44 www.agelectronica.com  1998 Microchip Technology Inc.www.com www. www.com .agelectronica.agelectronica.agelectronica.

com DS30430C-page 45 www. In this example. and only if. www. it is possible that the TPWRT time-out and TOST time-out will expire before VDD has reached its final value. the chip will reset properly if.agelectronica.com .com PIC16F8X FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET When VDD rises very slowly. V1 ≥ VDD min.agelectronica.  1998 Microchip Technology Inc.com www.agelectronica.agelectronica.www.

This is useful for testing purposes or to synchronize more than one PIC16F8X device when operating in parallel. in RC mode with the PWRT disabled. To reset a PIC16F8X device when a brown-out occurs. Then bringing MCLR high. and then recovers. Transistor Q1 turns off when VDD is below a certain level such that: VDD • DS30430C-page 46 MCLR R1 R1 + R2 = 0.agelectronica.7V  1998 Microchip Technology Inc. Then the OST is activated. PD is set on POR WDT Reset (during normal operation) WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP 40k www.com PIC16F8X This circuit will activate reset when VDD goes below (Vz + 0.com www.8 STATUS BITS AND THEIR SIGNIFICANCE Condition Power-on Reset Illegal.agelectronica. For example. TABLE 8-6 Reset on Brown-Out FIGURE 8-14: BROWN-OUT PROTECTION CIRCUIT 1 TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration 8.www.7 Time-out Sequence and Power-down Status Bits (TO/PD) On power-up (Figure 8-10. while Table 8-4 lists the reset conditions for all the registers.agelectronica. execution will begin immediately (Figure 8-10). TO PD 1 0 x 0 0 1 1 1 x 0 1 0 1 0 A brown-out is a condition where device power (VDD) dips below its minimum value. TABLE 8-5 XT. The total time-out will vary based on oscillator configuration and PWRTE configuration bit status. VDD VDD 33k 10k Since the time-outs occur from the POR reset pulse. the time-outs will expire. FIGURE 8-15: BROWN-OUT PROTECTION CIRCUIT 2 VDD VDD R1 Q1 MCLR R2 40k PIC16F8X This brown-out circuit is less expensive. if MCLR is kept low long enough. LP RC Power-up PWRT Enabled PWRT Disabled Wake-up from SLEEP 72 ms + 1024TOSC 72 ms 1024TOSC 1024TOSC — — Table 8-6 shows the significance of the TO and PD bits. TO is set on POR Illegal.agelectronica. although less accurate. Figure 8-12 and Figure 8-13) the time-out sequence is as follows: First PWRT time-out is invoked after a POR has expired. Figure 8-11. The device should be reset in the event of a brown-out. HS.7V) where Vz = Zener voltage. Table 8-3 lists the reset conditions for some special registers. as shown in Figure 8-14 and Figure 8-15.com . www. but not to zero. external brown-out protection circuits may be built.com PIC16F8X 8. there will be no time-out at all.

9 Interrupts The PIC16F8X has 4 sources of interrupt: • • • • External interrupt RB0/INT pin TMR0 overflow interrupt PORTB change interrupts (pins RB7:RB4) Data EEPROM write complete interrupt The interrupt control register (INTCON) records individual interrupt requests in flag bits. RETFIE.com PIC16F8X 8. The exact latency depends when the interrupt event occurs (Figure 8-17). The latency is the same for both one and two cycle instructions. Bit GIE is cleared on reset. For external interrupt events. www. The RB0/INT pin interrupt.agelectronica. the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register.agelectronica. Note 1: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. When an interrupt is responded to. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid infinite interrupt requests.agelectronica. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. which re-enable interrupts. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits.com .www.com DS30430C-page 47 www. such as the RB0/INT pin or PORTB change interrupt. the interrupt latency will be three to four instruction cycles.agelectronica. The “return from interrupt” instruction. the GIE bit is cleared to disable any further interrupt. GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. It also contains the individual and global interrupt enable bits. exits interrupt routine as well as sets the GIE bit.com www. The global interrupt enable bit. FIGURE 8-16: INTERRUPT LOGIC T0IF T0IE INTF INTE Wake-up (If in SLEEP mode) Interrupt to CPU RBIF RBIE EEIF EEIE GIE  1998 Microchip Technology Inc. the return address is pushed onto the stack and the PC is loaded with 0004h.

The INT interrupt can wake the processor from SLEEP (Section 8.2). if INTEDG bit is clear. refer to AC specs. www. 8. When a valid edge appears on the RB0/INT pin. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.agelectronica. the INTF bit (INTCON<1>) is set. or falling.agelectronica. 2: Interrupt latency = 3-4Tcy where Tcy = instruction cycle time. The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>) (Section 6.com  1998 Microchip Technology Inc. The status of the GIE bit decides whether the processor branches to the interrupt vector following wake-up. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.1 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered: either rising if INTEDG bit (OPTION_REG<6>) is set.0).agelectronica. the pulse width must be at least TCY wide.2 8. This interrupt can be disabled by clearing control bit INTE (INTCON<4>).9.com . 3: CLKOUT is available only in RC oscillator mode. 8. TMR0 INTERRUPT An overflow (FFh → 00h) in TMR0 will set flag bit T0IF (INTCON<2>).com PIC16F8X FIGURE 8-17: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 4 INT pin 1 1 INTF flag (INTCON<1>) Interrupt Latency 2 5 GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction fetched Inst (PC) Instruction executed Inst (PC-1) PC+1 Inst (PC+1) Inst (PC) 0004h PC+1 — Dummy Cycle 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) Note 1: INTF flag is sampled here (every Q1). Note 1: For a change on the I/O pin to be recognized.3 PORT RB INTERRUPT An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>).12) only if the INTE bit was set prior to going into SLEEP. 4: For minimum width of INT pulse. The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<3>) (Section 5.agelectronica.9.9. Flag bit INTF must be cleared in software via the interrupt service routine before re-enabling this interrupt.com www.www. DS30430C-page 48 www.

Executes the Interrupt Service Routine code. . . W_TEMP and STATUS_TEMP are the temporary storage locations for the W and STATUS registers values. . only the return PC value is saved on the stack. Stores the STATUS register in STATUS_TEMP. . www. .. This is implemented in software. Typically. W MOVWF STATUS SWAPF SWAPF W_TEMP. EXAMPLE 8-1: PUSH ISR POP a) b) c) d) e) Stores the W register.com PIC16F8X 8.10 Context Saving During Interrupts During an interrupt. . The User defined registers. Copy W to TEMP register. Swap status to be saved into W Save status to STATUS_TEMP register Interrupt Service Routine should configure Bank as required Swap nibbles in STATUS_TEMP register and place result into W Move W into STATUS register (sets bank to original state) Swap nibbles in W_TEMP and place result in W_TEMP Swap nibbles in W_TEMP and place result into W DS30430C-page 49 www. F W_TEMP. W W_TEMP STATUS.www. Example 8-1 stores and restores the STATUS and W register’s values. W register and STATUS register). Restores the W register. .agelectronica. Restores the STATUS (and bank select bit) register.com . .com Example 8-1 does the following: . : .agelectronica. .com www. W STATUS_TEMP  1998 Microchip Technology Inc.g.agelectronica. SAVING STATUS AND W REGISTERS IN RAM MOVWF SWAPF MOVWF : : : : SWAPF STATUS_TEMP. . users wish to save key register values during an interrupt (e.agelectronica.

2 WDT PROGRAMMING CONSIDERATIONS It should also be taken into account that under worst case conditions (VDD = Min.com www. WDT prescaler) it may take several seconds before a WDT time-out occurs. DS30430C-page 50 www..agelectronica. bits (2) (2) (2) (2) PWRTE(1) WDTE FOSC1 FOSC0 (2) 81h OPTION_ REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 Value on all other resets 1111 1111 Legend: x = unknown. time-out periods up to 2. The WDT can be permanently disabled by programming configuration bit WDTE as a '0' (Section 8. The TO bit in the STATUS register will be cleared upon a WDT time-out.agelectronica. Shaded cells are not used by the WDT.agelectronica.13 for operation of the Code and Data protection bits.www.11. FIGURE 8-18: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 6-6) 0 WDT Timer • 1 M U X Postscaler 8 8 . Temperature = Max. a WDT Wake-up causes the device to wake-up and continue with normal operation. by execution of a SLEEP instruction.to -1 MUX PS2:PS0 • To TMR0 (Figure 6-6) PSA WDT Enable Bit 1 0 MUX PSA WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION_REG register.11. 8.11 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. The time-out periods vary with temperature. If the device is in SLEEP mode. Thus. (with no prescaler). During normal operation a WDT time-out generates a device RESET.com PIC16F8X 8. max. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. VDD and process variations from part to part (see DC specs). a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION_REG register. for example. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped. If longer time-out periods are desired.1). 8.com .3 seconds can be realized.agelectronica. 2: See Figure 8-1. Note 1: See Figure 8-1 and Figure 8-2 for operation of the PWRTE bit.. TABLE 8-7 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset 2007h Config.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms.com  1998 Microchip Technology Inc. Figure 8-2 and Section 8. www. The CLRWDT and SLEEP instructions clear the WDT and the postscaler (if assigned to the WDT) and prevent it from timing out and generating a device RESET condition.

12.com . FIGURE 8-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction fetched Inst(PC) = SLEEP Instruction executed Inst(PC . the next instruction (PC + 1) is pre-fetched. the user should have a NOP after the SLEEP instruction.2 A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). External reset input on MCLR pin.1 SLEEP The Power-down mode is entered by executing the SLEEP instruction. CLKOUT is not available in these osc modes. 3. HS or LP oscillator mode assumed.12 Power-down Mode (SLEEP) 8. For the lowest current consumption in SLEEP mode. 2.12. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). the corresponding interrupt enable bit must be set (enabled).1) Note 1: 2: 3: 4: PC+1 PC+2 PC+2 Inst(PC + 1) Inst(PC + 2) SLEEP Inst(PC + 1) PC + 2 Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) XT. In cases where the execution of the instruction following SLEEP is not desirable. the device continues execution at the instruction after the SLEEP instruction. The T0CKI input should also be at VDD or VSS. Wake-up occurs regardless of the state of the GIE bit. In this case after wake. If the GIE bit is clear (disabled). GIE = '1' assumed. the PD bit (STATUS<3>) is cleared. The two latter events are considered a continuation of program execution. WDT Wake-up (if WDT was enabled). The TO and PD bits can be used to determine the cause of a device reset. or data EEPROM write complete. execution will continue in-line. the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). The MCLR pin must be at a logic high level (VIHMC). If enabled. and disable external clocks. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high. While the SLEEP instruction is being executed. place all I/O pins at either at VDD or VSS.agelectronica. If the GIE bit is set (enabled).com DS30430C-page 51 www. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. is cleared when SLEEP is invoked.agelectronica. Peripherals cannot generate interrupts during SLEEP.com PIC16F8X 8.agelectronica. the processor jumps to the interrupt routine. RB port change.  1998 Microchip Technology Inc. The contribution from on-chip pull-ups on PORTB should be considered. with no external circuitry drawing current from the I/O pins. the Watchdog Timer is cleared (but keeps running). or hi-impedance).www. Interrupt from RB0/INT pin. TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of the following events: 1. For the device to wake-up through an interrupt event. 8. which is set on power-up. the TO bit (STATUS<4>) is set. The first event (MCLR reset) will cause a device reset.agelectronica. If GIE = '0'. www. but shown here for timing reference. It should be noted that a RESET generated by a WDT time-out does not drive the MCLR pin low. since no on-chip Q clocks are present.up. low. The PD bit. and the oscillator driver is turned off.com www.

ID Locations Four memory locations (2000h . The device is placed into a program/verify mode by holding the RB6 and RB7 pins low. a CLRWDT instruction should be executed before a SLEEP instruction. To ensure that the WDT is cleared. • If the interrupt occurs during or after the execution of a SLEEP instruction. This is simply done with two lines for clock and data. while raising the MCLR pin from VIL to VIHH (see programming specification). the program counter (PC) points to location 00h. the SLEEP instruction was executed as a NOP.2003h) are designated as ID locations to store checksum or other code identification numbers. Therefore. To determine whether a SLEEP instruction executed. ground. RB6 becomes the programming clock and RB7 becomes the programming data.com . Customers can manufacture boards with unprogrammed devices. these values are submitted along with the ROM code. using load or read-type instructions.agelectronica. VDD To Normal Connections For ROM devices.14 Microchip does not recommend code protecting widowed devices. to place the device into programming/verify mode. and the programming voltage. www. the WDT and WDT postscaler will not be cleared. 8.agelectronica. Both RB6 and RB7 are Schmitt Trigger inputs in this mode. the WDT and WDT postscaler will be cleared. allowing the most recent firmware or custom firmware to be programmed. A 6-bit command is then supplied to the device. the SLEEP instruction will complete as a NOP.agelectronica. the device will immediately wake up from sleep. test the PD bit. These locations are not accessible during normal execution but are readable and writable only during program/verify. 14-bits of program data is then supplied to or from the device. For complete details of serial programming.com www. Note: 8. one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction. the on-chip program memory can be read out for verification purposes. After reset. but only the Data EEPROM memory may be programmed. DS30430C-page 52 www.15 In-Circuit Serial Programming PIC16F8X microcontrollers can be serially programmed while in the end application circuit. and three other lines for power.com  1998 Microchip Technology Inc. both the program memory and Data EEPROM memory may be read. Only the 4 least significant bits of ID location are usable. If the PD bit is set.com PIC16F8X 8.12. the TO bit will not be set and PD bits will not be cleared.3 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set. the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction. The SLEEP instruction will be completely executed before the wake-up.agelectronica. Therefore. 8.13 Program Verification/Code Protection If the code protection bit(s) have not been programmed. FIGURE 8-20: TYPICAL IN-SYSTEM SERIAL PROGRAMMING CONNECTION External Connector Signals To Normal Connections PIC16FXX +5V VDD 0V VSS VPP MCLR/VPP CLK RB6 Data I/O RB7 For ROM devices.www. and then program the microcontroller just before shipping the product. please refer to the PIC16CXX Programming Specifications (Literature #DS30189). it may be possible for flag bits to become set before the SLEEP instruction completes.

for an oscillator frequency of 4 MHz. and literal and control operations. the normal instruction execution time is 1 µs. For literal and control operations. bit-oriented. All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. Figure 9-1 shows the general formats that the instructions can have. It is the recommended form of use for compatibility with all Microchip software tools. unless a conditional test is true or the program counter is changed as a result of an instruction.com www. One instruction cycle consists of four oscillator periods. do not use the OPTION and TRIS instructions. d = 1: store result in file register f.agelectronica. Table 9-2 lists the instructions recognized by the MPASM assembler. The file register designator specifies which file register is to be used by the instruction. The PIC16CXX instruction set summary in Table 9-2 lists byte-oriented. If 'd' is one. www. For bit-oriented instructions.com .com PIC16F8X 9. For byte-oriented instructions. the result is placed in the W register. Thus. The destination designator specifies where the result of the operation is to be placed.agelectronica. FIGURE 9-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 8 7 OPCODE Contents 0 k (literal) k = 8-bit immediate value Assigned to Register bit field In the set of User defined term (font is courier) CALL and GOTO instructions only 13 11 OPCODE 10 0 k (literal) k = 11-bit immediate value  1998 Microchip Technology Inc.agelectronica. If a conditional test is true or the program counter is changed as a result of an instruction.0 INSTRUCTION SET SUMMARY Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. Table 9-1 shows the opcode field descriptions. 'f' represents a file register designator and 'd' represents a destination designator. 'k' represents an eight or eleven bit constant or literal value. Default is d = 1 d label TOS PC Label name Top of Stack Program Counter PCLATH Program Counter High Latch Global Interrupt Enable bit Watchdog Timer/Counter Time-out bit Power-down bit Destination either the W register or the specified register file location Options GIE WDT TO PD dest [ ] ( ) → <> ∈ italics The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations All instructions are executed within one single instruction cycle. the execution takes two instruction cycles with the second cycle executed as a NOP. constant data or label x Don't care location (= 0 or 1) The assembler will generate code with x = 0. the instruction execution time is 2 µs. If 'd' is zero. Destination select.www. TABLE 9-1 Field OPCODE FIELD DESCRIPTIONS Description f W Register file address (0x00 to 0x7F) Working register (accumulator) b k Bit address within an 8-bit file register Literal field. 'b' represents a bit field designator which selects the number of the bit affected by the operation.agelectronica. while 'f' represents the number of the file in which the bit is located. In this case. the result is placed in the file register specified in the instruction. d = 0: store result in W.com DS30430C-page 53 www. Note: To maintain upward compatibility with future PIC16CXX products.

agelectronica.Z Z Note 1: When an I/O register is modified as a function of itself ( e.com  1998 Microchip Technology Inc.2 2 1..DC. if the data latch is '1' for a pin configured as input and is driven low by an external device.agelectronica. b f.2 1.Z Z 1. d f. b f. 1). d f. b Bit Clear f Bit Set f Bit Test f.com PIC16F8X TABLE 9-2 PIC16FXX INSTRUCTION SET Mnemonic.3 1. 3: If Program Counter (PC) is modified or a conditional test is true. d f. MOVF PORTB. Skip if Clear Bit Test f.Z Z Z Z Z Z Z Z Z C C C.2 1.agelectronica. d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f. d f.g. Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f. d f. d f.agelectronica. where applicable. d f. www. Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C. the prescaler will be cleared if assigned to the Timer0 Module.com www. Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 1.2 1. For example. Skip if 0 Increment f Increment f.DC.DC.2 1.PD C.2. 2: If this instruction is executed on the TMR0 register (and. the value used will be that value present on the pins themselves.PD Z TO. d = 1). d f.2 1. d f.3 1. d f.2 1.www. b f. d f f.2.com . The second cycle is executed as a NOP.2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f.Z Z TO. the data will be written back with a '0'.2 1. the instruction requires two cycles.DC. d f f.2 1.2 3 3 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k k k k k k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 C.2 1.2 1. d f.2 1. DS30430C-page 54 www.

(f) → (destination) Status Affected: C. If 'd' is 1 the result is stored back in register 'f'. Description: Words: 1 Words: 1 Cycles: 1 Cycles: 1 Description: Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W ADDLW 0x15 = Example ADDWF = kkkk kkkk Q1 Q2 Q3 Q4 Decode Read literal "k" Process data Write to W ANDLW 0x5F Before Instruction W 0x10 = 0xA3 After Instruction After Instruction W 1001 The contents of W register are AND’ed with the eight bit literal 'k'. Description: Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination ADDWF FSR.AND.com PIC16F8X 9.1] Operands: 0 ≤ f ≤ 127 d ∈ [0.com Example 0101 dfff ffff AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register.com www. DC.agelectronica.d 0111 dfff ffff Encoding: 00 Add the contents of the W register with register 'f'. Z Status Affected: Z Encoding: 11 k 111x kkkk kkkk AND Literal with W Encoding: 11 The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register. If 'd' is 0 the result is stored in the W register. 1 Before Instruction 0x17 0xC2 After Instruction W = FSR = Q Cycle Activity: f.1] Operation: (W) + (f) → (destination) Operation: (W) .d W = FSR = 0x17 0xC2 After Instruction 0xD9 0xC2 W = FSR = 0x17 0x02 DS30430C-page 55 www.1 Instruction Descriptions ADDLW Add Literal and W ANDLW Syntax: [label] ADDLW Syntax: [label] ANDLW Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Operation: (W) .agelectronica.agelectronica. www.www.agelectronica. Z Status Affected: Z Encoding: Description: 00 f.AND. The result is placed in the W register. If 'd' is 1 the result is stored back in register 'f'. DC.com . Q Cycle Activity: Before Instruction W k W 0x25 Add W and f ANDWF = 0x03 AND W with f Syntax: [label] ADDWF Syntax: [label] ANDWF Operands: 0 ≤ f ≤ 127 d ∈ [0. Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination ANDWF FSR. 0 Before Instruction W = FSR =  1998 Microchip Technology Inc. (k) → (W) Status Affected: C.

www.b 00bb bfff ffff Bit 'b' in register 'f' is cleared. is '0' then the next instruction is discarded. Skip if Clear Syntax: [label] BTFSC f.agelectronica.com  1998 Microchip Technology Inc.com . PC = address FALSE f.1 PROCESS_CODE Before Instruction PC = address HERE After Instruction BSF Bit Set f Syntax: [label] BSF Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 1 → (f<b>) Status Affected: None Encoding: Description: 01 1 Cycles: 1 Example 01bb bfff ffff Bit 'b' in register 'f' is set. making this a 2TCY instruction.agelectronica. PC = address TRUE if FLAG<1>=1.www. Words: Q Cycle Activity: if FLAG<1> = 0.agelectronica. 7 01 Before Instruction 10bb bfff ffff If bit 'b' in register 'f' is '1' then the next instruction is executed.com PIC16F8X BCF Bit Clear f Syntax: [label] BCF BTFSC Operands: Bit Test.com www.b 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Encoding: Description: 01 f. Words: 1 Cycles: 1 Q Cycle Activity: Example Description: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' BCF Encoding: Words: 1 Cycles: 1(2) Q Cycle Activity: FLAG_REG. 7 Before Instruction FLAG_REG = 0x0A After Instruction FLAG_REG = 0x8A DS30430C-page 56 www. If bit 'b'. and a NOP is executed instead. Q1 Q2 Q3 Q4 Decode Read register 'f' Process data No-Operat ion Q3 Q4 FLAG_REG = 0xC7 If Skip: After Instruction FLAG_REG = 0x47 (2nd Cycle) Q1 Q2 No-Operati No-Opera No-Operat No-Operat on tion ion ion Example HERE FALSE TRUE BTFSC GOTO • • • FLAG.agelectronica. in register 'f'.b Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' BSF FLAG_REG.

Push PC to Stack Process data Write to PC Q4 No-Opera tion HERE No-Opera No-Opera No-Operat tion tion ion CALL THERE Before Instruction PC = Address HERE After Instruction Before Instruction PC = Description: 1st Cycle No-Operati No-Opera No-Operat No-Operat on tion ion ion Example Encoding: address HERE PC = Address THERE TOS = Address HERE+1 After Instruction if FLAG<1> = 0.1 PROCESS_CODE 2nd Cycle Example 0kkk kkkk kkkk Call Subroutine. making this a 2TCY instruction. then the next instruction is discarded and a NOP is executed instead. return address (PC+1) is pushed onto the stack.agelectronica.com PIC16F8X BTFSS Bit Test f. (PCLATH<4:3>) → PC<12:11> Status Affected: None Operation: skip if (f<b>) = 1 Status Affected: None Encoding: Description: 01 Words: 1 Cycles: 1(2) Q Cycle Activity: If Skip: 11bb bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is executed. k → PC<10:0>.www.com DS30430C-page 57 www.agelectronica.agelectronica. Q1 Q2 Q3 Q4 Decode Read literal 'k'. PC = address FALSE if FLAG<1> = 1. If bit 'b' is '1'. The eleven bit immediate address is loaded into PC bits <10:0>. CALL is a two cycle instruction.b Syntax: [ label ] CALL k Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ k ≤ 2047 Operation: (PC)+ 1→ TOS.com www. PC = address TRUE  1998 Microchip Technology Inc.com . www. Q1 Q2 Q3 Q4 Decode Read register 'f' Process data No-Operat ion (2nd Cycle) Q1 Q2 HERE FALSE TRUE BTFSC GOTO • • • Q3 10 Words: 1 Cycles: 2 Q Cycle Activity: FLAG. Skip if Set CALL Call Subroutine Syntax: [label] BTFSS f. The upper bits of the PC are loaded from PCLATH. First.agelectronica.

W Z CLRWDT = = 0x00 1 Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h → WDT 0 → WDT prescaler.com .com 0x00 0 1 1  1998 Microchip Technology Inc.agelectronica.www. 1 → TO 1 → PD Status Affected: TO. PD Encoding: Description: 00 Words: 1 Cycles: 1 Q Cycle Activity: Example 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer. Q1 Q2 Q3 Q4 Decode No-Opera tion Process data Clear WDT Counter CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = WDT prescaler= TO = PD = DS30430C-page 58 www.agelectronica.agelectronica. It also resets the prescaler of the WDT.com PIC16F8X CLRF Clear f Syntax: [label] CLRF Operands: 0 ≤ f ≤ 127 Operation: 00h → (f) 1→Z Status Affected: Z Encoding: Description: 00 CLRW f 0001 1fff ffff Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h → (W) 1→Z Status Affected: Z Encoding: 00 The contents of register 'f' are cleared and the Z bit is set. Description: Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' CLRF Q Cycle Activity: Example FLAG_REG = 0x5A xxxx Q1 Q2 Q3 Q4 Decode No-Opera tion Process data Write to W CLRW = = 0x00 1 W = 0x5A After Instruction After Instruction FLAG_REG Z 0xxx Before Instruction Before Instruction FLAG_REG 0001 W register is cleared. www. Status bits TO and PD are set.com www.agelectronica. Zero bit (Z) is set.

Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination DECF = address HERE After Instruction CNT if CNT PC if CNT PC = = = ≠ = CNT . 1 LOOP Before Instruction 00 Words: Q Cycle Activity: (2nd Cycle) Q1 Q2 PC Encoding: ffff No-Opera No-Operat No-Operati No-Operat tion ion on ion Decrement f Syntax: dfff Decode Before Instruction After Instruction 1011 The contents of register 'f' are decremented. the next instruction.agelectronica.0 REG1 = 0x13 REG1 W = = 0x13 0xEC If Skip: DECF [label] DECF f.agelectronica. skip if result = 0 Status Affected: None Encoding: Description: 00 f. If 'd' is 0 the result is placed in the W register.d 0 ≤ f ≤ 127 d ∈ [0.1 0. If the result is 0. Skip if 0 Syntax: [ label ] DECFSZ f. www. If 'd' is 0 the result is stored in W. 1 Cycles: 1 Example Example HERE DECFSZ GOTO CONTINUE • • • CNT. is executed.com .com www.1] Operation: (f) . address HERE+1 CNT. If 'd' is 1 the result is placed back in register 'f'.com DS30430C-page 59 www.com PIC16F8X COMF Complement f Syntax: [ label ] COMF Operands: DECFSZ Decrement f. If 'd' is 1 the result is stored back in register 'f'.1 → (destination).www. If the result is 1. If 'd' is 0 the result is stored in the W register. address CONTINUE 0.1] Operation: (f) → (destination) Operation: Status Affected: Z (f) .agelectronica.1] Operands: 0 ≤ f ≤ 127 d ∈ [0.d Operands: 0 ≤ f ≤ 127 d ∈ [0.d 1001 dfff ffff The contents of register 'f' are complemented.1 → (destination) Status Affected: Z Q1 Q2 Q3 Q4 Read register 'f' Process data Write to destination Q3 Q4 Description: 0011 dfff ffff Decrement register 'f'. then a NOP is executed instead making it a 2TCY instruction. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Encoding: Description: Words: 1 Cycles: 1(2) Q Cycle Activity: Example COMF 00 REG1. If 'd' is 1 the result is stored back in register 'f'. 1 Before Instruction CNT Z = = 0x01 0 = = 0x00 1 After Instruction CNT Z  1998 Microchip Technology Inc.agelectronica.

agelectronica. Increment f Encoding: Description: 00 1 Words: 1 Cycles: 2 Cycles: 1 1st Cycle 2nd Cycle Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to PC No-Operat ion Q Cycle Activity: 1010 dfff ffff The contents of register 'f' are incremented. GOTO is a two cycle instruction.com .agelectronica. 1 No-Operat No-Opera No-Operat ion tion ion Example Before Instruction Example GOTO THERE CNT Z After Instruction PC = DS30430C-page 60 www.com Address THERE = = 0xFF 0 = = 0x00 1 After Instruction CNT Z  1998 Microchip Technology Inc. The eleven bit immediate value is loaded into PC bits <10:0>.d Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination INCF CNT. The upper bits of PC are loaded from PCLATH<4:3>.agelectronica.com PIC16F8X GOTO Unconditional Branch INCF Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 2047 Operands: Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> 0 ≤ f ≤ 127 d ∈ [0. If 'd' is 0 the result is placed in the W register.agelectronica.com www. Words: Q Cycle Activity: INCF f.1] Operation: (f) + 1 → (destination) None Status Affected: Z Status Affected: Encoding: Description: 10 GOTO k 1kkk kkkk kkkk GOTO is an unconditional branch. If 'd' is 1 the result is placed back in register 'f'.www. www.

If the result is 0.OR.d Description: 11 1 Cycles: 1 Example 1000 kkkk kkkk The contents of the W register is OR’ed with the eight bit literal 'k'. address HERE +1 DS30430C-page 61 www. Skip if 0 IORLW Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0.com www. If 'd' is 1 the result is placed back in register 'f'. Words: Q Cycle Activity: 1111 Inclusive OR Literal with W Encoding: None Encoding: Description: INCFSZ f. Words: Q Cycle Activity: IORLW k Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W IORLW 0x35 Before Instruction W = 0x9A After Instruction W Z = = 0xBF 1 No-Opera No-Opera No-Operati tion tion on HERE INCFSZ GOTO CONTINUE • • • CNT. k → (W) Operation: Status Affected: Z Status Affected: 00 1 Cycles: 1(2) If Skip: ffff Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Q3 Q4 (2nd Cycle) Q1 Q2 No-Operat ion Example dfff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register.agelectronica.agelectronica. a NOP is executed instead making it a 2TCY instruction. the next instruction is executed.1] Operands: 0 ≤ k ≤ 255 Operation: (f) + 1 → (destination).www.com . www. The result is placed in the W register.com PIC16F8X INCFSZ Increment f. If the result is 1. 1 LOOP Before Instruction PC = address HERE After Instruction CNT = if CNT= PC = if CNT≠ PC =  1998 Microchip Technology Inc.com CNT + 1 0.agelectronica.agelectronica. address CONTINUE 0. skip if result = 0 (W) .

1] Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) Operation: (f) → (destination) Status Affected: None Status Affected: Z Encoding: Syntax: Operands: [ label ] Encoding: Description: 00 1000 dfff ffff The contents of register f is moved to a destination dependant upon the status of d.com .d 0100 dfff ffff Description: Inclusive OR the W register with register 'f'.com PIC16F8X IORWF Inclusive OR W with f MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0.agelectronica.d Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination Description: 00 1 Cycles: 1 Example 0000 f 1fff ffff Move data from W register to register 'f'. If 'd' is 0 the result is placed in the W register. Words: 1 Cycles: 1 Q Cycle Activity: Q1 MOVLW k Example Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W MOVLW 0x5A After Instruction RESULT.com  1998 Microchip Technology Inc. If 'd' is 1 the result is placed back in register 'f'.com www.1] Operands: 0 ≤ k ≤ 255 Operation: (W) . (f) → (destination) Operation: k → (W) Status Affected: Z Status Affected: None Encoding: IORWF 00 f.www. If d = 1.agelectronica. 0 W = 0x5A Before Instruction RESULT = W = 0x13 0x91 After Instruction RESULT = W = Z = MOVF 0x13 0x93 1 MOVWF Move f Move W to f Syntax: [ label ] 0 ≤ f ≤ 127 d ∈ [0. destination is W register. The don’t cares will assemble as 0’s. www. d = 1 is useful to test a file register since status flag Z is affected. 0 After Instruction OPTION = W = 0x4F 0x4F W = value in FSR register Z =1 DS30430C-page 62 www. the destination is file register f itself.OR. Words: 1 Cycles: 1 Q Cycle Activity: MOVF f.agelectronica. Words: 1 Cycles: 1 Q Cycle Activity: Example Encoding: Description: 11 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination IORWF 00xx kkkk kkkk The eight bit literal 'k' is loaded into W register. If d = 0. Words: Q Cycle Activity: MOVWF Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write register 'f' MOVWF OPTION_REG Before Instruction OPTION = W = 0xFF 0x4F After Instruction Example MOVF FSR.agelectronica.

Stack is POPed and Top of Stack (TOS) is loaded in the PC. GIE (INTCON<7>).com . This instruction is supported for code compatibility with PIC16C5X products. 1 → GIE Status Affected: None Encoding: Description: 00 NOP 0000 0xx0 0000 Encoding: No operation. Words: 1 Cycles: 1 Example To maintain upward compatibility with future PIC16CXX products. www. Words: Q Cycle Activity: RETFIE Q1 Q2 Q3 Q4 Decode No-Opera tion Set the GIE bit Pop from the Stack No-Operat ion No-Opera No-Opera No-Operat tion tion ion RETFIE After Interrupt PC = GIE = OPTION Load Option Register Syntax: [ label ] Operands: None Operation: (W) → OPTION TOS 1 OPTION Status Affected: None Encoding: 00 0000 0110 0010 Description: The contents of the W register are loaded in the OPTION register. do not use this instruction. This is a two cycle instruction. Interrupts are enabled by setting Global Interrupt Enable bit.agelectronica.agelectronica. Words: 1 Cycles: 1 Q Cycle Activity: Description: Q1 Decode Example Q2 Q3 Q4 No-Opera No-Opera No-Operat tion tion ion NOP 00 1 Cycles: 2 1st Cycle 2nd Cycle Example 0000 0000 1001 Return from Interrupt.com PIC16F8X NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS → PC. Since OPTION is a readable/writable register.com DS30430C-page 63 www.agelectronica. the user can directly address it.com www.agelectronica.www.  1998 Microchip Technology Inc.

The stack is POPed and the top of the stack (TOS) is loaded into the program counter.W now has table value • • • TABLE ADDWF PC RETLW k1 RETLW k2 PC = TOS .com www. TOS → PC Operation: TOS → PC Status Affected: None None Encoding: Status Affected: Encoding: RETLW k 11 Description: 01xx kkkk kkkk The W register is loaded with the eight bit literal 'k'.agelectronica. Words: 1 Cycles: 2 Q Cycle Activity: 1st Cycle 2nd Cycle Description: Q2 Decode Read literal 'k' Q3 Q4 No-Opera Write to W.com PIC16F8X RETLW Return with Literal in W RETURN Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: None Operation: k → (W). tion Pop from the Stack No-Opera No-Opera No-Operat tion tion ion No-Operat ion 00 1 Cycles: 2 1st Cycle 2nd Cycle Example RETURN 0000 0000 1000 Return from subroutine. This is a two cycle instruction.agelectronica.Begin table .W = offset .agelectronica. Words: Q Cycle Activity: Q1 Return from Subroutine Q1 Decode No-Operat ion Q2 Q3 Q4 No-Opera No-Opera Pop from tion tion the Stack No-Opera No-Opera No-Opera tion tion tion RETURN After Interrupt Example CALL TABLE . End of table Before Instruction W = 0x07 After Instruction W DS30430C-page 64 www. The program counter is loaded from the top of the stack (the return address).offset value . • • • RETLW kn .com = value of k8  1998 Microchip Technology Inc. This is a two cycle instruction.W contains table . www.agelectronica.www.com .

0  1998 Microchip Technology Inc. If 'd' is 0 the result is placed in the W register.www.com dfff ffff Register f Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination RRF REG1. If 'd' is 1 the result is placed back in register 'f'.d RRF f. REG1 C = = 1110 0110 0 = = = 1110 0110 0111 0011 0 After Instruction REG1 W C DS30430C-page 65 www.agelectronica.com PIC16F8X RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0.agelectronica.d Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: Description: 00 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag.agelectronica. If 'd' is 1 the result is stored back in register 'f'.1] RLF f.com .agelectronica. If 'd' is 0 the result is placed in the W register.com www.0 Before Instruction = = 1110 0110 0 = = = 1110 0110 1100 1100 1 After Instruction REG1 W C Q Cycle Activity: Example Before Instruction REG1 C 1100 The contents of register 'f' are rotated one bit to the right through the Carry Flag. www. C Encoding: Description: 00 Register f C Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Example Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination RLF REG1.1] Operands: 0 ≤ f ≤ 127 d ∈ [0.

agelectronica. DC. Z Encoding: 11 110x kkkk kkkk Description: The W register is subtracted (2’s complement method) from the eight bit literal 'k'. Words: 1 Cycles: 1 Words: 1 Example 1: Cycles: 1 Status Affected: TO. PD Encoding: Description: Q Cycle Activity: 00 0000 0110 0011 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W SUBLW 0x02 Before Instruction Q1 Decode Q2 Q3 No-Opera No-Opera tion tion Q4 W C Z Go to Sleep = = = 1 ? ? After Instruction Example: SLEEP W C Z Example 2: = = = 1 1.com 0xFF 0.8 for more details. PD is cleared. 0 → WDT prescaler.com .agelectronica. result is nega0  1998 Microchip Technology Inc.www. See Section 14. 0 → PD Operation: k . TO is set. result is zero 1 Before Instruction W C Z = = = 3 ? ? After Instruction W = C = tive Z = DS30430C-page 66 www.(W) → (W) Status Affected: C.agelectronica. 1 → TO. The power-down status bit. result is positive 0 Before Instruction W C Z = = = 2 ? ? After Instruction W C Z Example 3: = = = 0 1. The result is placed in the W register. The processor is put into SLEEP mode with the oscillator stopped.agelectronica.com PIC16F8X SLEEP SUBLW Subtract W from Literal Syntax: Syntax: [ label ] 0 ≤ k ≤ 255 [ label ] SLEEP SUBLW k Operands: None Operands: Operation: 00h → WDT. Watchdog Timer and its prescaler are cleared. www. Time-out status bit.com www.

1 Before Instruction REG1 W C Z Encoding: Example To maintain upward compatibility with future PIC16CXX products.1] Operands: 0 ≤ f ≤ 127 d ∈ [0.www. If 'd' is 1 the result is stored back in register 'f'. Z Encoding: Description: 00 1 Cycles: 1 Example 1: dfff ffff Subtract (2’s complement method) W register from register 'f'. REG1. Since TRIS registers are readable and writable. the user can directly address them. DC. Words: Q Cycle Activity: 0010 Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination SUBWF Description: 00 Words: 1 Cycles: 1 Q Cycle Activity: Example 2: Example = = = = Q1 Q2 Q3 Q4 Read register 'f' Process data Write to destination SWAPF REG.d Operands: 0 ≤ f ≤ 127 d ∈ [0. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.agelectronica.agelectronica. TRIS f Status Affected: None 0 2 1.com = = = = 0xA5 = = 0xA5 0x5A 1 2 1.1] Operation: (f) . www. result is positive 0 2 2 ? ? TRIS Load TRIS Register Syntax: [label] Operands: 5≤f≤7 Operation: (W) → TRIS register f.com .agelectronica. result is negative 0 00 0000 0110 0fff Description: The instruction is supported for code compatibility with the PIC16C5X products. result is zero 1 1 2 ? ? After Instruction REG1 W C Z = After Instruction Encoding: 0xFF 2 0. Words: 1 Cycles: 1 Before Instruction REG1 W C Z 0 REG1 W After Instruction REG1 W C Z ffff Before Instruction 3 2 ? ? Before Instruction REG1 W C Z dfff Decode After Instruction REG1 W C Z 1110 The upper and lower nibbles of register 'f' are exchanged. do not use this instruction.(W) → (destination) Operation: (f<3:0>) → (destination<7:4>).com www.d Status Affected: C.agelectronica. = = = = = = = = Example 3: = = = = REG1 = = = =  1998 Microchip Technology Inc. DS30430C-page 67 www.com PIC16F8X SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] Syntax: [ label ] SWAPF f. If 'd' is 0 the result is stored in the W register. (f<7:4>) → (destination<3:0>) Status Affected: None SUBWF f.

agelectronica. k → (W) Status Affected: Z Encoding: 11 1010 kkkk kkkk Description: The contents of the W register are XOR’ed with the eight bit literal 'k'.www.agelectronica.XOR.d dfff ffff Exclusive OR the contents of the W register with register 'f'.agelectronica. (f) → (destination) Status Affected: Z XORLW k 0 ≤ k ≤ 255 Operation: (W) .com www. Words: 1 Cycles: 1 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode Read literal 'k' Process data Write to W XORLW Encoding: Description: 00 0110 f. www.com  1998 Microchip Technology Inc.1] Operation: (W) . If 'd' is 1 the result is stored back in register 'f'. Words: 1 Cycles: 1 Q Cycle Activity: XORWF Q1 Q2 Q3 Q4 Decode Read register 'f' Process data Write to destination 0xAF Before Instruction W = Example 0xB5 After Instruction W = 0x1A XORWF REG 1 Before Instruction REG W = = 0xAF 0xB5 = = 0x1A 0xB5 After Instruction REG W DS30430C-page 68 www.XOR.agelectronica. If 'd' is 0 the result is stored in the W register.com PIC16F8X XORLW Syntax: Operands: Exclusive OR Literal with W XORWF Exclusive OR W with f [label] Syntax: [label] Operands: 0 ≤ f ≤ 127 d ∈ [0. The result is placed in the W register.com .

 1998 Microchip Technology Inc. PICSTART Plus is not recommended for production programming. ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT through Pentium based machines under Windows 3. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers. A CE compliant version of PICMASTER is available for European Union (EU) countries. 10.5 Interchangeable target probes allow the system to be easily reconfigured for emulation of different processors. PIC16C5X. PIC16C5X. PIC16CXXX and PIC17CXX devices with up to 40 pins. The PC compatible 386 (and higher) machine platform and Microsoft Windows 3. 10. and source debugging from a single environment. PICMASTER is supplied with the MPLAB Integrated Development Environment (IDE). low-cost prototype programmer.www.com PIC16F8X 10. It connects to the PC via one of the COM (RS-232) ports.com www.x environment were chosen to best make these features available to you. PIC16CXXX and PIC17CXX families. PIC14C000. PRO MATE II is CE compliant. PIC14C000. In standalone mode the PRO MATE II can read. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. Larger pin count devices such as the PIC16C923. ICEPIC features real time. PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers.x environment. non-intrusive emulation. “make” and download. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability.1 Development Tools The PICmicrο microcontrollers are supported with a full range of hardware and software development tools: • PICMASTER/PICMASTER CE Real-Time In-Circuit Emulator • ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator • PRO MATE II Universal Programmer • PICSTART Plus Entry-Level Prototype Programmer • PICDEM-1 Low-Cost Demonstration Board • PICDEM-2 Low-Cost Demonstration Board • PICDEM-3 Low-Cost Demonstration Board • MPASM Assembler • MPLAB SIM Software Simulator • MPLAB-C17 (C Compiler) • Fuzzy Logic Development System (fuzzyTECH−MP) 10. www.0 DEVELOPMENT SUPPORT 10.com . PIC12CXXX.agelectronica. verify or program PIC12CXXX. PIC16C924 and PIC17C756 may be supported with an adapter socket.2 PICMASTER: High Performance Universal In-Circuit Emulator with MPLAB IDE 10. PICSTART Plus Entry Level Development System The PICSTART programmer is an easy-to-use.agelectronica.4 PRO MATE II: Universal Programmer The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. It can also set configuration and code-protect bits in this mode. keys to enter commands and a modular detachable socket assembly to support various package types.agelectronica. The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools.com DS30430C-page 69 www. PICSTART Plus supports all PIC12CXXX. The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC14C000. PIC16CXXX and PIC17CXX devices. It has an LCD display for displaying error messages. the end user.3 ICEPIC: Low-Cost PICmicro™ In-Circuit Emulator ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX. PIC16C5X.agelectronica. PICSTART Plus is CE compliant. which allows editing.

conditional assembly.6 PICDEM-1 Low-Cost PICmicro Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers.agelectronica.agelectronica. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A).9 MPLAB™ Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market.1 software for showing the demultiplexed LCD signals on a PC. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). PIC16CXXX. PIC14000. push-button switches. Some of the features include DS30430C-page 70 www.com an RS-232 interface. a potentiometer for simulated analog input.  1998 Microchip Technology Inc.com . on a PRO MATE II programmer or PICSTART-Plus. PIC16C8X.com PIC16F8X 10. a potentiometer for simulated analog input. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). push-button switches.editor . The PICMASTER emulator may also be used with the PICDEM-3 board to test firmware. 10. Some of the features include an RS-232 interface.www. MPASM allows full symbolic debugging from PICMASTER. It generates various object code formats to support Microchip's development tools as well as third party programmers.absolute listing file • Transfer data dynamically via DDE (soon to be replaced by OLE) • Run up to four emulators on the same PC The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). and several source and listing formats. PIC16C61. a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connection to an LCD module and a keypad.agelectronica.emulator . 10.10 Assembler (MPASM) The MPASM Universal Macro Assembler is a PC-hosted symbolic assembler. The users can program the sample microcontrollers provided with the PICDEM-1 board. on a PRO MATE II or PICSTART-Plus programmer. and easily test firmware. Microchip’s Universal Emulator System.source files . MPASM offers full featured Macro capabilities. that is capable of displaying time. PIC16C65. 10. The user can program the sample microcontrollers provided with the PICDEM-2 board. with 4 commons and 12 segments. PIC16C64. MPLAB is a windows based application which contains: • A full featured editor • Three operating modes . The user can program the sample microcontrollers provided with the PICDEM-3 board.8 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. The PICMASTER emulator may also be used with the PICDEM-2 board to test firmware. All necessary hardware and software is included to run basic demo programs. All the necessary hardware and software is included to run the basic demonstration programs. on a PRO MATE II programmer or PICSTART Plus with an adapter socket. a thermistor and separate headers for connection to an external LCD module and a keypad. push-button switches and eight LEDs connected to PORTB.com www. PIC16C73 and PIC16C74 microcontrollers. and easily test firmware. It supports all microcontroller series including the PIC12C5XX. PIC16C62X.agelectronica. www. Also provided on the PICDEM-3 board is an LCD panel. PIC17C43 and PIC17C44. The PICDEM-3 provides an additional RS-232 interface and Windows 3. PIC16C71. All the necessary hardware and software is included to run the basic demonstration programs.7 PICDEM-2 Low-Cost PIC16CXX Demonstration Board The PICDEM-2 is a simple demonstration board that supports the PIC16C62. 10. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the firmware to the emulator for testing. a potentiometer for simulated analog input. It will also support future 44-pin PLCC microcontrollers with a LCD Module. PIC17C42.simulator • A project manager • Customizable tool bar and key mapping • A status bar with project information • Extensive on-line help MPLAB allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) • Debug using: . Some of the features include a RS-232 interface. temperature and day of the week. PIC16C5X. and PIC17CXX families. and easily test firmware.

The Total Endurance Disk is included to aid in trade-off analysis and reliability calculations.  1998 Microchip Technology Inc. Directives are helpful in making the development of your assemble source code shorter and more maintainable. • Produces all the files (Object. execute until break. The Software Simulator offers the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. and a programming interface to program test transmitters. and special) required for symbolic debug with Microchip’s emulator systems.agelectronica. The MPLAB-C Code Development System is a complete ‘C’ compiler and integrated development environment for Microchip’s PIC17CXXX family of microcontrollers. For easier source level debugging. the user may examine or modify any of the data areas or provide external stimulus to any of the pins.11 Software Simulator (MPLAB-SIM) The MPLAB-SIM Software Simulator allows code development in a PC host environment. 10. The total kit can significantly reduce time-to-market and result in an optimized system.14 MP-DriveWay – Application Code Generator MP-DriveWay is an easy-to-use Windows-based Application Code Generator. The input/output radix can be set by the user and the execution can be performed in.12 C Compiler (MPLAB-C17) 10. The compiler provides powerful integration capabilities and ease of use not found with other compilers.agelectronica.a low cost introductory version.com PIC16F8X MPASM has the following features to assist in developing software for specific use applications. The code produced is highly modular and allows easy integration of your own code. • Macro assembly capability. The kit includes everything necessary to read. Edition for implementing more complex systems. fuzzyTECH-MP. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.16 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. • Supports Hex (default). The HCS evaluation kit includes an LCD display to show changing codes.agelectronica.com DS30430C-page 71 www. write. Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic systems implementation. Symbol. and a full-featured version. 10. 10.www. The output is fully compatible with Microchip’s MPLAB-C C compiler. MPASM provides a rich directive language to support programming of the PICmicro. generate all the initialization and many functional code modules in C language. 10. It allows the user to simulate the PICmicro series microcontrollers on an instruction level.13 Fuzzy Logic Development System (fuzzyTECH-MP) fuzzyTECH-MP fuzzy logic development tool is available in two versions . 10.com . MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. www.agelectronica.com www. or in a trace mode. Listing. for designers to gain a comprehensive working knowledge of fuzzy logic system design. MP Explorer. single step. a decoder to decode transmissions. • Provides translation of Assembler source code to object code for all Microchip microcontrollers. erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. Decimal and Octal source and listing formats. with a click of the mouse. With MP-DriveWay you can visually configure all the peripherals in a PICmicro device and. the compiler provides symbol information that is compatible with the MPLAB IDE memory display.15 SEEVAL Evaluation and Programming System The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. On any given instruction.

com ü ü ü ü ü ü ü ü ü www.agelectronica.agelectronica.agelectronica. Kit PRO MATE II Universal Programmer KEELOQ Programmer Demo Boards  1998 Microchip Technology Inc.com HCS200 HCS300 HCS301 ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü SEEVAL Designers Kit PICDEM-1 24CXX 25CXX 93CXX PIC16F8X PIC14000 DEVELOPMENT TOOLS FROM MICROCHIP PIC12C5XX MPLAB Integrated Development Environment Software Tools www.com .agelectronica. Tool ü ü MP-DriveWay Applications Code Generator PIC17C75X ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü Programmers Total Endurance Software Model PICSTARTPlus Low-Cost Universal Dev.com TABLE 10-1: DS30430C-page 72 Emulator Products www.PIC16C5X PIC16CXXX ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü ü PICMASTER/ PICMASTER-CE In-Circuit Emulator ICEPIC Low-Cost In-Circuit Emulator ü ü ü PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X MPLAB C17 Compiler fuzzyTECH-MP Explorer/Edition Fuzzy Logic Dev. PICDEM-2 PICDEM-3 KEELOQ Evaluation Kit www.

.................................................................................... Exposure to maximum rating conditions for extended periods may affect device reliability...........................6V) Total power dissipation(1) ...........................∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin...................................± 20 mA Output clamp current...................................6V to (VDD + 0..............-55°C to +125°C Storage temperature ............. -65°C to +150°C Voltage on VDD with respect to VSS ...................................... † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device......................................................................................................................20 mA Maximum current sunk by PORTA ... IOK (VO < 0 or VO > VDD) .....................................................................................0 PIC16F8X ELECTRICAL CHARACTERISTICS FOR PIC16F83 AND PIC16F84 Absolute Maximum Ratings † Ambient temperature under bias..........................................................150 mA Maximum current into VDD pin .........................................  1998 Microchip Technology Inc.................... www..............3 to +14V Voltage on any pin with respect to VSS (except VDD and MCLR)......................agelectronica........................................................................................................................................... may cause latch-up..............com DS30430C-page 73 www.......................................................... inducing currents greater than 80 mA.....3 to +7........................................................................................................www.................80 mA Maximum current sourced by PORTA ...........50 mA Maximum current sunk by PORTB.......................................com ..........................................................................................................................100 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD ................................................... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied............................................................................................................................................... -0..800 mW Maximum current out of VSS pin ....................... -0............................................................± 20 mA Maximum output current sunk by any I/O pin.................................................................agelectronica...............................150 mA Maximum current sourced by PORTB..............................................agelectronica.............25 mA Maximum output current sourced by any I/O pin ...................................... -0..............................agelectronica........................................... a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS..............com www......................100 mA Input clamp current...........5V Voltage on MCLR with respect to VSS(2) ............. Thus.......................................... IIK (VI < 0 or VI > VDD).................com PIC16F83/84 10...

at 3.5V WDT dis Freq: VDD: IDD: IPD: Freq: 4. VDD: IDD: 4.5V 1. at 2V WDT dis 2.0V 4. 4.0 µA typ.8 mA typ. www. at 32 kHz.0V WDT dis 200 kHz max.0 MHz max.5V WDT dis 4.0V WDT dis 200 kHz max. at 5.0 MHz max. at 32 kHz.5V 4.agelectronica. at 5.0V 45 µA max.0V to 6. Do not use in LP mode PIC16LF84-04 PIC16LF83-04 VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 2.5 mA max.com  1998 Microchip Technology Inc.5V 14 µA max. at 5. 2. at 4V WDT dis 4.com PIC16F8X TABLE 10-1 XT HS LP CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16F84-04 PIC16F83-04 OSC RC PIC16F83/84 PIC16F84-10 PIC16F83-10 VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4.5V to 5. The shaded sections indicate oscillator selections which are tested for functionality. at 4.0 MHz max.5V 10 mA max.5V to 5.5V 7. 4. at 4. at 5.5V to 5.agelectronica. at 5. 2.5 mA max.agelectronica. at 5.0V to 6.0 µA typ. but not for MIN/MAX specifications.0V 4.www. at 5. at 5.0V 7 µA max. at 4V WDT dis 4.0 µA typ.5V to 5. DS30430C-page 74 www.5V VDD: IDD: 4.5V typ.0V 0.5V WDT dis IPD: 1.5 mA typ.5V 7.5V 1.5V 14 µA max. at 5.5 mA max. at 5. at 2V WDT dis 2. It is recommended that the user select the device type that ensures the specifications required.5V 1.0 MHz max. 2.com .6 µA typ. IPD: 1.0V to 6.0 MHz max. Freq: 10 MHz max.0V to 6. Do not use in HS mode VDD: IDD: IPD: Freq: 2.0V 4.0V 48 µA typ.agelectronica.0 µA max.0 µA typ.5V WDT dis 4.0 µA max.0 MHz max.0V to 6.0 MHz max.0V 4. at 2.5 mA max.5V 1.8 mA typ. 4..com www.0V to 6. VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4.

0V. Power-down current is measured with the part in SLEEP mode. oscillator type.com PIC16F83/84 10.com .5 1. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. from rail to rail. current through Rext is not included. 2: The supply current is mainly a function of the operating voltage and frequency.com DS30430C-page 75 www.1 DC CHARACTERISTICS: DC Characteristics Power Supply Pins Sym Parameter No. VDD = 5. WDT disabled. 25˚C unless otherwise stated. Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C ≤ TA ≤ +70°C (commercial) -40°C ≤ TA ≤ +85°C (industrial) Min Typ† Max Units Conditions 4. WDT enabled/disabled as specified. VDD = 5. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm. MCLR = VDD.0 16 µA * These parameters are characterized but not tested.agelectronica. 3: The power down current in SLEEP mode does not depend on the oscillator type.0 MHz.0V.0 4. industrial VDD = 4. internal code execution pattern. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave. T0CKI = VDD.05* — — — — 1.0 14 µA D021A — 1.agelectronica.com www. VDD = 5. WDT disabled. These parameters are for design guidance only and are not tested.8 7. www. and temperature also have an impact on the current consumption.0 28 µA D021 — 1. Characteristic D001 D001A D002 VDD Supply Voltage VDR D003 VPOR D004 SVDD RAM Data Retention Voltage(1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current(2) IDD D010 D010A PIC16F8X PIC16F84. † Data in "Typ" column is at 5.3 4.0V.0 5.5* — — — 6. commercial VDD = 4. WDT enabled. RC and LP osc configuration HS osc configuration Device in SLEEP mode — VSS — V See section on Power-on Reset for details 0.5V VDD = 4.agelectronica. industrial D013 — 5 10 mA D020 IPD Power-down Current(3) — 7. PIC16F83 (Commercial. 4: For RC osc configuration. all I/O pins tristated.5 — V V V XT.5 10 V/ms See section on Power-on Reset for details mA mA RC and XT osc configuration(4) FOSC = 4. with all I/O pins in hi-impedance state and tied to VDD and VSS. pulled to VDD.  1998 Microchip Technology Inc.5V (During Flash programming) HS osc configuration (PIC16F84-10) FOSC = 10 MHz.agelectronica.5V FOSC = 4.0V.www. Other factors such as I/O pin loading and switching rate.0 MHz.

Industrial) DC Characteristics Power Supply Pins Parameter No.0V. industrial D020 IPD Power-down Current(3) — 3. and temperature also have an impact on the current consumption.0 MHz. Sym Characteristic 2.agelectronica. 2: The supply current is mainly a function of the operating voltage and frequency.0V. RC.www. T0CKI = VDD. WDT enabled/disabled as specified. WDT enabled.0 1. commercial VDD = 2. WDT disabled. from rail to rail.4 7.3 4 10 mA mA D014 — 15 45 µA D001 D002 VDD VDR D003 VPOR D004 SVDD IDD Supply Voltage RAM Data Retention Voltage(1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current(2) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C ≤ TA ≤ +70°C (commercial) -40°C ≤ TA ≤ +85°C (industrial) Min Typ† Max Units Conditions V/ms See section on Power-on Reset for details RC and XT osc configuration(4) FOSC = 2.agelectronica.com www. all I/O pins tristated.agelectronica. and LP osc configuration Device in SLEEP mode — VSS — V See section on Power-on Reset for details 0. † Data in "Typ" column is at 5. Other factors such as I/O pin loading and switching rate. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave. Power-down current is measured with the part in SLEEP mode. These parameters are for design guidance only and are not tested.com  1998 Microchip Technology Inc. oscillator type. internal code execution pattern. WDT disabled VDD = 2.4 9.0V. MCLR = VDD. current through Rext is not included.com . www.05* — — D010 D010A — — 1 7. 25°C unless otherwise stated.com PIC16F8X 10. VDD = 5.0 MHz. DS30430C-page 76 www. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.agelectronica.0 µA D021A — 0. with all I/O pins in hi-impedance state and tied to VDD and VSS. industrial VDD = 2.0 — V V XT.5* — — 6. 3: The power down current in SLEEP mode does not depend on the oscillator type. WDT disabled.0 16 µA D021 — 0.5V FOSC = 2. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.0V.0 µA * These parameters are characterized but not tested. pulled to VDD. VDD = 5. VDD = 2.0V. 4: For RC osc configuration.5V (During Flash programming) LP osc configuration FOSC = 32 kHz.2 DC CHARACTERISTICS: PIC16F83/84 PIC16LF84. PIC16LF83 (Commercial.

0 mA.com PIC16F8X PIC16F83/84 10. RA4/T0CKI OSC1 Conditions — — — — V Output Low Voltage — — I/O ports 0.com DS30430C-page 77 www.5 V(4) entire range(4) entire range VDD VDD VDD VDD V V 4.5V(4) entire range(4) entire range VDD — V V 400* µA VDD = 5. VDD = 4.5V — — D092 OSC2/CLKOUT VDD-0. 3: Negative current is defined as coming out of the pin.agelectronica.7 VDD — Hysteresis of TBD Schmitt Trigger inputs PORTB weak pull-up current 50* 250* Input Leakage Current(2. Do not drive the PIC16F8X with an external clock while the device is in RC mode. VDD = 4.5 V ≤ VDD ≤ 5. The specified levels represent normal operating conditions.16VDD 0.0V. HS and LP modes)(1) 0.7 V IOH = -3. www. HS and LP modes)(1) OSC1 (RC mode) Input High Voltage I/O ports with TTL buffer Min Typ† Max Units VSS VSS VSS Vss Vss Vss — 0.6 V IOL = 1. VDD = 4.5V * These parameters are characterized but not tested.2VDD 0.com www. RA4/T0CKI.8 0. Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C ≤ TA ≤ +70°C (commercial) -40°C ≤ TA ≤ +85°C (industrial) Operating voltage VDD range as described in DC spec Section 10. Sym VIL D030 D030A D031 D032 D033 D034 VIH D040 D040A D041 D042 D043 D050 VHYS D070 IPURB D060 IIL D061 D063 Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level.3 DC CHARACTERISTICS: PIC16F84.com .4 — 0.5V Output High Voltage — — D090 VOH I/O ports(3) VDD-0.agelectronica. These parameters are for design guidance only and are not tested.48VDD — with Schmitt Trigger buffer 0.5 mA. † Data in “Typ” column is at 5. VDD = 4.2VDD 0. OSC1 0.6 V IOL = 8.5V — — OSC2/CLKOUT 0. PIC16F83 (Commercial. XT.agelectronica. D080 D083 VOL  1998 Microchip Technology Inc.5 V ≤ VDD ≤ 5. or chip damage may result. 4: The user may choose the better of the two specs.agelectronica.45VDD — MCLR.2.0V. VPIN = VSS ±1 µA ±5 ±5 µA µA Vss ≤ VPIN ≤ VDD. 25°C unless otherwise stated. Pin at hi-impedance Vss ≤ VPIN ≤ VDD Vss ≤ VPIN ≤ VDD.7 V IOH = -1. the OSC1 pin is a Schmitt Trigger input.3VDD 0.3) — — I/O ports MCLR. PIC16LF83 (Commercial. Note 1: In RC oscillator configuration.1 and Section 10. DC Characteristics All Pins Except Power Supply Pins Parameter No.6 mA.www.1VDD V V V V V V 4. RA4/T0CKI OSC1 (XT. Industrial) PIC16LF84. Higher leakage current may be measured at different input voltages. HS and LP osc configuration — — — — — — — 2.85 (RC mode) VDD — OSC1 (XT.3 mA.

www.com www.0 In XT.agelectronica.agelectronica.com .agelectronica.5 5. All I/O pins and OSC2 (RC mode) Data EEPROM Memory Endurance VDD for read/write Erase/Write cycle time Program Flash Memory Endurance VDD for read Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C ≤ TA ≤ +70°C (commercial) -40°C ≤ TA ≤ +85°C (industrial) Operating voltage VDD range as described in DC spec Section 10. HS and LP modes when external clock is used to drive OSC1.5 D133 TPEW Erase/Write cycle time — 10 — * These parameters are characterized but not tested.0 — 10 20* 100 VMIN 1000 — — 6. Industrial) DC Characteristics All Pins Except Power Supply Pins Sym Characteristic D100 COSC2 Capacitive Loading Specs on Output Pins OSC2 pin D101 CIO D120 D121 ED VDRW D122 TDEW D130 D131 EP VPR Parameter No. 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. E/W 25°C at 5V V VMIN = Minimum operating voltage ms E/W V VMIN = Minimum operating voltage V ms — D132 VPEW VDD for erase/write 4. Industrial) PIC16LF84.2.com PIC16F8X 10.agelectronica.1 and Section 10. PIC16F83 (Commercial.www.com  1998 Microchip Technology Inc.0V. DS30430C-page 78 www. Min Typ† Max Units Conditions — — 15 pF — — 50 pF 1M VMIN 10M — — 6. † Data in “Typ” column is at 5.4 PIC16F83/84 DC CHARACTERISTICS: PIC16F84. PIC16F83 (Commercial.

agelectronica.agelectronica. TppS T F Frequency Lowercase symbols (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time io I/O port inp INT pin mc MCLR Uppercase symbols and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low T Time os.9 VDD (High) 0.3 VDD XTAL 0. www.15 VDD RC (Low) OSC1 Measurement Points 0.agelectronica.com www.www.com DS30430C-page 79 www.  1998 Microchip Technology Inc.agelectronica.7 VDD XTAL 0.com .com PIC16F8X PIC16F83/84 TABLE 10-2 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1.1 VDD (Low) I/O Port Measurement Points FIGURE 10-2: LOAD CONDITIONS Load Condition 1 Load Condition 2 VDD/2 RL CL Pin CL Pin VSS VSS RL = CL = 464Ω 50 pF for all pins except OSC2. 15 pF for OSC2 output. TppS2ppS 2.osc ost pwrt rbt t0 wdt OSC1 oscillator start-up timer power-up timer RBx pins T0CKI watchdog timer P R V Z Period Rise Valid High Impedance FIGURE 10-1: PARAMETER MEASUREMENT INFORMATION All timings are measure between high and low measurement points as indicated in the figures below. 0.8 VDD RC (High) 0.

com . All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code.1 1.com www.0V. 25°C unless otherwise stated.com  1998 Microchip Technology Inc. RC osc HS osc LP osc PIC16LF8X-04 PIC16F8X-04 PIC16F8X-10 PIC16LF8X-04 Oscillator Frequency(1) DC DC 0.5 PIC16F83/84 Timing Diagrams and Specifications FIGURE 10-3: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 10-3 Parameter No. When an external clock input is used. TosH Instruction Cycle Time(1) Clock in (OSC1) High or Low Time 4 TosR. DS30430C-page 80 www.com PIC16F8X 10. the "Max.0 — — — — — — — — ns ns ns µs XT. All devices are tested to operate at "min.agelectronica.000 1.0 DC — — — — — — 2 4 2 4 10 200 MHz MHz MHz MHz MHz kHz RC osc RC osc XT osc XT osc HS osc LP osc PIC16LF8X-04 PIC16F8X-04 PIC16LF8X-04 PIC16F8X-04 PIC16F8X-10 PIC16LF8X-04 External CLKIN Period(1) 500 250 100 5.0 * 35 * 25 * 50 * 15 * 4/Fosc — — — — — — — DC — — — — — — — µs ns ns µs ns ns ns ns XT osc XT osc LP osc HS osc XT osc LP osc HS osc PIC16LF8X-04 PIC16F8X-04 PIC16LF8X-04 PIC16F8X-10 PIC16F8X-04 PIC16LF8X-04 PIC16F8X-10 2 3 TCY TosL. www.4 60 * 50 * 2.1 0.0 — — — — — — — — 10. RC osc HS osc LP osc PIC16LF8X-04 PIC16F8X-04 PIC16F8X-10 PIC16LF8X-04 Oscillator Period(1) 500 250 500 250 100 5. Data in "Typ" column is at 5.agelectronica. RC osc XT. TosF Clock in (OSC1) Rise or Fall Time Conditions * † These parameters are characterized but no tested. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period." cycle time limit is "DC" (no clock) for all devices.www. These parameters are for design guidance only and are not tested.000 10.000 — ns ns ns ns ns µs RC osc RC osc XT osc XT osc HS osc LP osc PIC16LF8X-04 PIC16F8X-04 PIC16LF8X-04 PIC16F8X-04 PIC16F8X-10 PIC16LF8X-04 0.agelectronica. EXTERNAL CLOCK TIMING REQUIREMENTS Sym FOSC 1 Tosc Characteristic Min Typ† Max Units External CLKIN Frequency(1) DC DC DC DC — — — — 2 4 10 200 MHz MHz MHz kHz XT." values with an external clock applied to the OSC1 pin.agelectronica. RC osc XT.

agelectronica.agelectronica. 10 CLKOUT AND I/O TIMING REQUIREMENTS Sym Characteristic TosH2ckL OSC1↑ to CLKOUT↓ PIC16F8X PIC16LF8X TosH2ckH OSC1↑ to CLKOUT↑ PIC16F8X PIC16LF8X TckR CLKOUT rise time PIC16F8X PIC16LF8X 10A 11 11A 12 12A 13 TckF CLKOUT fall time 13A Min Typ† Max — 15 30 * Units Conditions — 15 120 * ns Note 1 — 15 30 * ns Note 1 — 15 120 * ns Note 1 — 15 30 * ns Note 1 — 15 100 * ns Note 1 ns Note 1 PIC16F8X — 15 30 * ns Note 1 PIC16LF8X — 15 100 * ns Note 1 14 TckL2ioV CLKOUT ↓ to Port out valid — — 0.30TCY + 80 * — — ns Note 1 0* — — ns Note 1 16 TckH2ioI 17 TosH2ioV 18 19 20 TosH2ioI TioV2osH TioR Port in hold after CLKOUT ↑ OSC1↑ (Q1 cycle) to PIC16F8X — — 125 * ns Port out valid PIC16LF8X — — 250 * ns OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold time) PIC16F8X 10 * — — ns PIC16LF8X 10 * — — ns Port input valid to OSC1↑ (I/O in setup time) PIC16F8X -75 * — — ns PIC16LF8X -175 * — — ns Port output rise time 20A 21 TioF Port output fall time 22 Tinp 23 23A Trbp — 10 35 * ns — 10 70 * ns PIC16F8X — 10 35 * ns PIC16LF8X — 10 70 * ns INT pin high PIC16F8X 20 * — — ns or low time PIC16LF8X 55 * — — ns RB7:RB4 change INT PIC16F8X TOSC § — — ns high or low time PIC16LF8X TOSC § — — ns 21A 22A PIC16F8X PIC16LF8X * † These parameters are characterized but not tested.agelectronica.  1998 Microchip Technology Inc. These parameters are for design guidance only and are not tested.com PIC16F8X PIC16F83/84 FIGURE 10-4: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20.com www. 25°C unless otherwise stated.agelectronica.0V.com .www. § By design Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC. Data in "Typ" column is at 5.com DS30430C-page 81 www.5TCY +20 * ns Note 1 15 TioV2ckH Port in valid before PIC16F8X 0. TABLE 10-4 Parameter No. 21 Note: All tests must be done with specified capacitive loads (Figure 10-2) 50 pF on I/O pins and CLKOUT.30TCY + 30 * — — ns Note 1 CLKOUT ↑ PIC16LF8X 0. www.

www.agelectronica.com

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PIC16F8X

PIC16F83/84

FIGURE 10-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING

VDD
MCLR
30
Internal
POR
33
PWRT
Time-out

32

OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET

31

34

34

I/O Pins

TABLE 10-5

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS

Parameter
No.

Sym

Characteristic

30

TmcL

MCLR Pulse Width (low)

31

Twdt

Watchdog Timer Time-out Period
(No Prescaler)

*

32

Tost

33

Tpwrt

34

TIOZ

Min

Typ†

Max

Units

1000 *

ns

2.0V ≤ VDD ≤ 6.0V

7*

18

33 *

ms

VDD = 5.0V

Oscillation Start-up Timer Period
Power-up Timer Period
I/O Hi-impedance from MCLR Low
or reset

1024TOSC

Conditions

ms

TOSC = OSC1 period

28 *

72

132 *

ms

VDD = 5.0V

100 *

ns

These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

DS30430C-page 82

www.agelectronica.com

 1998 Microchip Technology Inc.

www.agelectronica.com

www.agelectronica.com

www.agelectronica.com

PIC16F8X

PIC16F83/84
FIGURE 10-6: TIMER0 CLOCK TIMINGS

RA4/T0CKI

40

41

42

TABLE 10-6
Parameter
No.
40

TIMER0 CLOCK REQUIREMENTS
Sym

Characteristic

Tt0H T0CKI High Pulse Width

No Prescaler
With Prescaler

41

Tt0L T0CKI Low Pulse Width

No Prescaler
With Prescaler

42
*

Tt0P T0CKI Period

Min

Typ† Max Units

Conditions

0.5TCY + 20 *

ns

50 *
30 *



ns
ns

0.5TCY + 20 *

ns

50 *
20 *



ns
ns

2.0V ≤ VDD ≤ 3.0V
3.0V ≤ VDD ≤ 6.0V

TCY + 40 *
N

ns

N = prescale value
(2, 4, ..., 256)

2.0V ≤ VDD ≤ 3.0V
3.0V ≤ VDD ≤ 6.0V

These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

 1998 Microchip Technology Inc.

www.agelectronica.com

DS30430C-page 83

www.agelectronica.com

www.agelectronica.com

PIC16F8X

www.agelectronica.com

PIC16F83/84

NOTES:

DS30430C-page 84

www.agelectronica.com

 1998 Microchip Technology Inc.

www.agelectronica.com

............................................................... † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device...................................± 20 mA Output clamp current..............................................................................................0 PIC16F8X ELECTRICAL CHARACTERISTICS FOR PIC16CR83 AND PIC16CR84 Absolute Maximum Ratings † Ambient temperature under bias................com www...20 mA Maximum current sunk by PORTA ..................agelectronica........... IOK (VO < 0 or VO > VDD) ................................................................... -0........................................................com PIC16CR83/84 11..... a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly to VSS.6V to (VDD + 0......................................................................................... www............................................................................................................ -0...................................... inducing currents greater than 80 mA.. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied...........................................................................................com DS30430C-page 85 www..............................................................com ...............800 mW Maximum current out of VSS pin ................................25 mA Maximum output current sourced by any I/O pin ............................................100 mA Input clamp current.........................................................-55°C to +125°C Storage temperature ...............................∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR pin....................± 20 mA Maximum output current sunk by any I/O pin................................50 mA Maximum current sunk by PORTB............................................... IIK (VI < 0 or VI > VDD).........................................................................3 to +14V Voltage on any pin with respect to VSS (except VDD and MCLR).....6V) Total power dissipation(1) ....................................100 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD ......................................................................................................................................................... Thus................................................agelectronica.......................... -65°C to +150°C Voltage on VDD with respect to VSS ..............................................................agelectronica......................................................... -0.......150 mA Maximum current into VDD pin ......................................................................80 mA Maximum current sourced by PORTA ...................................................agelectronica...........www..............  1998 Microchip Technology Inc........3 to +7..... Exposure to maximum rating conditions for extended periods may affect device reliability................................. may cause latch-up........................................................................................5V Voltage on MCLR with respect to VSS(2) ................150 mA Maximum current sourced by PORTB..........

5V to 5. at 5. but not for MIN/MAX specifications. at 2V WDT dis 200 kHz max. at 5.5V 1. 4.5V 5 µA max.agelectronica.5V IDD: 10 mA max.5V WDT dis Freq: VDD: IDD: IPD: Freq: 4.5V 14 µA max. at 2V WDT dis 2. 4.com PIC16F8X TABLE 11-1 XT HS LP CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) PIC16CR84-04 PIC16CR83-04 OSC RC PIC16CR83/84 VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4.5V 14 µA max. VDD: 4.5V WDT dis IPD: 1.5V to 5.5 mA max. at 5. DS30430C-page 86 www. Do not use in HS mode VDD: IDD: IPD: Freq: 2.com  1998 Microchip Technology Inc. 2. 4. at 4V WDT dis 4.0V 5 µA max.0V 45 µA max.www. at 2V WDT dis 2. VDD: 4.5 mA max. at 32 kHz.0V to 6.0 MHz max.5V PIC16CR84-10 PIC16CR83-10 VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 4. It is recommended that the user select the device type that ensures the specifications required. at 4.6 µA typ. at 5.0 µA typ.5V 1.com www.8 mA typ.5 mA max. at 5.0V 4.0 µA typ. at 4.5V 1.0V 4.0 µA typ.0V to 6. at 5.5V to 5.0 MHz max.com .agelectronica.0V 4. www.0 MHz max.5V IDD: 4. The shaded sections indicate oscillator selections which are tested for functionality.agelectronica.0V WDT dis 200 kHz max. 2.0 MHz max.0 MHz max.5V 5 µA max..0V 4.agelectronica.5V WDT dis 4.5V typ. Freq: 10 MHz max.5V WDT dis 4.0V to 6. Do not use in LP mode PIC16LCR84-04 PIC16LCR83-04 VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: 2.0V to 6.8 mA typ.0 MHz max. IPD: 1.0 µA typ.5 mA max. at 4V WDT dis 4.0 MHz max. at 5. at 5.0V 0. at 3.5V 1.5 mA typ. at 32 kHz.0V to 6. at 5.0V to 6. 2.0V 48 µA typ. at 5.5V to 5.

industrial — D013 5 10 mA — D020 IPD Power-down Current(3) 7.0 MHz.5V (During EEPROM programming) HS OSC CONFIGURATION (PIC16CR84-10) FOSC = 10 MHz.8 7. all I/O pins tristated.com DS30430C-page 87 www. Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C ≤ TA ≤ +70°C (commercial) -40°C ≤ TA ≤ +85°C (industrial) Min Typ† Max Units Conditions 4. WDT enabled. Power-down current is measured with the part in SLEEP mode.5V VDD = 4.www.agelectronica. PIC16CR83 (Commercial. pulled to VDD. These parameters are for design guidance only and are not tested. 4: For RC osc configuration.5* — — 6. www. VDD = 5.5 1.0 MHz. 25˚C unless otherwise stated. Characteristic D001 D001A D002 VDD Supply Voltage VDR D003 VPOR D004 SVDD RAM Data Retention Voltage(1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current(2) IDD D010 D010A PIC16F8X PIC16CR84. Other factors such as I/O pin loading and switching rate.5 — V V V XT. commercial VDD = 4.0V. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave.5V FOSC = 4. and temperature also have an impact on the current consumption.0 5. WDT disabled. industrial VDD = 4.05* — — — — 1. VDD = 5.  1998 Microchip Technology Inc.5 10 V/ms See section on Power-on Reset for details mA mA RC and XT osc configuration(4) FOSC = 4. VDD = 5.0 28 µA — D021 1.agelectronica. 2: The supply current is mainly a function of the operating voltage and frequency. † Data in "Typ" column is at 5.0 4.1 DC CHARACTERISTICS: DC Characteristics Power Supply Pins Sym Parameter No. 3: The power down current in SLEEP mode does not depend on the oscillator type. WDT disabled.3 4. with all I/O pins in hi-impedance state and tied to VDD and VSS. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.0V. T0CKI = VDD.com . MCLR = VDD. from rail to rail. internal code execution pattern. oscillator type.0 16 µA * These parameters are characterized but not tested.0V. current through Rext is not included.0 14 µA — D021A 1. WDT enabled/disabled as specified.agelectronica. RC and LP osc configuration HS osc configuration Device in SLEEP mode — — VSS — V See section on Power-on Reset for details 0.agelectronica.com www.com PIC16CR83/84 11. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm.0V.

0 — V V XT. and temperature also have an impact on the current consumption.2 PIC16CR83/84 DC CHARACTERISTICS: PIC16LCR84. oscillator type. 3: The power down current in SLEEP mode does not depend on the oscillator type.5V (During EEPROM programming) LP osc configuration FOSC = 32 kHz.agelectronica. † Data in "Typ" column is at 5.0V.5V FOSC = 2. from rail to rail. Sym Characteristic 2.4 6. 2: The supply current is mainly a function of the operating voltage and frequency.com www. WDT disabled VDD = 2. internal code execution pattern. DS30430C-page 88 www. The current through the resistor can be estimated by the formula IR = VDD/2Rext (mA) with Rext in kOhm. The test conditions for all IDD measurements in active operation mode are: OSC1=external square wave.3 4 10 mA mA D014 — 15 45 µA D001 D002 VDD VDR D003 VPOR D004 SVDD IDD Supply Voltage RAM Data Retention Voltage(1) VDD start voltage to ensure internal Power-on Reset signal VDD rise rate to ensure internal Power-on Reset signal Supply Current(2) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C ≤ TA ≤ +70°C (commercial) -40°C ≤ TA ≤ +85°C (industrial) Min Typ† Max Units Conditions V/ms See section on Power-on Reset for details RC and XT osc configuration(4) FOSC = 2.agelectronica. current through Rext is not included. PIC16LCR83 (Commercial. pulled to VDD. and LP osc configuration Device in SLEEP mode — VSS — V See section on Power-on Reset for details 0.agelectronica.0 MHz.0V.0 16 µA D021 — 0.www.0V. Other factors such as I/O pin loading and switching rate.agelectronica. WDT disabled. T0CKI = VDD. commercial VDD = 2. Industrial) DC Characteristics Power Supply Pins Parameter No.0 µA D021A — 0.0 µA * These parameters are characterized but not tested.4 5. industrial VDD = 2.0V. WDT enabled/disabled as specified. WDT disabled.0V.0 MHz. These parameters are for design guidance only and are not tested. VDD = 2.com . industrial D020 IPD Power-down Current(3) — 3.0 1. with all I/O pins in hi-impedance state and tied to VDD and VSS. www.com PIC16F8X 11.com  1998 Microchip Technology Inc. VDD = 5. MCLR = VDD. all I/O pins tristated. VDD = 5.05* — — D010 D010A — — 1 7. WDT enabled. RC. 4: For RC osc configuration. Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. Power-down current is measured with the part in SLEEP mode.5* — — 6. 25°C unless otherwise stated.

7 — — V IOH = -3. 3: Negative current is defined as coming out of the pin. The specified levels represent normal operating conditions. VPIN = VSS I/O ports — — ±1 µA Vss ≤ VPIN ≤ VDD. Sym Characteristic Min Typ† Max Units Conditions Input Low Voltage VIL D030 I/O ports with TTL buffer D030A D031 with Schmitt Trigger buffer VSS — 0.1 and Section 11.2. HS and LP modes)(1) Vss — 0. PIC16CR83 (Commercial.com www. Higher leakage current may be measured at different input voltages. These parameters are for design guidance only and are not tested.45VDD — VDD 0.3) D060 IIL Output Low Voltage D080 VOL D083 Output High Voltage D090 VOH D092 * † These parameters are characterized but not tested. 25°C unless otherwise stated. PIC16LCR83 (Commercial. VDD = 4. HS and LP osc configuration I/O ports — — 0. the OSC1 pin is a Schmitt Trigger input. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level.8 V 4.6 V IOL = 1. Data in “Typ” column is at 5.www.agelectronica. VDD = 4.2VDD V D033 OSC1 (XT.com .5V(4) entire range(4) entire range — VDD V D050 VHYS Hysteresis of Schmitt Trigger inputs TBD — — V D070 IPURB PORTB weak pull-up current 50* 250* 400* µA VDD = 5. RA4/T0CKI Vss — 0. OSC1 (RC mode) D043 OSC1 (XT.3 mA.16VDD V entire range(4) entire range VSS — 0.6 V IOL = 8.5V OSC2/CLKOUT — — 0.7 — — V IOH = -1. www. Pin at hi-impedance D061 MCLR.agelectronica.5 V(4) VSS — 0.agelectronica. Note 1: In RC oscillator configuration.com PIC16F8X PIC16CR83/84 11.5V I/O ports(3) VDD-0.5V OSC2/CLKOUT VDD-0. HS and LP modes)(1) 0.85 VDD — VDD V D042 MCLR.0V.48VDD — — VDD VDD with Schmitt Trigger buffer 0. VDD = 4. or chip damage may result.5V Input Leakage Current(2. VDD = 4.0 mA.1VDD V V V Input High Voltage VIH D040 D040A D041 I/O ports — with TTL buffer 2.4 0.3VDD V D034 OSC1 (RC mode) Vss — 0.3 DC CHARACTERISTICS: PIC16CR84. RA4/T0CKI. RA4/T0CKI — — ±5 µA Vss ≤ VPIN ≤ VDD D063 OSC1 — — ±5 µA Vss ≤ VPIN ≤ VDD.5 V ≤ VDD ≤ 5.7 VDD 4.6 mA. 4: The user may choose the better of the two specs. Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C ≤ TA ≤ +70°C (commercial) -40°C ≤ TA ≤ +85°C (industrial) Operating voltage VDD range as described in DC spec Section 11.agelectronica.5 mA.2VDD V D032 MCLR.com DS30430C-page 89 www. Industrial) PIC16LCR84. XT.  1998 Microchip Technology Inc. DC Characteristics All Pins Except Power Supply Pins Parameter No. Do not drive the PIC16CR8X with an external clock while the device is in RC mode.0V.5 V ≤ Vdd ≤ 5.

com www. PIC16CR83 (Commercial. www. Min Typ† Max Units Conditions — — 15 pF — — 50 pF 1M VMIN 10M — — 6.1 and Section 11.com .agelectronica.agelectronica. Industrial) DC Characteristics All Pins Except Power Supply Pins Sym Characteristic D100 COSC2 Capacitive Loading Specs on Output Pins OSC2 pin D101 CIO D120 D121 ED VDRW Parameter No.com PIC16F8X 11.4 PIC16CR83/84 DC CHARACTERISTICS: PIC16CR84. E/W 25°C at 5V V VMIN = Minimum operating voltage ms D122 TDEW Erase/Write cycle time — 10 20* * These parameters are characterized but not tested. HS and LP modes when external clock is used to drive OSC1.0V. PIC16LCR83 (Commercial. Industrial) PIC16LCR84.www.agelectronica. 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.0 In XT. † Data in “Typ” column is at 5.com  1998 Microchip Technology Inc.2.agelectronica. DS30430C-page 90 www. All I/O pins and OSC2 (RC mode) Data EEPROM Memory Endurance VDD for read/write Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C ≤ TA ≤ +70°C (commercial) -40°C ≤ TA ≤ +85°C (industrial) Operating voltage VDD range as described in DC spec Section 11.

3 VDD XTAL 0.15 VDD RC (Low) OSC1 Measurement Points 0.com PIC16F8X PIC16CR83/84 TABLE 11-2 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1.  1998 Microchip Technology Inc.7 VDD XTAL 0.com www.1 VDD (Low) I/O Port Measurement Points FIGURE 11-2: LOAD CONDITIONS Load Condition 1 Load Condition 2 VDD/2 RL CL Pin CL Pin VSS VSS RL = CL = 464Ω 50 pF for all pins except OSC2. www. 0.com . TppS T F Frequency Lowercase symbols (pp) and their meanings: pp 2 to ck CLKOUT cy cycle time io I/O port inp INT pin mc MCLR Uppercase symbols and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low T Time os. TppS2ppS 2.8 VDD RC (High) 0.agelectronica.agelectronica. 15 pF for OSC2 output.com DS30430C-page 91 www.www.9 VDD (High) 0.agelectronica.agelectronica.osc ost pwrt rbt t0 wdt OSC1 oscillator start-up timer power-up timer RBx pins T0CKI watchdog timer P R V Z Period Rise Valid High Impedance FIGURE 11-1: PARAMETER MEASUREMENT INFORMATION All timings are measure between high and low measurement points as indicated in the figures below.

These parameters are for design guidance only and are not tested. EXTERNAL CLOCK TIMING REQUIREMENTS Sym FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) 1 Tosc External CLKIN Period(1) Oscillator Period(1) 2 3 TCY TosL.000 10.agelectronica. RC osc PIC16LCR8X-04 PIC16CR8X-04 DC DC — — 10 200 MHz kHz HS osc LP osc PIC16CR8X-10 PIC16LCR8X-04 DC DC — — 2 4 MHz MHz RC osc RC osc PIC16LCR8X-04 PIC16CR8X-04 0.0 — — 1. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. RC osc XT. DS30430C-page 92 www. TosH Instruction Cycle Time(1) Clock in (OSC1) High or Low Time 4 TosR. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. RC osc XT.agelectronica.5 PIC16CR83/84 Timing Diagrams and Specifications FIGURE 11-3: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 11-3 Parameter No. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. 25°C unless otherwise stated. TosF Clock in (OSC1) Rise or Fall Time Min Typ† Max Units Conditions DC DC — — 2 4 MHz MHz XT.agelectronica. www." values with an external clock applied to the OSC1 pin. All devices are tested to operate at "min.4 60 * 50 * 2.1 — — 2 4 MHz MHz XT osc XT osc PIC16LCR8X-04 PIC16CR8X-04 1.com . the "Max. When an external clock input is used.000 ns ns XT osc XT osc PIC16LCR8X-04 PIC16CR8X-04 100 5. Data in "Typ" column is at 5.000 — ns µs HS osc LP osc PIC16CR8X-10 PIC16LCR8X-04 0.www.1 0.agelectronica.com www.0 — — — — ns µs HS osc LP osc PIC16CR8X-10 PIC16LCR8X-04 500 250 — — — — ns ns RC osc RC osc PIC16LCR8X-04 PIC16CR8X-04 500 250 — — 10.com  1998 Microchip Technology Inc.com PIC16F8X 11.0 DC — — 10 200 MHz kHz HS osc LP osc PIC16CR8X-10 PIC16LCR8X-04 500 250 — — — — ns ns XT." cycle time limit is "DC" (no clock) for all devices. RC osc PIC16LCR8X-04 PIC16CR8X-04 100 5.0V.0 * 4/Fosc — — — DC — — — µs ns ns µs XT osc XT osc LP osc PIC16LCR8X-04 PIC16CR8X-04 PIC16LCR8X-04 35 * 25 * 50 * 15 * — — — — — — — — ns ns ns ns HS osc XT osc LP osc HS osc PIC16CR8X-10 PIC16CR8X-04 PIC16LCR8X-04 PIC16CR8X-10 * † These parameters are characterized but not tested.

21 Note: All tests must be done with specified capacitive loads (Figure 11-2) 50 pF on I/O pins and CLKOUT. Data in "Typ" column is at 5.agelectronica.agelectronica. 25°C unless otherwise stated. 10 CLKOUT AND I/O TIMING REQUIREMENTS Sym Characteristic TosH2ckL OSC1↑ to CLKOUT↓ PIC16CR8X PIC16LCR8X TosH2ckH OSC1↑ to CLKOUT↑ PIC16CR8X PIC16LCR8X TckR CLKOUT rise time PIC16CR8X PIC16LCR8X 10A 11 11A 12 12A 13 TckF CLKOUT fall time 13A Min Typ† Max — 15 30 * Units Conditions — 15 120 * ns Note 1 — 15 30 * ns Note 1 — 15 120 * ns Note 1 — 15 30 * ns Note 1 — 15 100 * ns Note 1 ns Note 1 PIC16CR8X — 15 30 * ns Note 1 PIC16LCR8X — 15 100 * ns Note 1 14 TckL2ioV CLKOUT ↓ to Port out valid — — 0.30TCY + 30 * — — ns Note 1 CLKOUT ↑ PIC16LCR8X 0. § By design Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.com DS30430C-page 93 www. TABLE 11-4 Parameter No.  1998 Microchip Technology Inc.com PIC16F8X PIC16CR83/84 FIGURE 11-4: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20.30TCY + 80 * — — ns Note 1 0* — — ns Note 1 16 TckH2ioI 17 TosH2ioV 18 19 20 TosH2ioI TioV2osH TioR Port in hold after CLKOUT ↑ OSC1↑ (Q1 cycle) to PIC16CR8X — — 125 * ns Port out valid PIC16LCR8X — — 250 * ns OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold time) PIC16CR8X 10 * — — ns PIC16LCR8X 10 * — — ns Port input valid to OSC1↑ (I/O in setup time) PIC16CR8X -75 * — — ns PIC16LCR8X -175 * — — ns Port output rise time PIC16CR8X — 10 35 * ns PIC16LCR8X — 10 70 * ns PIC16CR8X — 10 35 * ns PIC16LCR8X — 10 70 * ns INT pin high PIC16CR8X 20 * — — ns or low time PIC16LCR8X 55 * — — ns RB7:RB4 change INT PIC16CR8X TOSC § — — ns high or low time PIC16LCR8X TOSC § — — ns 20A 21 TioF Port output fall time 21A 22 Tinp 22A 23 23A Trbp * † These parameters are characterized but not tested.www.agelectronica.com www.0V.5TCY +20 * ns Note 1 15 TioV2ckH Port in valid before PIC16CR8X 0. www.com . These parameters are for design guidance only and are not tested.agelectronica.

OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Sym Characteristic 30 TmcL MCLR Pulse Width (low) 31 Twdt Watchdog Timer Time-out Period (No Prescaler) 32 Tost Oscillation Start-up Timer Period 33 Tpwrt Power-up Timer Period 34 TIOZ I/O Hi-impedance from MCLR Low or reset Min Typ† Max Units 1000 * — — ns 2. * † RESET.agelectronica.com .com www.www.agelectronica.0V 1024TOSC Conditions ms TOSC = OSC1 period 28 * 72 132 * ms VDD = 5.0V ≤ VDD ≤ 6. WATCHDOG TIMER. Data in "Typ" column is at 5V. DS30430C-page 94 www. 25°C unless otherwise stated.agelectronica.0V — — 100 * ns These parameters are characterized but not tested. WATCHDOG TIMER.com PIC16F8X PIC16CR83/84 FIGURE 11-5: RESET. www.com  1998 Microchip Technology Inc.agelectronica.0V 7* 18 33 * ms VDD = 5. These parameters are for design guidance only and are not tested. OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins TABLE 11-5 Parameter No.

agelectronica.com www.0V ≤ VDD ≤ 3..agelectronica.  1998 Microchip Technology Inc.0V.com .0V TCY + 40 * N — — ns N = prescale value (2.5TCY + 20 * — — ns 50 * 30 * — — — — ns ns 0. . www.com DS30430C-page 95 www.0V ≤ VDD ≤ 6..0V These parameters are characterized but not tested.5TCY + 20 * — — ns 50 * 20 * — — — — ns ns 2.0V ≤ VDD ≤ 6. 4..0V 3.com PIC16F8X PIC16CR83/84 FIGURE 11-6: TIMER0 CLOCK TIMINGS RA4/T0CKI 40 41 42 TABLE 11-6 Parameter No. 40 TIMER0 CLOCK REQUIREMENTS Sym Tt0H Characteristic T0CKI High Pulse Width Min No Prescaler With Prescaler 41 Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42 * † Tt0P T0CKI Period Typ† Max Units Conditions 0. Data in "Typ" column is at 5. 25°C unless otherwise stated.0V ≤ VDD ≤ 3.0V 3. These parameters are for design guidance only and are not tested.www.agelectronica. 256) 2.agelectronica.

agelectronica. www.com PIC16F8X www.com .agelectronica.com PIC16CR83/84 NOTES: DS30430C-page 96 www.com  1998 Microchip Technology Inc.agelectronica.agelectronica.www.

0 DC & AC CHARACTERISTICS GRAPHS/TABLES The graphs and tables provided in this section are for design guidance and are not tested or guaranteed.www.34 MHz ± 21% 10 k 756 kHz ± 18% 100 k 82.com DS30430C-page 97 www.2 kHz ± 23% * Measured on DIP packages.00 VDD = 5.92 VDD = 3.agelectronica.96 0. This is for information only and devices are guaranteed to operate properly only within the specified range.88 0.com .04 1. FIGURE 12-1: TYPICAL RC OSCILLATOR FREQUENCY vs.. TEMPERATURE FOSC FOSC (25°C) Frequency normalized to +25°C 1. The variation indicated is ±3 standard deviation from average value for full VDD range.66 MHz ± 24% 100 k 311 kHz ± 39% 100 pF 5k 1. The percentage variation indicated here is part-to-part variation due to normal process distribution.61 MHz ± 25% 10 k 2.agelectronica.agelectronica.5 V 0. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. the data presented are outside specified operating range (i. 25°C Part to Part Variation 5k 4. 20 pF  1998 Microchip Technology Inc.e. outside specified VDD range).3σ) respectively.com PIC16F8X 12.8 kHz ± 28% 300 pF 5k 428 kHz ± 13% 10 k 243 kHz ± 13% 100 k 26.20 Rext = 10 kΩ Cext = 100 pF 1.5 V 0.agelectronica.com www.12 1. www. 'Typical' represents the mean of the distribution at 25°C.84 -40 -20 0 20 25 40 60 70 80 85 100 T(°C) TABLE 12-1 RC OSCILLATOR FREQUENCIES* Cext Rext Average Fosc @ 5V. while 'max' or 'min' represents (mean + 3σ) and (mean .08 1. In some graphs or tables.16 1. where σ is standard deviation.

T = 25˚C 5.com www.0 R = 100k 0.agelectronica.0 4.com PIC16F8X FIGURE 12-2: TYPICAL RC OSCILLATOR FREQUENCY vs.www.5 4.5 5.0 1.0 VDD (Volts) DS30430C-page 98 www.5 5.agelectronica.5 2.0 2.0 2. CEXT = 20 PF Measured on DIP Packages.5 4.0 R = 5k 4.5 R = 10k 3.com  1998 Microchip Technology Inc.5 1.com . VDD.agelectronica.0 2. www.5 0.0 Fosc (MHz) 3.5 3.5 6.0 5.agelectronica.0 3.

4 0. CEXT = 300 PF Measured on DIP Packages. www.0  1998 Microchip Technology Inc.0 2.5 4.0 2.0 VDD (Volts) FIGURE 12-4: TYPICAL RC OSCILLATOR FREQUENCY vs.com www.0 4.2 0. VDD.6 0.6 1.0 3.5 5. VDD.0 2. T = 25˚C 0.1 R = 100k 0.0 3.0 4. CEXT = 100 PF Measured on DIP Packages.0 5.5 0. T = 25˚C 1.com PIC16F8X FIGURE 12-3: TYPICAL RC OSCILLATOR FREQUENCY vs.5 3.agelectronica.5 6.agelectronica.0 5.2 R = 100k 0.2 1.agelectronica.6 R = 5k FOSC (MHz) 0.5 4.5 3.3 0.4 Fosc (MHz) 1.4 R = 10k 0.8 R = 5k 1.8 0.5 VDD (Volts) 5.www.com 2.0 DS30430C-page 99 www.agelectronica.5 6.0 R = 10k 0.com .

agelectronica.0 VDD (Volts) 4. www.5 4.agelectronica.90 0.0 2.agelectronica.0 3. VDD 1.5 3.0 5.5 6.5 3.0 1 0 2.com  1998 Microchip Technology Inc.5 6.5 5. WATCHDOG ENABLED 6.80 0.0 5.5 5.0 2.0 3.0 5 4 3 2 2.5 4.www.com PIC16F8X FIGURE 12-5: TYPICAL IPD vs.5 3.0 2. WATCHDOG DISABLED FIGURE 12-6: TYPICAL IPD vs.10 1.70 2.5 5.0 5. DS30430C-page 100 www.0 3.40 VTH (Volts) 1.0 Note: These input pins have TTL input buffers.30 1.0 8 T = 25°C T = 25°C 7 6 IPD (µA) IPD (µA) 4.com .0 VDD (Volts) FIGURE 12-7: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs.0 3.0 2. VDD.5 4.0 1.0 4.00 0.20 °C) +25 ( Typ 1.com www.0 10 9 5.0 VDD (Volts) 0. VDD.0 4.5 6.agelectronica.

8 2. T0CKI AND OSC1 (IN RC MODE) vs.4 2.0 VDD (Volts) Note: This input pin is CMOS input.0 4.www.6 1.com PIC16F8X FIGURE 12-8: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT.agelectronica.0 Note: These input pins have Schmitt Trigger input buffers.5 6.5 6.0 1.0 2.5 3.5 25°C 3.5 4.0 5.0 VIH.5 0.0 0.8 1.0 ) 25°C (+ Typ 1.com DS30430C-page 101 www.  1998 Microchip Technology Inc. VIL (Volts) 3.2 2.5 4.0 VDD (Volts) 4. FIGURE 12-9: VIH.0 4. VDD 3.0 3.4 1. AND LP MODES) vs.0 0.0 2.5 2.0 3.6 VTH (Volts) 2. HS.5 VIL typ +25°C 1.agelectronica. www.2 1.8 2.agelectronica.5 4.5 5. VDD 5.com .agelectronica.0 5. VIL OF MCLR.0 2.5 5.com www.0 2.5 3.0 VIH typ + 2.

www.0V 5.agelectronica.0V 2.www.com www. FREQUENCY (RC MODE @20PF.com .com PIC16F8X FIGURE 12-10: TYPICAL IDD vs.agelectronica.agelectronica.5V 3. 25°C) TYPICAL IDD vs FREQ (RC MODE @20pF) 10000 IDD (uA) 1000 100 6.0V 4.5V 5.5V 2.com  1998 Microchip Technology Inc.agelectronica.5V 4.0V 3.0V 10 100000 1000000 10000000 FREQ (Hz) DS30430C-page 102 www.

0V 100000 1000000 10000000 FREQ (Hz)  1998 Microchip Technology Inc.agelectronica.5V 5.agelectronica.0V 4.www.5V 2.com .agelectronica. www. FREQUENCY (RC MODE @100PF. 25°C) TYPICAL IDD vs FREQ (RC MODE @100 pF) 10000 IDD (uA) 1000 100 10 10000 6.5V 3.com DS30430C-page 103 www.agelectronica.0V 2.0V 3.com PIC16F8X FIGURE 12-11: TYPICAL IDD vs.0V 5.com www.5V 4.

com PIC16F8X FIGURE 12-12: TYPICAL IDD vs.com www. www.com .0V 100 5.agelectronica.5V 2.0V 2.5V 3.5V 4.0V 3.5V 5.www. 25°C) TYPICAL IDD vs FREQ (RC MODE @300pF) 1000 IDD (uA) 6.agelectronica.0V 4.agelectronica.0V 10 10000 100000 1000000 FREQ (Hz) DS30430C-page 104 www. FREQUENCY (RC MODE @300PF.agelectronica.com  1998 Microchip Technology Inc.

0 VDD (Volts) 6.agelectronica.com www.com .0 VDD (Volts)  1998 Microchip Technology Inc.0 3.0 0 2. VDD Typ +25°C 25 Typ +25°C 4000 20 3000 15 2000 10 100 5 2.0 DS30430C-page 105 www. VDD 50 9000 45 8000 40 7000 35 6000 30 5000 gm (µA/V) WDT period (ms) FIGURE 12-13: WDT TIMER TIME-OUT PERIOD vs.0 5.0 5.0 3. www.0 4.agelectronica.com 6.0 4.agelectronica.agelectronica.com PIC16F8X FIGURE 12-14: TRANSCONDUCTANCE (gm) OF HS OSCILLATOR vs.www.

VDD FIGURE 12-16: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs.com .www.com www.0 VDD (Volts)  1998 Microchip Technology Inc.0 4.0 5.0 4.0 DS30430C-page 106 www.com PIC16F8X FIGURE 12-15: TRANSCONDUCTANCE (gm) OF LP OSCILLATOR vs.0 VDD (Volts) 6.0 6. www.0 3.com 3.0 5. VDD 2500 45 40 2000 35 30 25 gm (µA/V) gm (µA/V) 1500 20 Typ +25°C Typ +25°C 1000 15 500 10 5 0 2.agelectronica.agelectronica.0 0 2.agelectronica.agelectronica.

0 VOH (Volts) 0 0.0 VOL (Volts)  1998 Microchip Technology Inc.5 2.0 2.5 3. VDD = 5 V 90 0 80 –5 70 –10 60 –20 Typ +25°C IOL (mA) IOH (mA) –15 Typ +25°C 50 40 –25 30 –30 20 –35 10 –40 1.www.0 0.0 1.com PIC16F8X FIGURE 12-17: IOH vs.5 1.0 1.5 4. VDD = 5 V FIGURE 12-20: IOL vs.agelectronica.5 3.0 VOH (Volts) 0.0 3.0 0.0 1.5 2.agelectronica.com DS30430C-page 107 www.0 2. www.com www.5 3.0 2.5 5.agelectronica. VOL. VOL.0 4.0 VOL (Volts) FIGURE 12-18: IOH vs.5 3.5 1.5 2. VOH.com .5 1. VOH.agelectronica. VDD = 3 V 45 0 40 –5 35 30 –10 IOL (mA) IOH (mA) Typ +25°C –15 25 Typ +25°C 20 15 –20 10 5 –25 0. VDD = 3 V FIGURE 12-19: IOL vs.0 2.5 2.0 0 0.

0 6.0 4.agelectronica.com .8 * All capacitance values are typical at 25°C.0 OSC1/CLKIN 4.5 T0CKI 3.0 5.5 VDD (Volts) Shaded area is beyond recommended range. TABLE 12-2 INPUT CAPACITANCE* Typical Capacitance (pF) Pin Name 18L PDIP 18L SOIC PORTA 5.com  1998 Microchip Technology Inc.agelectronica.5 3. VDD 10 9 8 DMEM Typ.2 2.0 4.3 MCLR 17.agelectronica.com www.3 3.0 17.0 3.www.5 5. DS30430C-page 108 www.5 2.5 OSC2/CLKOUT 4.3 PORTB 5.5 4.0 4. A part to part variation of ±25% (three standard deviations) should be taken into account. www.com PIC16F8X FIGURE 12-21: TYPICAL DATA MEMORY ERASE/WRITE CYCLE TIME VS. E/W Cycle Time (ms) 7 6 5 4 3 2 1 0 1.5 6.0 2.0 3.agelectronica.

week code. www. U.com DS30430C-page 109 www. mask rev# and assembly code. certain price adders apply.  1998 Microchip Technology Inc.S.0 PACKAGING INFORMATION 13. Arizona. thus limiting the number of available characters for customer specific information.com . For OTP marking beyond this.. U. any special marking adders are included in QTP price.agelectronica..com PIC16F8X 13. facility code.agelectronica.agelectronica. For QTP devices. S = Tempe.A.1 Package Marking Information Example 18L PDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX AABBCDE 18L SOIC PIC16F84-04I/P 9632SAW Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE Legend: XX.com www.A. Standard OTP marking consists of Microchip part number. it will be carried over to the next line.X AA BB C D E PIC16F84-04 /SO 9648SAN Microchip part number & customer specific information* Year code (last two digits of calendar year) Week code (week of January 1 is week ‘01’) Facility code of the plant at which wafer is manufactured C = Chandler. year code. Arizona.www. Mask revision number Assembly code of the plant or country of origin in which part was assembled Note: * In the event the full Microchip part number cannot be marked on one line.S.agelectronica. Please check with your Microchip Sales Office..

115 0.94 1.13 0.065 0.076 mm) per side or 0.254 mm) per side or 0.91 2.com www.48 6.79 3.005 0.41 2.255 0.30 3.13 0. Dam-bar protrusions shall not exceed 0.100 0.023 0.270 0.110 0.com  1998 Microchip Technology Inc.35 6.73 5.65 0.060 0.58 1.245 0.43 22.135 0.000 0.006” (0.85 9.00 0.010 0.020” (0.055 0.51 3.” DS30430C-page 110 www. www.250 0. † Dimension “B1” does not include dam-bar protrusions.86 7.015 0.agelectronica.73 22.152 mm) more than dimension “B1.387 15 15 MILLIMETERS NOM MAX 7.54 0.900 0.508 mm) more than dimensions “D” or “E.51 0.890 0.310 0.013 0.018 0.895 0.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions.92 0. Mold flash or protrusions shall not exceed 0.38 2.52 1.010” (0.33 0.005 0.020 0.020 0.87 8.075 0.www.83 5 10 15 5 10 15 MIN * Controlling Parameter.agelectronica.155 0.010 0.46 0.095 0.00 0.84 6.25 0.agelectronica.agelectronica.94 3.265 0.22 6.000 0.125 0.349 5 10 5 10 MIN n p B B1† R c A A1 A2 L D‡ E‡ E1 eB α β MAX 0.18 3.130 0.com PIC16F8X Package Type: K04-007 18-Lead Plastic Dual In-line (P) – 300 mil E D 2 n α 1 E1 A1 A R L c A2 B1 β p B eB Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Molded Package Width Radius to Radius Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom INCHES* NOM 0.300 18 0.62 18 2.155 0.com .230 0.40 1.61 22.25 0.86 6.003” (0.

com www.23 0.01 10.58 7.73 11.51 10.254 mm) per side or 0.005 0.016 0. Mold flash or protrusions shall not exceed 0.020 0.41 4 8 0 0.com L1 A1 DS30430C-page 111 www.64 10.009 0.19 11.010 0.015 0.53 0.22 1.093 0.30 0.www.019 15 15 MILLIMETERS NOM MAX 1.agelectronica.64 2.agelectronica.029 0.099 0.50 1.13 0.012 0.419 0.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions.28 0.36 2.38 0.42 0 12 15 0 12 15 MIN * Controlling Parameter.152 mm) more than dimension “B.25 0. 300 mil E1 p E D 2 B 1 n X 45 ° α L R2 c A R1 β Units Dimension Limits Pitch Number of Pins Overall Pack.73 1.13 0.com PIC16F8X Package Type: K04-051 18-Lead Plastic Small Outline (SO) – Wide.10 0.456 0.407 0.36 0.010” (0.058 0.068 0.050 18 0.508 mm) more than dimensions “D” or “E.74 0.296 0.011 0. Dam-bar protrusions shall not exceed 0.28 0.agelectronica.450 0.51 0.13 0.25 0.021 8 0.292 0. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Chamfer Distance Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A2 INCHES* NOM 0.020 0.005 0.006” (0.33 0.299 0.076 mm) per side or 0.014 0 12 0 12 MIN p n A A1 A2 D‡ E‡ E1 X R1 R2 L φ L1 c B† α β φ MAX 0. www.394 0.003” (0.011 0 4 0.011 0.008 0.005 0.048 0.50 0.462 0.42 7.104 0.agelectronica.com .47 0.27 18 2.”  1998 Microchip Technology Inc.25 0.004 0.010 0.010 0.48 0.27 0.13 0.010 0. † Dimension “B” does not include dam-bar protrusions.020” (0.005 0.43 11.017 0.25 0.59 7.

www.com PIC16F8X NOTES: DS30430C-page 112 www.agelectronica.com .agelectronica. www.agelectronica.agelectronica.com www.com  1998 Microchip Technology Inc.

OPTION. Two separate timers.agelectronica. Instruction word length is increased to 14 bits. are being phased out although they are kept for compatibility with PIC16C5X. 4. The user can program PIC16CXX devices using only five pins: VDD. 14. Data memory paging is redefined slightly. GOTO. T0CKI pin is also a port pin (RA4/T0CKI). 4. and SUBLW. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and the register file (128 bytes now versus 32 bytes before). Remove any program memory page select operations (PA2. 3. PA1 and PA0 bits are removed from the status register and placed in the option register. 5. 10. 3. 15. the Oscillator Start-up Timer (OST) and Power-up Timer (PWRT). Change reset vector to 0000h.agelectronica.com PIC16F8X APPENDIX A: FEATURE IMPROVEMENTS FROM PIC16C5X TO PIC16F8X The following is the list of feature improvements over the PIC16C5X microcontroller family: 1. Reset vector is changed to 0000h. 8.) to make sure page bits are set properly under the new scheme. PA2.agelectronica. Five different reset (and wake-up) types are recognized. Eliminate any data memory page switching. Verify all writes to STATUS. Wake up from SLEEP through interrupt is added. 13. Interrupt capability is added. Revisit any computed jump operations (write to PC or add to PC. Registers are reset differently.FROM PIC16C5X TO PIC16F8X To convert code written for PIC16C5X to PIC16F8X. Stack size is increased to 8 deep. Reset of all registers is revisited. ADDLW. PA1. etc. The STATUS register is modified. RB6 (clock) and RB7 (data in/out). PORTB has weak pull-ups and interrupt on change features. VSS.com APPENDIX B: CODE COMPATIBILITY . RETFIE. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 5. are included for more reliable power-up. and FSR registers since these have changed. OPTION and TRIS registers are made addressable. Two instructions. 11.agelectronica. A PC latch register (PCLATH) is added to handle program memory paging. 7. the user should take the following steps: 1. DS30430C-page 113 www.www. TRIS and OPTION. Four new instructions have been added: RETURN. 2. www. 12. Redefine data variables for reallocation.com www.com . PA0 bits) for CALL. Interrupt vector is at 0004h.  1998 Microchip Technology Inc. VPP. 6. 9. 2. FSR is a full 8-bit register. "In system programming" is made possible.

and resolves the conflict between the OPTION command and OPTION register. An appendix on conversion considerations has been added. DC & AC Characteristics Graphs/Tables section for PIC16F8X devices has been added.com PIC16F8X APPENDIX C: WHAT’S NEW IN THIS DATA SHEET APPENDIX D: WHAT’S CHANGED IN THIS DATA SHEET Here’s what’s new in this data sheet: Here’s what’s changed in this data sheet: 1. Errors have been fixed.com . www. Option register name has been changed from OPTION to OPTION_REG.agelectronica.agelectronica. DS30430C-page 114 www.  1998 Microchip Technology Inc. This is consistant with other data sheets and header files.www. 2.com Errata information has been included. This explains differences for customers wanting to go from PIC16C84 to PIC16F84 or similar device.agelectronica.agelectronica. 2. 4. The appendix containing PIC16/17 microcontrollers has been removed.com www. 3. 1.

WDT disabled) =14µA (PIC16F84) =7µA (PIC16LF84) PORTA and crystal oscillator values less than 500kHz For crystal oscillator configurations operating below 500kHz.0V MCLR pulse width (low) = 1000ns.agelectronica. Development Systems support is available for all of the PIC16X8X devices. These considerations apply to converting from the PIC16C84 to the PIC16F83 (same as PIC16F84 except for program Difference and data RAM memory sizes) and the PIC16CR84 and PIC16CR83 (ROM versions of Flash devices).100kΩ REXT = 5kΩ .100kΩ GIE bit unintentional enable If an interrupt occurs while the Global Interrupt Enable (GIE) bit is being cleared.com . N/A Code Protect 1 CP bit 9 CP bits Recommended value of REXT for RC oscillator circuits REXT = 3kΩ . RAM = 36 bytes RAM = 68 bytes The MCLR pin now has an on-chip filter. MCLR pulse width (low) = 350ns.0V ≤ VDD ≤ 3.agelectronica. www. When either of these bits is set.www. the device may generate a spurious internal Qclock when PORTA<0> switches state. the GIE bit may unintentionally be re-enabled by the user’s Interrupt Service Routine (the RETFIE instruction).agelectronica.0V Some electrical specifications have been improved (see IPD example). 2. the maximum IDD for the device is higher than when both are cleared. 3. Compare the electrical specifications of the two devices to ensure that this will not cause a compatibility issue. PWRTE PWRTE The PIC16F84 (and PIC16CR84) have larger RAM sizes.0V ≤ VDD ≤ 6. N/A  1998 Microchip Technology Inc.0V ≤ VDD ≤ 6. N/A RB0/INT pin TTL TTL/ST* (* This buffer is a Schmitt Trigger input when configured as the external interrupt.PIC16C84 TO PIC16F83/F84 AND PIC16CR83/CR84 Considerations for converting from the PIC16C84 to the PIC16F84 are listed in the table below.agelectronica. WDT disabled) =100µA (PIC16C84) =100µA (PIC16LC84) IPD (max @ 4V. IPD (typ @ 2V) = 26µA IPD (typ @ 2V) < 1µA IPD (max @ 4V.) EEADR<7:6> and IDD It is recommended that the EEADR<7:6> bits be cleared.com www. Ensure that this does not cause an issue with your program. Ensure that the programmer has this bit correctly set before programming. 2. PIC16C84 PIC16F84 The polarity of the PWRTE bit has been reversed.com DS30430C-page 115 www.0V = 150ns. The input signal on the MCLR pin will require a longer low pulse to generate an interrupt.com PIC16F8X APPENDIX E: CONVERSION CONSIDERATIONS .

agelectronica.agelectronica.agelectronica.agelectronica.com  1998 Microchip Technology Inc.com www.www.com .com PIC16F8X NOTES: DS30430C-page 116 www. www.

.................................................................................... 21 I/O Programming Considerations .. 37 A Absolute Maximum Ratings .......................................................................... 7 E CALL ........... 37................................................... 56 BTFSS ......................................................................... 39......................................................................................................................................................... 7 Assembler MPASM Assembler ........................................................ 46 LP ..................................................... 42 Instruction Format .......... 23 TMR0/WDT Prescaler ... 69 Development Tools ................................................................................................................................................................................................................................ 42 Memory Organization Data Memory ............................. 53 Instruction Set ADDLW ...... 42................................................................................agelectronica....... 66 SUBWF .............................................................................agelectronica........................................................................... 65 SLEEP ................ 55 ANDWF .............. 3 FSR .................................................................................................................... 70 O OPCODE .................................................................. 56 BTFSC ............................ 71 Loading of PC .............. 12 Memory Organization . 37.......................................................................................................... 71 MPLAB C ............................. 3 Computed GOTO .......................... 19.............................................. 17................................................................................................................................ 47 On-Chip Reset Circuit ................................................................... 66 SUBLW .... 7 CLKIN .......................................... 39............................................. 73............................................................................. 52 INDF .................................................................................................................... 47 Interrupt on Change Feature ........................... 58 CLRW ............................................. 65 RRF ................................... 41 RA3:RA0 and RA5 Port Pins .......................................................................... 75......... 85 External Power-on Reset Circuit ............................. 58 CLRWDT ............................................... 46 RC .................................. 42.......................................... 9 Code Protection ..9 OSC2 . 42 Fuzzy Logic Dev.............................. 21 RB7:RB4 Port Pins ............................................. 55 ANDLW ........... 53 Summary Table ................. 87............................................. 55 ADDWF ......................................................................................................... 85 ALU ........... 61 IORWF ..com KeeLoq Evaluation and Programming Tools ........... 23 Interrupts .......................................................................................................... 57 CLRF .......................... 37 D DC Characteristics ................................................................................................................................................... 9..................................................................com PIC16F8X INDEX Numerics 8......................... 9 CLKOUT ................................................. 90 Development Support ............................. 69 Digit Carry ............................................................................ 25 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ................................ 18 Configuration Bits ...................... 11 MP-DriveWay™ ........... 40 XT ......................9 Oscillator HS ...... 73.................................................www........... 59 GOTO .......................... 46 C Carry ...................................... 77........................................... 68 XORWF ....... www..................................................... 71 MPLAB Integrated Development Environment Software ......................................Application Code Generator .. 37................................................................................................................................................... 59 DECFSZ .......................................................... 67 TRIS ... 11 Program Memory ............................. 63 OPTION ..................................................................................... 39 DS30430C-page 117 www.... 56 BSF .......................... 53 OPTION .................... 43 K F L Family of Devices PIC16C8X ........................................................................ 55 BCF ...................agelectronica...... upward .................................. System (fuzzyTECH-MP) ............1 Configuration Bits .......................................................................................................................................................................................................................................................................................................................................................................................................................... 57  1998 Microchip Technology Inc...................................... 39 Oscillator Configurations .............. 30 Watchdog Timer ........................................................................................ 54 INT Interrupt .................................com www..................................... 59 DECF ................. 89.................................................................... 41................................. 58 COMF . 78............................................ 60 INCF ............................ 37 OSC1 .............................. 62 NOP .................. 67 SWAPF . 69 In-Circuit Serial Programming .............................. 68 Section ................................................. 48 INTEDG ........... 48 INTCON ........... 63 RETFIE ..................................................................................... 21 RA4 Pin ......................................................................................................................................................... 47 I I/O Ports ...................... 62 MOVWF ..................... 48 OSC selection ................................com .... 16..... 70 B Block Diagram Interrupt Logic ............ 67 XORLW ................................................................................................................................................................. 62 MOVLW ...................................................... 18 G GIE ............................ 7 Architectural Overview ..................................................................................................................... 61 IORLW ............................................... 48 Interrupts Flag ............... 76............................................................. 64 RLF ........... 47............................ 60 INCFSZ ....................... 62 MOVF ..................................................... 47 Electrical Characteristics ...................................................................................................................... 71 M MCLR ................................................................................. 50 Brown-out Protection Circuit ............................................agelectronica..................................................... 88................. 39.................. 52 Compatibility............................................................................. 64 RETURN .................. 63 RETLW ........................

.............. 51 Watchdog Timer (WDT) ....................................................................................... 46 Z Zero bit . 46 S Saving W Register and STATUS in RAM ................................................................................................... 15...... 43 Power-up Timer (PWRT) ................................................................. 18....................agelectronica.......... 42 PCLATH ........................................................................................................................ 69 PICSTART Plus Entry Level Development System ........ 70 PICDEM-3 Low-Cost PIC16CXXX Demo Board ........................................... 42 Period ................... 42 Timer0 Switching Prescaler Assignment ....................................... 37.............................. 21............................................. 42 T time-out .......................................... 41...............agelectronica......................agelectronica.......................... 37..... 18....................... 70 PICDEM-2 Low-Cost PIC16CXX Demo Board ...... 49 SEEVAL Evaluation and Programming System .................................. 12 Reset .... 46 Port RB Interrupt ............................. 42......................................................... 48 PORTA .................................... 70 PICMASTER In-Circuit Emulator ..................................................................................................................... 42 Power-down Mode (SLEEP) ................................................................................. 43 Time-out Sequence ...... 37....................... 31 T0IF ............ 37........ 42 PORTB ............................ 42 X XT ............. 41 Reset on Brown-Out ................................ 18 STATUS .......................................................................... 80................. 42 W W ......... 23............................................................................................................................................................... 46 Time-out Sequence on Power-up ..................................................................................................... 29 PRO MATE II Universal Programmer .................................................... 48 TMR0 with External Clock .... 69 Pinout Descriptions ......... 50 Time-out ........................................................................... 21 TRISB ........................... Program Memory ............. 46 PICDEM-1 Low-Cost PICmicro Demo Board ....................... 41........................com PIC16F8X P Paging.............................................................................www.......... 41.................................................. 43 Power-on Reset (POR) ...................... 37................. 23.................... 71 SLEEP ......... 15......................................com .............. 9 POR ........................... 71 Special Features of the CPU ........................................... 9........... 29 Timing Diagrams Time-out Sequence ........................................................... 37 Special Function Registers .... 7................................................................................ 18 Overflows ........................................ 12 Stack ...................................................................... 44 TO ............ 42 PD ........................................................................................................................... 37..................agelectronica............................. 46 Read-Modify-Write ....................... 15......... 51 Prescaler ....................................... www.............................. 69 Product Identification System .................................................................. 7 R RBIF bit ................. 41................ 92 TRISA ..................................... 23............... 51 Software Simulator (MPLAB-SIM) ............................. 121 Programming Considerations .................. 48 RC Oscillator ........................................... 44 Timing Diagrams and Specifications .......................... 50 WDT ............................... 9..................... 48 Timer0 Module ..... 50 DS30430C-page 118 www...... 43 Oscillator Start-up Timer (OST) .......................................................................... 42................................ 27 TMR0 Interrupt .com www........................... 18 Underflows ... 42 Wake-up from SLEEP . 18 PCL ...................................... 42...........................................................................com  1998 Microchip Technology Inc.............. 25 Register File .............................

the user must have access to the Internet and a web browser. The web site is used by Microchip as a means to make files and information easily available to customers. Application Notes. 980106 The Microchip web site is available by using your favorite Internet browser to attach to: www.S. MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U. Files are also available for FTP download from our FTP site. IBM PC-AT are registered trademarks of International Business Machines Corp.agelectronica. A variety of Microchip specific business information is also available.A. PICSTART. User's Guides.www. including listings of Microchip sales offices.microchip.futureone.agelectronica. PICmicro.com The file transfer site is available by using an FTP service to connect to: ftp://ftp. technical information and more • Listing of seminars and events  1998 Microchip Technology Inc. such as Netscape or Microsoft Explorer.S. FlexROM. and 1-602-786-7302 for the rest of the world. Connecting to the Microchip Internet Web Site Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. To view the site. CompuServe is a registered trademark of CompuServe Incorporated.com www.A. Data Sheets.agelectronica.agelectronica. Development Systems. Plus. Microsoft Windows are registered trademarks of Microsoft Corporation.com Trademarks: The Microchip name. www. fuzzyTECH is a registered trademark of Inform Software Corporation. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products.com/pub/microchip The web site and file transfer site provide a variety of services. PIC. Articles and Sample Programs. logo. and most of Canada. Windows is a trademark and MS-DOS.The Hot Line Numbers are: 1-800-755-2345 for U. All other trademarks mentioned herein are the property of their respective companies. this line provides information on how customers can receive any currently available upgrade kits.com . distributors and factory representatives. Pentium is a trademark of Intel Corporation. IBM. and other countries. Users may download files for the latest Development Tools.com PIC16F8X ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U. DS30430C-page 119 www.S.

and ways in which our documentation can better serve you.com www. If you wish to provide your comments on organization. and silicon products? DS30430C-page 120 www.agelectronica. How would you improve this document? 8. Do you find the organization of this data sheet easy to follow? If not. Is there any incorrect or misleading information (what and where)? 7. please FAX your comments to the Technical Publications Manager at (602) 786-7578.agelectronica. clarity.www. Please list the following information._________ Application (optional): Would you like a reply? Device: PIC16F8X Y N Literature Number: DS30430C Questions: 1. www. What additions to the data sheet do you think would enhance the structure and subject? 5.com PIC16F8X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. What deletions from the data sheet could be made without affecting the overall usefulness? 6. why? 4. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ .com  1998 Microchip Technology Inc._________ FAX: (______) _________ . systems. How would you improve our software.agelectronica.agelectronica. subject matter. What are the best features of this document? 2. and use this outline to provide us with your comments about this Data Sheet. How does this document meet your hardware and software development needs? 3.com .

. Extended VDD range 3: T = in tape and reel . PIC16CR8XT(3) PIC16LCR8X(2). on pricing or delivery.. For latest version information and upgrade kits for Microchip Development Tools. revision of silicon and Data Sheet (include Literature #) you are using. QTP pattern #301. please contact one of the following: 1. 10MHz. SOIC package. e. PART NO. PDIP package.agelectronica. PIC16LCR8XT(3) Frequency Range 04 10 20 = 4 MHz = 10 MHz = 20 MHz Temperature Range b(1) I = 0°C to = -40°C to Package P SO SS = PDIP = SOIC (Gull Wing. 2. SSOP packages only. via your local CompuServe number (CompuServe membership NOT required). www. The Microchip Corporate Literature Center U. The Microchip’s Bulletin Board. PDIP package. Please specify which device.agelectronica. To determine if an errata sheet exists for a particular device.10I/P = ROM program memory. Standard VDD range LCR = ROM Version. PIC16F8XT(3) PIC16LF8X(2). Device Device X -XX Frequency Temperature Range Range /XX XXX Package Pattern PIC16F8X(2). PIC16LF8XAT(3) PIC16CR8X(2).g. normal VDD limits..www. Note 1: b = blank 2: F = Standard VDD range LF = Extended VDD range CR = ROM Version.com DS30430C-page 121 www. please call 1-800-755-2345 or 1-602-786-7302.  1998 Microchip Technology Inc.04I/SO = Industrial temp. 300 mil body) = SSOP Pattern 3-digit Pattern Code for QTP. c) PIC16CR84 . SALES AND SUPPORT Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. Your local Microchip sales office.com www. Extended VDD limits.com PIC16F8X PIC16F8X PRODUCT IDENTIFICATION SYSTEM To order or obtain information.S. Industrial temp.com .SOIC. ROM (blank otherwise) +70°C +85°C (Commercial) (Industrial) Examples: a) PIC16F84 -04/P 301 = Commercial temp.agelectronica. FAX: (602) 786-7277 3. b) PIC16LF84 . PIC16LF8XT(3) PIC16F8XA(2).agelectronica. PIC16F8XAT(3) PIC16LF8XA(2). refer to the factory or the listed sales office.. 4 MHz. normal VDD limits. 200 kHz.

www.com PIC16F8X NOTES: DS30430C-page 122 www.com www.com  1998 Microchip Technology Inc.agelectronica.agelectronica. www.agelectronica.agelectronica.com .

com PIC16F8X NOTES:  1998 Microchip Technology Inc.www.com .agelectronica.com DS30430C-page 123 www. www.com www.agelectronica.agelectronica.agelectronica.

agelectronica. 18201 Von Karman. No licenses are conveyed. under any intellectual property rights. Convent Road Bangalore 560 025.com Microchip Asia Pacific RM 3801B. Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei.com www.agelectronica. All rights reserved. Le Colleoni 1 20041 Agrate Brianza Milan. Legacy. © 1998. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information. implicitly or otherwise. 2077 Yan’an Road West. 14651 Dallas Parkway. France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Müchen.A. CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Toronto Microchip Technology Inc. 500 Sugar Mill Road. Tower Two Metroplaza 223 Hing Fong Road Kwai Fong.T. Suite 200B Atlanta. 2355 West Chandler Blvd. Two Prestige Place. Suite 816 Dallas. 333 Pierce Road. DS30430C-page 124 www. India Liaison Office No. Youngbo Bldg.microchip. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www. and wafer fabrication facilities in January. 150 Motor Parkway. OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 Los Angeles Microchip Technology Inc. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates.C Microchip Technology Inc. R. Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 Shanghai Microchip Technology RM 406 Shanghai Golden Bridge Bldg. Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire. Kangnam-Ku Seoul. Suite 202 Hauppauge. CA 92612 Tel: 714-263-1888 Fax: 714-263-1338 New York Microchip Technology Inc. Suite 180 Itasca.agelectronica. MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Chicago Microchip Technology Inc. Ontario L4V 1W1. Suite 200 Mississauga.. Italy Tel: 39-39-6899939 Fax: 39-39-6899883 Microchip Technology Taiwan Singapore Branch 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850 San Jose Microchip Technology Inc. www. NY 11788 Tel: 516-273-5305 Fax: 516-273-5335 Japan Microchip Technology Intl. USA.com M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Corporate Office Hong Kong Taiwan. design. 1997. Suite 150 Miamisburg. Inc. PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060 Singapore ASIA/PACIFIC (CONTINUED) Arizona Microchip Technology Ltd.com  1998 Microchip Technology Inc. Printed on recycled paper.O.www. Chandler. Canada Tel: 905-405-6279 Fax: 905-405-6253 All rights reserved. Benex S-1 6F 3-18-20. and other countries. Suite 1090 Irvine. in the U. The Microchip logo and name are registered trademarks of Microchip Technology Inc. IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas Microchip Technology Inc. 3 Floor Samsung-Dong. N. All other trademarks mentioned herein are the property of their respective companies. 5925 Airport Road. Serial EEPROMs. Hong Qiao District Shanghai.com . Yokohama-shi Kanagawa 222 Japan Tel: 81-45-471.S. GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Microchip Technology Inc.6166 Fax: 81-45-471-6122 Korea Microchip Technology Korea 168-1. ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 Atlanta India EUROPE Microchip Technology Inc. 3/98 1/13/98 Microchip received ISO 9001 Quality System certification for its worldwide headquarters. India Tel: 91-80-229-0061 Fax: 91-80-229-0062 United Kingdom Boston Microchip Technology Inc. or infringement of patents or other intellectual property rights arising from such use or otherwise. Taiwan. Shinyokohama Kohoku-Ku. England RG41 5TU Tel: 44-1189-21-5858 Fax: 44-1189-21-5835 France Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy. 2107 North First Street. 6. related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO). Our field-programmable PICmicro™ 8-bit MCUs. Suite 590 San Jose. Microchip Technology Incorporated. 5 Mount Royal Avenue Marlborough. TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588 Dayton Microchip Technology Inc.agelectronica.