Interface studies on high-k/GaAs MOS capacitors by deep level transient spectroscopy

Souvik Kundu, Yelagam Anitha, Supratic Chakraborty, and Pallab Banerji

Citation: Journal of Vacuum Science & Technology B 30, 051206 (2012); doi: 10.1116/1.4745882
View online: http://dx.doi.org/10.1116/1.4745882
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Published by the AVS: Science & Technology of Materials, Interfaces, and Processing
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Interface studies on high-k/GaAs MOS capacitors by deep level transient

spectroscopy
Souvik Kundu and Yelagam Anitha
Materials Science Centre, Indian Institute of Technology, Kharagpur 721 302, India

Supratic Chakraborty
Applied Materials Science Division, Saha Institute of Nuclear Physics, 1/AF Saltlake, Sector I,
Kolkata 700 064, India

Pallab Banerjia)
Materials Science Centre, Indian Institute of Technology, Kharagpur 721 302, India

(Received 4 April 2012; accepted 30 July 2012; published 10 August 2012)

An experimental analysis has been performed in high-k/GaAs MOS devices to investigate the slow
and fast interface traps (Dit) using high frequency capacitance-voltage and deep level transient
spectroscopic (DLTS) measurements. Prior to deposition of high-k gate dielectric, an ultrathin
layer of ZnO was deposited on GaAs by metalorganic chemical vapor deposition. The number of
slow interface traps was found to be 2.80  1011 cm2, whereas the fast interface trap density was
measured to be 1.80  1011 eV1 cm2. The activation energy, capture cross section, and
concentration of majority carrier traps were measured to be 0.30 eV, 5.70  1019 cm2, and
4.93  1015 cm3, respectively. Combining conventional DLTS with insufficient-filling, the trap
location was found to be at 0.14 eV. Therefore, the traps are not exactly at the interface of GaAs
and high-k but in the GaAs surfaces very close to the interfaces. According to the trap energy level
position, Dit was found to be 5.3  1011 eV1 cm2. The leakage current is found to reduce in ZnO
passivated devices due to an increase in valance band offset by 0.49 eV. Such an improvement is
C 2012 American
due to a higher surface potential resulting from the wide bandgap of ZnO. V
Vacuum Society. [http://dx.doi.org/10.1116/1.4745882]
I. INTRODUCTION
GaAs is one of the most promising alternative channel
materials in metal-oxide-semiconductor (MOS) devices due
to its higher electron mobility, low power consumption, and
high breakdown field.1 However, direct deposition of high-k
onto GaAs leads to Fermi level pinning and very high density of interface traps (Dit), which degrade the electronic
behavior of GaAs based MOS devices.2 Native oxides on a
GaAs surface, such as Ga-O and As-O, are mainly responsible for Fermi level pinning.3 The Fermi level pinning of
GaAs not only limits the performance but also reduces the
lifetime of the devices. Therefore, these native oxides from
the GaAs/high-k interface must be removed to fabricate stable GaAs based MOS devices. To address the above issue,
recently the present authors have shown that an ultrathin
(1.8 nm) ZnO interface passivation layer (IPL) can suppress
the formation of As-O or Ga-O at the GaAs surfaces, which
reduces surface states density.4 If we consider Si/SiO2 MOS
as a benchmark, achievement of a reduced value of Dit may
be a step forward toward the development of GaAs based
MOS devices. So, the interface study between the dielectric
and the semiconductor is extremely essential for any MOS
devices. Two kinds of traps (slow and fast interface traps)
are present at the interfaces between high-k dielectric and
GaAs. Fast trap states are those that are located exactly at
the dielectric/semiconductor interface and are close to the
a)

Author to whom correspondence should be addressed; electronic mail:

pallab@matsc.iitkgp.ernet.in

051206-1 J. Vac. Sci. Technol. B 30(5), Sep/Oct 2012

Fermi level (EF) and also able to exchange charge in a very

short time. On the other hand, slow trap states are charged and
discharged very slowly. The conventional capacitance-voltage
(C-V) or conductance-voltage (G-V) techniques are not suitable to determine the fast interface traps precisely because of
the wide distribution of response time and very high interface
trap density. A lot of reports are available in the literature on
the characterization of the interface between GaAs and high-k
using x-ray photoelectron spectroscopy (XPS).36 Apart from
the XPS study, deep level transient spectroscopy (DLTS) is
also widely used to study the interfaces.7,8 DLTS has some
edge over the other techniques as it has the ability to identify
the majority/minority traps in MOS devices.9 Several reports
on interface characterizations of Si, InP, and Ge MOS devices
by DLTS have been found in the literature.714 However, few
works have been reported on the properties or the determination of the interface traps in GaAs/oxide interfaces by
DLTS.1517 It is found from the literature that Yamasaki and
Sugano15 reported studies on a GaAs MOS capacitor using
anodized oxide as an insulator and have studied the density
distribution of trap states. They have determined the activation energy of 0.40 eV and the interface trap density was
found to be very high [(13)  1013 cm2 eV1]. Similar
value of the interface trap density (1013 cm2 eV1) has been
reported by Murray et al.16 in their Al/Si3N4/GaAs MOS devices. Such a high interface trap density degrades the electronic
behavior and defeats the idea of GaAs based MOS devices.
Hasegawa and Sawada17 used DLTS to study the anodic
native oxide/GaAs MOS device and their work was aimed at
studying the origin of the interface traps using the interface

2166-2746/2012/30(5)/051206/8/$30.00

C 2012 American Vacuum Society

V

051206-1

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051206-2 Kundu et al.: Interface studies on high-k/GaAs MOS capacitors

state model. Narsale and Arora18 investigated the interface

defects as a function of the crystal orientation in GaAs by
DLTS. However, in all the studies, the authors have neither
used high-k dielectric as an insulating layer nor have they passivated the GaAs surfaces prior to deposition of dielectrics,
which are the essential steps in fabricating high performance
GaAs MOS devices to achieve low Dit. In the present work
we have attempted to study the interfaces of high-k/GaAs
MOS devices by DLTS measurements. The concentration of
traps was evaluated. A small pulse DLTS (SP-DLTS) was
used separately to determine the energies and capture cross
sections of the interface traps.19,20 Conventional DLTS was
used in combination with insufficient -filling DLTS (IFDLTS) to precisely determine the energy level position of
interface traps and the activation energy. In addition, the band
alignments in ZrO2 gate dielectric on passivated and unpassivated p-GaAs substrates were studied by XPS. An effort has
been made to understand the effect of interface trap charges
on the leakage current and its correlation with the valance
band offset which was measured by XPS. Capacitancevoltage characteristics were used to determine the hysteresis
voltage and slow interface traps.
II. EXPERIMENT
p-GaAs (100) wafers with a doping concentration of
1  1016 cm3 were degreased using trichloroethylene, acetone, and methanol for 3 min each, successively. This was
followed by cleaning in a chemical solution of H2O2-NH4OHH2O in a ratio of 1:1:2 to remove native oxide and elemental
As and then rinsed for 3 min in deionized water and dried by
N2 gun. An ultrathin layer (1.8 nm) of ZnO was grown by an
atmospheric pressure metalorganic chemical vapor deposition
reactor on p-GaAs. Diethylzinc and tertiary butanol were used
as the Zn and O precursors, respectively. Nitrogen (N2) was
used as the carrier gas and the growth was carried out at
300  C. The high-k gate dielectric ZrO2 was used for the present study, the details of which were discussed elsewhere.4 The
thickness of ZrO2 high-k was measured by both an ellipsometer and a cross sectional high resolution transmission electron
microscope and the value was found to be 9.5 nm. The Al gate
electrode with an area of 1.96  103 cm2, and low resistance
Ohmic contact on the backside with Pd-Ag, were formed by
thermal evaporation. It was followed by annealing at 300  C
for 3 min in argon ambience. The C-V and current densityvoltage (J-V) characteristics of Al/high-k/ZnO/p-GaAs MOS
devices were recorded using an Agilent E4980 A LCR meter
and a Keithley 2400 source meter, respectively. XPS was used
to analyze the band alignments of passivated and unpassivated
GaAs based MOS devices. DLTS studies were performed at
temperatures ranging from 150350 K by a Boonton 7200 capacitance meter at 100 kHz frequency. The capacitance transients were digitally stored with an interval from 1150 ms. The
characterization rate window was taken as t2/t1 2.

051206-2

FIG. 1. (Color online) Voltage-time (V-t) and capacitance-time (C-t)

diagrams. VQ is the quiescent voltage and VP is the majority carrier pulse
voltage.

measurements were done as a function of temperature in a

liquid nitrogen cryostat to study the interface traps in GaAs
MOS devices. Figure 1(a) shows the situation of applied quiescent bias and pulse bias whereas the corresponding capacitance transient is shown in Fig. 1(b). Figures 1(a) and 1(b)
illustrate the concept of majority carrier DLTS. At the quiescent voltage (VQ) the most band bending occurs and a lot of
bulk traps are empty and when the pulse voltage (VP) is
applied bulk traps are rapidly filled by means of capture.
Furthermore, when the voltage is switched back to the quiescent voltage the carriers in the bulk traps are slowly emitted
to the majority carrier band. The situation is more elaborated
in Fig. 2. As the temperature increases the time constant
becomes shorter; the charge decays exponentially at a faster
rate and the difference in capacitance between t1 and t2 will
show a maximum. The minority carriers in the inversion
layer induce the charging and discharging of minority traps
at the interface. A small VQ of 1 V is applied to the MOS
samples to keep the substrates operating in a depletion mode

III. THEORY
DLTS has been used to investigate the interface traps in
ultrathin ZnO-passivated ZrO2/GaAs MOS devices. These

FIG. 2. (Color online) Energy band diagrams of Al/ZrO2/p-GaAs MOS devices (a) before, (b) on, and (c) after majority carrier pulse.

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051206-3 Kundu et al.: Interface studies on high-k/GaAs MOS capacitors

in order to prevent disturbances of the minority carriers in

the inversion layer [Fig. 2(a)]. Then the samples are initially
biased into an accumulation region by applying a VP of
2.5 V [Fig. 2(b)]. The deep traps with energy ET above
Fermi level will be filled with majority holes and accumulate
at the interface of high-k and GaAs. After removing the voltage pulse, the deep traps are restored to their initial potential
and emit holes to valence band with some emission rate (eP)
[Fig. 2(c)].
A. Calculation of activation energy and capture cross
section of traps

The hole emission rate is given by21



ET  EV
;
ep rp Vth Nv exp 
kT

(1)

where rP is the hole capture cross section, Vth is the thermal

velocity, NV is the effective density of states, k is the Boltzmann constant, and T is the temperature in Kelvin.
The effective density of states and thermal velocity can
be written as22
r 



2pm kT 3=2
2kT
2kT 1=2
Nv 2
and Vth
;

h2
pm
pm

051206-3

Again the hole emission rate eP can be written as7

ep lnt2 =t1 =t2  t1 , where t1 and t2 are the chosen sampling times. This expression for ep is valid only at the DLTS
peak which is defined by the rate windows t1 and t2 in DLTS
measurements.
Therefore from Eq. (5) we can get


ep
DE

r
l
exp

T
T2
kT


e 
DE
p
:
(7)
) ln 2 lnrT :l:
T
kT
So it is found that by using Eq. (7) we can easily determine rT
and DE from the Arrhenius plot of lnep =T 2 versus 1000/T.
The interface trap density (Dit) can be expressed as23
Dit

eGaAs COX NA DC
;
CO 3 kT lnt2 =t1

(8)

where eGaAs is the permittivity of GaAs, COX is the accumulation capacitance, NA is the acceptor doping concentration, DC
is the correlation signal or [C(t1)  C(t2)], in which C(t) is the
capacitance transient and CO is the depletion capacitance.

(2)
B. Calculation of the trap energy level position

where m* is the hole effective mass and h is the Plancks

constant.
So,
Nv Vth 22pm kT=h2 3=2  2kT=pm 1=2 l  T 2 ,
where l is a constant.
Therefore, by putting the value of Nv Vth , Eq. (1) can be
modified as


ET  EV
2
:
(3)
ep rp lT exp 
KT

In GaAs MOS devices, the holes will be captured by traps

when the device is fed from a positive bias to a negative
bias. However, the traps may not be filled completely due to
the short pulse period, and then we can assume few traps are
filled. Therefore, the density of filling traps (dit) and the
pulse time (tP) can be written as24



tP
;
(9)
dit Dit 1  exp 
sc

The hole capture cross section (rP) can be written as21,23



EA
;
(4)
rp rT exp 
KT

where sc 1=rP Vth p is the capture time constant and p is

the density of holes in valence band. From Eq. (8) it is
observed that Dit is proportional to correlation signal DC;
therefore, following Eq. (9), the relation for DC can also be
expressed as24



tP
;
(10)
DCmax tP DCmax tLP 1  exp 
sc

where rT and EA are the capture cross sections of traps and

activation energy of majority carriers, respectively. For a
system such as ZrO2/ZnO/p-GaAs, due to the presence of
lattice relaxation we can invoke this thermally activated capture cross-section for further analysis of the interface states.
From Eqs. (3) and (4) we can write





EA
ET  EV
2
 l  T  exp 
ep rT exp 
kT
kT


DE
) ep rT lT 2 exp 
;
kT

(5)

where DE is the activation energy of capture cross sections

and can be expressed as
DE ET  EV EA :

(6)

where DCmax(tP) and DCmax(tLP) are the maximum DLTS

signals. Both are the functions of pulse time, the latter being
long pulse (tLP), i.e., by that time traps are completely filled.
Equation (10) can be rewritten as


DCmax tP
t
P:
(11)
ln 1 
sc
DCmax tLP
Thus if we plot ln1  DCmax tP =DCmax tLP  as a function
of pulse time (tP), then one can easily determine sc from its
slope.
The capture cross section for majority carriers can be
determined from the following relation:

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051206-4 Kundu et al.: Interface studies on high-k/GaAs MOS capacitors

rp

1
:
sC vth p

051206-4

(12)

If we put the value of rP into Eq. (4), the activation energy

of majority carriers can be obtained and similarly from
Eq. (6), the energy level positions of the traps (ET  EV) can
be determined.
IV. RESULTS AND DISCUSSION
A higher leakage current density is observed in unpassivated samples (Fig. 3) possibly due to defects or a high value
of Dit. These defects build up over time and finally the oxide
breaks down. The leakage current is found to have been
reduced by 2 orders of magnitude (at 1 V) with an ultrathin
passivation layer of ZnO on GaAs. The IPL in the MOS capacitor is essential to minimize leakage current since its
properties determine how much charge leaks into the channel from the gate as well as how much charge is accumulated
in the channel in response to the applied gate voltage. ZnO is
a wide bandgap material compared to GaAs and it acts as a
potential barrier and repels electrons and holes, both the carriers away from the GaAs surface (the situation is shown in
Fig. 4). Therefore it reduces recombination centers and as a
result a reduced value of leakage current is observed in
ultrathin ZnO passivated GaAs MOS devices. Figures 5(a)
and 5(b) show, respectively, the valence band alignment in
ZrO2/GaAs without and with a ZnO ultrathin passivation
layer. The valence band edge of ZrO2 films on passivated
and ultrathin ZnO passivated GaAs were determined to be
2.96 and 3.45 eV, respectively. Therefore, the effective valence band offset DEV in unpassivated ZrO2/GaAs was found
to be 2.66 eV [from Fig. 5(a)], whereas that for ZnO passivated ZrO2/GaAs was found to be 3.15 eV [from Fig. 5(b)],
i.e., an increase by 0.49 eV. There should not be any straininduced field in passivated GaAs surfaces due to the pseudomorphic ultrathin layer of ZnO onto GaAs. However, the
depletion layer induced field in p-GaAs/n-ZnO shifts DEV in
ZnO passivated ZrO2/GaAs. This increase in DEV in ZnO
passivated samples explains the decrease in leakage current
as was noted earlier. The obtained value of DEV in the pres-

FIG. 3. (Color online) Current density-voltage characteristics in ultrathin

ZnO passivated and unpassivated Al/ZrO2/p-GaAs MOS devices.

FIG. 4. (Color online) Potential barrier formation of ZnO onto GaAs and
repelling of the carriers away from the GaAs surfaces.

ent study is found to be inconsistent with the available literature data.5,25 The increase in DEV is due to the presence of a
ZnO ultrathin passivation layer which fully suppresses the
As-O formation at the interface between high-k and GaAs.
Subsequently, the conduction band offset DEC has been
obtained from the relation DECHighk=GaAs Eg;Highk
Eg;GaAs  DEV , where Eg is the bandgap. The value of DEC
in ZrO2/GaAs and ZrO2/ZnO/GaAs was calculated to be
1.59 and 1.1 eV, respectively. These values are found to
match well with the earlier reported results in ZrO2/GaAs
samples.5,25
Figure 6 shows the high frequency C-V characteristics of
ultrathin ZnO passivated Al/ZrO2/p-GaAs MOS devices.
The gate voltage was swept from 2.5 to 2 V and then again
back to 2.5 V. The memory window, i.e., the flatband voltage (VFB) difference (between the VFB of the forward curve
and that of the backward curve) measures the hysteresis voltage. The hysteresis was caused by charge trapping (slow
interface states) at the interface. The hysteresis voltage
(DVH) in ZnO passivated GaAs MOS devices was found to
be 0.13 V. The hysteresis in ZrO2/ZnO/p-GaAs stacks is

FIG. 5. (Color online) Valence-band spectra of GaAs substrate and ZrO2

films (a) without and (b) with ZnO interfacial passivation layer.

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051206-5 Kundu et al.: Interface studies on high-k/GaAs MOS capacitors

051206-5

where q is the electronic charge.

The slow interface traps will screen some of the charges
on the gate electrode and shift the threshold voltage. It can
also interact with carriers in the channel through Coulombic
forces and bring down the carrier mobility. For these reasons, charges at the interface must be minimized. However,
in our devices the densities of slow interface traps were
determined as 2.80  1011 cm2, quite a low value.
Figure 7 shows the conventional DLTS spectra of the
GaAs MOS devices with t1/t2 1/2, 2/4, 3/6, and 4/8. We
have fixed t2/t1, while t1 and t2 were varied to avoid the
change in both size and shape of the peaks. Therefore, the
peaks shift with temperature without any change in the shape

of the curve making the location of the peak easier. The

applied quiescent voltage and pulse voltage for the DLTS
measurement were taken as 1.0 and 2.5 V, respectively.
From Fig. 7 it is observed that the peak height is increasing
with temperature and it is mainly due to the electron-capture
process.7 When the GaAs MOS device is switched from
accumulation to inversion, the electron capture process is
dominant. However, in the low temperature, the process gets
slower and does not contribute to the DLTS signal.7 The
DLTS signal is caused by the majority carriers and by using
Eq. (7), the activation energy of majority carriers and capture
cross section were determined by the slope and intercept of
Arrhenius plot (as shown in Fig. 8) and the values were
found to be 0.30 eV and 5.70  1019 cm2, respectively. It
may be mentioned here that the capture cross section in the
Si/SiO2 system is in the range of 10121014 cm2. Thus,
the small value of capture cross section (1019) obtained in
the present study is due to the ultrathin ZnO passivation
layer and it indicates that the ZrO2/GaAs interface may have
a lower chance of charge collision than the SiO2/Si interface.
The activation energy obtained in the present investigation is
much lower compared to earlier reports on GaAs and InP
based MOS devices.9,12,13,16 Jeon et al.7 reported the activation energy of 0.27 eV for Si/SiO2 MOS devices, whereas
Zhan et al.24 studied the interface characteristics in HfAlO/
Si MOS devices and they determined the activation energy
of 0.33 eV. On the other hand, Li et al.29 investigated the Si/
ZrO2 MOS devices and determined the activation energy
0.30 eV. So, the value of activation energy, which was determined in the present study, is consistent with those for Si/
SiO2 or Si/high-k MOS devices. This low value of activation
energy can be attributed to a small number of defects and
low interface traps in ZnO passivated GaAs based MOS
capacitors, and this is due to the suppression of As-O and
Ga-O on the GaAs surfaces. This was also confirmed by
XPS studies.4 Thus ultrathin ZnO IPL reduces the surface
states density in GaAs MOS devices. The interface trap density (Dit) can be calculated using Eq. (8) and it was found to
be 1.80  1011 eV1 cm2, which is quite a low value. This
value of Dit is observed to be inconsistent with the value

FIG. 7. (Color online) DLTS spectra of GaAs MOS devices when t1/t2 1/2,
2/4, 3/6, and 4/8.

FIG. 8. (Color online) Arrhenius plot (obtained from DLTS spectra) of GaAs
MOS devices.

FIG. 6. (Color online) Capacitancevoltage characteristics in ultrathin ZnO

passivated Al/ZrO2/p-GaAs MOS devices.

found to be lower compared to those reported earlier with

other IPL deposited between high-k and GaAs.2,5,2628 This
low hysteresis voltage in ZnO passivated GaAs MOS devices indicates a low density of defects contributing to charge
trapping in the IPL and ZrO2. The number of slow interface
traps (NSIT) can be calculated using the following relation:
NSIT

COX  DVH
;
q

(13)

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051206-6 Kundu et al.: Interface studies on high-k/GaAs MOS capacitors

051206-6

(2.5  1011 eV1 cm2) obtained earlier by a conduction

technique in similar devices.4 This low value of Dit also
leads to the low value of hysteresis voltage.
The concentration of deep traps (Ntrap) in ultrathin ZnO
passivated Al/ZrO2/GaAs MOS devices can be determined
by the following relation:2931
Ntrap 2DCt

;
NA
CO

(14)

where NA is the substrate doping concentration. Figure 9

shows the Ntrap/NA plot as a function of temperature under
different gate bias voltages. The concentration of traps is a
temperature activated process and it increases with temperature. However, as the temperature increases the time constant becomes shorter and it decays exponentially at a faster
rate. The peak shows the maximum concentration of traps at
a particular temperature between t1 and t2. The Ntrap/NA peak
is also increasing with the increase in gate voltage (Vg); it
may be due to the nonuniform spatial distribution of deep
traps. The deep traps concentration was determined to be
4.93  1015 cm3. Figure 10 shows the plot of the DLTS signal as a function of temperature with different gate voltage
(11.8 V). From Fig. 10 it is seen that the DLTS signal peak
is increasing (S1, S2, S3, and S4) with decreasing gate voltage (VG). The variation of the DLTS signal with gate voltage
is due to the increase in the difference between EF and EC
with decreasing VG.7 An SP-DLTS method was used to separately determine the capture cross sections of the interface
traps. The capture cross sections were found to be
5.70  1019, 4.83  1020, 5.70  1021, and 5.70  1022
cm2 at a given VG of 1, 1.25, 1.50, and 1.80 V, respectively.
The hole emission process is mainly responsible for the SPDLTS signal (ISP-DLTS). This is because the interface traps in
the lower energy from EF by an interval of 3 kT would participate in the emission process.7,19 At high temperature,
the normal DLTS signal (IDLTS) was very high compared to
ISP-DLTS (ISP-DLTS > 4). Therefore, the electron capture process is mainly responsible for the high value of a normal
DLTS signal.

FIG. 9. (Color online) Ntrap/NA plot as a function of temperature under different gate bias voltages.

FIG. 10. (Color online) Variation of DLTS signals as a function of temperature under different gate bias voltages.

To determine the energy level position of traps, the

IF-DLTS method was adopted. Figure 11 shows the variation
of ln1  DCmax tP =DCmax tLP  with tP. The capture time
constant, capture cross sections for majority carriers, and the
active energy of capture cross sections were found to be
0.84 lS, 6.6  1022 cm2, and 0.17 eV, respectively. Therefore,
the energy level position of traps was determined by Eq. (6)
and the value was found to be 0.14 eV. Figure 12 shows the
variation of Dit with ET  EV. According to the trap energy
position, Dit was found to be 5.3  1011 eV1 cm2, whereas
the minimum Dit was found to be 1.5  1011 eV1 cm2.
These values of Dit are also consistent with the value of Dit
obtained by the conductance and conventional DLTS technique, and it confirms the validity of conventional DLTS
results. The value of Dit obtained by the DLTS technique is
slightly different than the value obtained by the conductance
technique. The difference is due to the surface potential fluctuation, as DLTS is independent of surface potential. On the
other hand, the conductance technique is influenced by the
surface potential.

FIG. 11. (Color online) IF-DLTS spectra of GaAs MOS devices as a function
of pulse time tP.

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051206-7 Kundu et al.: Interface studies on high-k/GaAs MOS capacitors

051206-7

states at the GaAs surfaces close to the band edges are

caused by As or Ga dangling bonds which are present at
the GaAs surfaces, not exactly at the interface of GaAs
and high-k. According to the trap energy level position,
Dit was found to be 5.3  1011 eV1 cm2, whereas the
minimum Dit was found to be 1.5  1011 eV1 cm2.

FIG. 12. (Color online) Variations of Dit as a function of (ET  EV) in ZnO
passivated Al/ZrO2/p-GaAs MOS devices.

Thus, we have shown that DLTS is a powerful technique

to characterize the interface between GaAs and high-k with
the presence of IPL. The obtained Dit was found to be very
low by DLTS measurement which is consistent with the
value obtained by the conductance technique. Thus, the validity of DLTS to examine the trap properties in the high-k/
GaAs interfaces was confirmed. Therefore, the improved
capacitance-voltage characteristics with low interface trap
density, low hysteresis, and large DEV make the ZrO2/ZnO/
p-GaAs gate stack a potential candidate for future GaAsbased MOSFET devices.

V. CONCLUSION
C-V measurement was adopted in the present study to
determine the slow interface traps and hysteresis voltage in
ZnO passivated Al/ZrO2/p-GaAs MOS devices. XPS and
DLTS have been applied to analyze the band alignments and
to determine the trap states in the interface between GaAs
and high-k. The main conclusions are listed below.
(1) It has been demonstrated that the insertion of an ultrathin
(1.8 nm) ZnO IPL between a ZrO2 and a p-GaAs substrate improves interface quality. As shown by C-V analysis, low slow interface traps and low hysteresis voltage
have been found. It is also found that the band alignments depend on the interface passivation layer. The
effective valence-band offset in ZrO2/p-GaAs and in
ZrO2/ZnO/p-GaAs were 2.66 and 3.15 eV, respectively.
Therefore, the leakage current is found to have been
reduced by 2 orders of magnitude (at 1 V) with an
ultrathin passivation layer of ZnO on GaAs.
(2) The hole emission from the ZrO2/ZnO/p-GaAs interface
was detected by DLTS. The active energy, capture cross
sections, interface trap density, and concentration of
interface traps were determined from the DLTS spectra.
Dit was found to be 1.80  1011 eV1 cm2. This
value of Dit is consistent with the value of Dit
(2.5  1011 eV1 cm2) obtained by a conduction technique in ZnO passivated GaAs MOS devices. However,
the value of Dit obtained by the DLTS technique is
slightly different than the value obtained by the conductance technique. The different value of Dit is due to the
influence of surface potential fluctuation in the conductance technique, whereas DLTS is independent of such
potential.
(3) SP-DLTS was adopted to separately determine the capture cross sections of interface traps, whereas the IFDLTS was adopted to determine the exact trap energy
level in ZnO passivated Al/ZrO2/p-GaAs MOS devices
and it was found to be EV 0.14 eV. It is well known
that the traps are present in the GaAs bandgap (01 V
range) and sometimes at the surfaces.32,33 These trapping

ACKNOWLEDGMENTS
The authors acknowledge the help of T. Shripathi in conducting XPS measurements and N. Basu for DLTS studies.
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