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The primary objective is to give you a quick,
hands-on tour of the synthesis process.
Upon completion of this exercise, you will be
able to describe the 4 basic steps involved in
the synthesis process. You will gain experience
in navigating through a designs hierarchy
using Design Analyzer, the graphical interface
to Design Compiler.
This overview contains many forward
references; dont dwell on the details now,
just proceed through the exercise. This early
exposure is intended to pique your interest and
aid your understanding of these concepts when
you encounter them again (in much greater
detail) in the following lectures and labs.

30 min

UNIT

Unit 1

Chip Synthesis Using Synopsys Design Compiler: The Big Picture


31833-000-S35

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In the Unit 1 lecture, the process of synthesis is described as translation plus optimization plus
mapping.
In terms of the Synopsys tools, translation is performed by the analyze plus elaborate command
sequence. Optimization and mapping are performed by the compile command. This process is
illustrated in the figure below. (Refer to this figure as you run the step-by-step instructions.)
GTECH

target_library

gtech.db

tc6a.db

my_chip.v(hd)
HDL source

DC_MEMORY

read
analyze/
elaborate

DC_MEMORY

compile
Y=A+B
MY_CHIP

MY_CHIP
write

write

unmapped

read

include

scripts

my_chip.db
constraints.scr

TRANSLATION

mapped
my_chip.db
my_chip.edif

OPTIMIZATION + MAPPING

Preliminary Definitions
analyze reads your (V)HDL files, performs syntax and synthesis-policy checks, then writes
intermediate files to the directory specified as your design_library.
elaborate reads the intermediate files from your design library and builds the design using
generic components.
constrain is not a DC command, but a series of steps you perform to tell Design Compiler what
your timing and area requirements are.
compile optimizes a design and maps it to real gates from your target_library, producing a circuit
that meets your constraints. The unmapped design in DC memory is overwritten by the new,
mapped design.

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Unit 1 Lab Exercise

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8 Log in to the workstation using the appropriate UserID and
password.

8 Change directories to the project directory Lab_1:


UNIX> cd Lab_1
UNIX> ls -a
This is your top-level directory for the Lab_1 project; notice the file called
.synopsys_dc.setup and the various subdirectories. The scripts you will be
executing in this exercise are stored in the scripts subdirectory.

8 Invoke Design Analyzer from the UNIX prompt:


UNIX> design_analyzer &

8 Open the Design Analyzer command window by clicking the


mouse through the following menu sequence:

Setup

Command Window

The command window enables you to monitor the commands being


executed and any messages DC returns.
Resize and relocate the windows so that the Synopsys Design Analyzer
window covers the top half of your workstation screen.
Resize and move the Command Window covers the next quarter of screen
below it.

8 analyze the file my_chip.vhd by clicking the mouse through the


following menu sequence:
Setup Execute Script scripts/
1_Analyze_my_chip.scr OK

Wait for the word Done to appear in the bottom left corner of the Design
Analyzer window, and then look for the return code 1 (one) in the
command window. These indicate that analyze has completed
successfully.

8 elaborate the design MY_CHIP_RTL by clicking the mouse through

Synopsys Chip Synthesis Lab Guide

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the following menu sequence:

Setup

Execute Script

2_Elaborate_my_chip.scr

OK

You will see an equation icon for MY_CHIP in the Design Analyzer
window.

Y=A+B
MY_CHIP

The design MY_CHIP is now in Design Compiler memory, represented


internally in Boolean format, and schematically in terms of GTECH
components.

8 Push into the Symbol View by double-clicking the mouse on the


equation icon.
You will see a block with input and output ports attached to it. This is
referred to as the symbol view of the design, as indicated in the lower right
corner of the Design Analyzer Window. The symbol view shows the
block diagram of the design.

8 Push into the Schematic View by double-clicking the mouse on


the block in the Symbol View.
Notice that Schematic View is now indicated in the lower right corner of
the Design Analyzer Window
You will see the structure of your design represented in terms of generic
technology-independent components, located in your Synopsys GTECH
library.
Is this structure similar to what you expected from the (V)HDL code?

8 Constrain the design by clicking the mouse through the following


menu sequence:

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Unit 1 Lab Exercise

Setup

Execute Script

3_Constrain_my_chip.scr

OK

You will notice that a red square wave symbol has appeared above the
Clock_In port (the top left port on the design). The script file has declared
that it will be treated as a clock with period of 100ns (10 MHz). Other
constraints (operating conditions, input delays, etc) have also been applied.
You will learn how to view and change these constraints soon

8 Compile the design by clicking the mouse through the following


menu sequence:

Setup

Execute Script

4_Compile_my_chip.scr

OK

You now see a schematic of your design represented in terms real of


components (cells) from the target technology library.
Does this look like a solution you expected?

8 Save the design by clicking the mouse through the following menu
sequence:

Setup

OK

Execute Script

5_Save_mapped_chip_as_DB.scr

This script saves your design in Synopsys internal (db) format. The name
of the file is my_chip.db. It is saved in the current subdirectory.

8 Run the design report by clicking the mouse through the following
menu sequence:

Setup

Execute Script

6_Report_my_chip.scr

OK

This script writes two new reports to the current directory. You could view
these files from UNIX, but everything contained in them just scrolled by in
Design Analyzers command window.
Look at the last few lines in the command window.
Does the report indicate that the constraints were met or violated?
(Look for the word MET or the word VIOLATED)

Synopsys Chip Synthesis Lab Guide

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Dont worry about the details of the report at this point!

8 Exit Design Analyzer by clicking the mouse through the following


menu sequence:

File

Quit

OK

Well done! You have just completed the core of a simple design in less
than 20 minutes!

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Unit 1 Lab Exercise

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(Youll answer these questions in later labs.)

How would you handle the following last-minute changes to the designs
specification?
1.

Counter width increases from two bits to six?


The bit width values can be changed by simple modifications to the HDL code.
With careful coding for design reuse, i.e., using parameters in Verilog or
generics in VHDL, the code doesnt even have to change you can simply
specify the new generic/parameter values when you elaborate the design.

2.

Clock frequency increases to 100 MHz?


Change the period of the clock in the constraints file, or simply change the
period via the Design Analyzer menus.

3.

Operating temperature range extends to +125C?

4.

Operating voltage drops to 4.5 volts?


Change operating conditions via the Design Analyzer menus or in the
constraints file.

5.

Up_DownF input arrives 2ns later than before?


Change one line in the constraints file and recompile

6.

Internal scan and boundary scan circuitry is required?


The commands insert_scan and compile -scan insert internal scan circuitry.
The insert_jtag command can insert boundary scan cells and synthesize a TAP
controller and all associated logic.

7.

You want to automate this process?


You could simply write one script file which includes all of the scripts you
have executed in this lab.

8.

You have to switch to a different silicon vendor?


Get the library file from your new vendor, install it on your workstation, point
your target_library variable to it, and recompile.

Synopsys Chip Synthesis Lab Guide

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Unit 1 Lab Exercise