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AV 242 VLSI LAB

VLSI LABSHEET-1
Study of Basic Simulation Flow
The following diagram shows the basic steps for simulating a design in Questa
Basic Simulation Flow - Overview Lab

Creating the Working Library

In Questa, all designs are compiled into a library. You typically start a new simulation in
Questa by creating a working library called "work," which is the default library name used by the
compiler as the default destination for compiled design units.
Compiling Your Design
After creating the working library, you compile your design units into it. The Questa
Library format is compatible across all supported platforms. You can simulate your design on any
platform without having to recompile your design.
Loading the Simulator with Your Design and Running the Simulation
With the design compiled, you load the simulator with your design by invoking the
Simulator on a top-level module (Verilog) or a configuration or entity/architecture pair (VHDL).
Assuming the design loads successfully, the simulation time is set to zero, and you enter
a run command to begin simulation.
Debugging Your Results
If you dont get the results you expect, you can use Questas robust debugging environment
to track down the cause of the problem.
Create the Working Design Library
Before you can simulate a design, you must first create a library and compile the source code
into that library.
1. Type vsim at a UNIX shell prompt or use the Questa icon in Windows.
2. Click File-New-Source-VHDL

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Enter the following codes in two separate files and save with <filename>.vhd in a directory.
//For example here I have given the VHDL code for simple NAND Gate and its Test Bench
for your familiarization.
Library ieee;
use ieee.std_logic_1164.all;
entity logic_nand is
port
(a,b : in std_logic;
C : out std_logic);
end logic_nand;
architecture beh of logic_nand is
begin
c<=a nand b;
end beh;
Select File > Change Directory and change to the directory where your source files are save.
3. Create the working library.
a. Select File > New > Library.
This opens a dialog where you specify physical and logical names for the library. You can
create a new library or map to an existing library. Well be doing the former.

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The Create a New Library Dialog

b. Type work in the Library Name field (if it isnt already entered automatically).
c. Click OK.
Questa creates a directory called work (any other name typed in the Library name field) and
writes a specially-formatted file named_info into that directory. The _info file must remain in the
directory to distinguish it as a Questa library. Do not edit the folder contents from your operating
system; all changes should be made from within Questa.

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work Library Added to the Library Window

When you pressed OK in step 3c above, the following was printed to the Transcript window:
vlibwork
vmapworkwork
These two lines are the command-line equivalents of the menu selections you made. Many
command-line equivalents will echo their menu-driven functions in this fashion.
Compile the Design Units
With the working library created, you are ready to compile your source files.
You can compile by using the menus and dialogs of the graphic interface.
1. Compile <filename>.vhd
a. Select Compile > Compile. This opens the Compile Source Files dialog
If the Compile menu option is not available, you probably have a project open. If so,
close the project by making the Library window active and selecting File > Close from the menus.
b. Select <filename>.vhd module from the Compile Source Files dialog and click Compile. The
files are compiled into the work library.
c. When compile is finished, click Done.
Compile Source Files Dialog

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2. View the compiled design units.

a. In the Library window, click the + icon next to the work library and you will see two design
units. You can also see their types (Modules, Entities, etc.) and the path to the underlying source
files.
VHDL Modules Compiled into work Library

Load the Design

1. Load the test_filename module into the simulator.
When the design is loaded, a Structure window opens (labeled sim). This window
displays the hierarchical structure of the design as shown in fig. You can navigate within the design
hierarchy in the Structure (sim) window by clicking on any line with a + (expand) or - (contract)
icon.

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Run the Simulation

Were ready to run the simulation. But before we do, well open the Wave window and add
signals to it.
1. Open the Wave window.
a. Enter view wave at the command line. The Wave window opens in the right side of the
Main window. Resize it so it is visible.
You can also use the View > Wave menu selection to open a Wave window. The Wave window is
just one of several debugging windows available on the View menu.
2. Add signals to the Wave window.
a. In the Structure (sim) window, right-click test_filename to open a popup context
menu.
b. Select Add > To Wave > All items in region All signals in the design are added to the
Wave window.

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Using the Popup Menu to Add Signals to Wave Window

3. Run the simulation.

a. Click the Run icon. The simulation runs for 100 ns (the default simulation length) and
waves are drawn in the Wave window.
b. Enter run 500 at the VSIM> prompt in the Transcript window. The simulation advances
another 500 ns for a total of 600 ns.
c. Click the Run -All icon on the Main or Wave window toolbar. The simulation continues
running until you execute a break command or it hits a statement in your code (e.g., a Verilog $stop
statement) that halts the simulation.

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Waves Drawn in Wave Window

Test Bench Program

Library ieee;
use ieee.std_logic_1164.all;
entity test_nand is
end test_nand;
architecture beh of test_nand is
component logic_nand
port
a,b:in std_logic;
c:out std_logic);
end component;
signal a,b,c:std_logic;
begin
u0:logic_nand port map(a=>a,b=>b,c=>c);--instantiation
--logic_nand port map(a,b,c);--another way of instantiation
b<='0','1' after 5 ns,'0'after 10 ns,'1' after 15 ns;
a<='0','1' after 5 ns;
end beh;
VHDL SIMULATION
Write the VHDL code for all the logic gates(Behavioral). Simulate using Modelsim/QuestaSim by
writing by Test benches and show the waveform.

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ModelSim/Questasim is a verification and simulation tool for VHDL, Verilog, System

Verilog and mixedlanguage designs.
Follow the following procedure to down load the Libero IDE V8.6 free 1 year license
software from www.actel.com
Go to Customer portal
Register as new user
Go to download
Download Libero IDE ver9.1 and install
To get the license
It uses your PC disk drive number as id.
Then
Go to licensing in main menu
Enter in by giving your username and password
Click Request free License
Under Free 1 Year Licenses
Click Libero Gold Node Locked for windows.
The license will be generated and send to your email
Create a folder as flexlm and paste the license in that folder
How to install the license in your system
Go to My computer- Right click
Properties-Advanced-Environmental variables
Create the variable as LM_License_File
Give the path name and click ok
Crate a short cut of ModelSim in your desktop
(C:\Libero\Model\win32acoem)

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