Xilinx ISE VHDL and Simulator Tutorial

Version 14.7

Modified by: Lindon Falconer on September 24, 2017

Modified by: Hoang Nguyen on June 11, 2015

Prepared by: Bayan Nimer on February 1, 2012

Instructor: Lindon Falconer

Xilinx ISE Simulation Tutorial

Contents

1. Introduction .......................................................................................................................................... 3

2. Basic Software Requirements ............................................................................................................. 4

3. ISE Project Navigator.......................................................................................................................... 5

4. Creating New Project........................................................................................................................... 6

5. Creating VHDL Source Files ............................................................................................................ 10

6. Editing VHDL Source Code .............................................................................................................. 14

7. Synthesizing VHDL Code .................................................................................................................. 15

8. Simulation of Design .......................................................................................................................... 17

9. Simulation Printouts .......................................................................................................................... 31

Appendix: Installing Xilinx WebPack .................................................................................................. 34

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1. Introduction

Xilinx is a powerful software tool that is used to design, synthesize, simulate, test and verify
digital circuit designs. The designer (you in this case) can describe the digital design by
either using the schematic entry tool or a hardware description language. In this tutorial, we
will create VHDL design input files – the hardware description of the logic circuit, compile
VHDL source files, create a test bench and simulate the design to make sure of the correct
operation of the design (functional simulation). The purpose of this tutorial is to give new
users an exposure to the basic and necessary steps to implement and examine your own
designs using ISE environment. In this tutorial, we will design one simple module (OR gate);
however, in the future, you will be designing such modules and completing the overall circuit
design from these existing files.

A VHDL input file in the Xilinx environment consists of:

 Entity Declarations: module name and interface specifications (I/O) – list of input
and output ports; their mode, which is direction of data flow; and data type.
 Architecture: defines a component’s logic operation.

As you will learn (or have learned) in this course, there are different styles for the
architecture body:

o Behavioral – set of sequential assignment statements

o Data Flow – set of concurrent assignments
o Structural – set of interconnected components

A combination of these could be used, but in this tutorial we will use Dataflow. In
its simplest form, the architectural body will take the following format, regardless
of the style:

architecture architecture_name of entity_name is

begin
… -- statement
end architecture_name;

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2 Basic Software Requirements

 After creating an account at https://www.xilinx.com/registration/create-

account.html, install Xilinx software: ISE https://www.xilinx.com/products/design-
tools/ise-design-suite/ise-webpack.html

 For a step by step process of downloading and installing Xilinx ISE Webpack (student
version), go to the appendix at the end of tutorial.
 Xilinx ISE Simulation Tutorial

3. ISE Project Navigator

In this section, we introduce the reader to the main components of an “ISE Project
Navigator” window, which allows us to manage our design files and move our design
process from creation, to synthesis, to simulation phase.

1 2 3 4

Figure 1: Xilinx Project Navigator window

1. Toolbar: provides fast access to frequently used menu commands.

2. Design Panel: consists of the following three areas
A. View Pane – allows for only viewing source files that are associated with the
selected design phase (e.g. testbench source files can only be viewed in
“Implementation” view).
B. Hierarchy Pane – allows for viewing source files that you created and added
to your project. You can double click a source file to open for editing in the
workspace. You can expand the level of hierarchy by clicking (+) icon or
collapse by clicking (-) icon.
C. Process Pane – determines and shows only the processes available to run for
the selected source file. Similarly, they can be expanded and collapsed using
(+) and (-) icons, respectively.

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3. Transcript Window – displays output messages from processes you run.

4. Workspace – used to view and edit source files, multiple files can be opened
simultaneously and the name of each file will be shown in a separate tab in the
bottom of workspace window to enable you to switch between different files.

4. Creating New Project

 In this Project, we will be designing, synthesizing and simulating a 2-input “or gate”,
where “a” and “b” are our inputs and “c” is our output. The truth table (as we all know) is
given below (used to verify our design).

a (1st Input) b (2nd Input) c (Output)

0 0 0
0 1 1
1 0 1
1 1 1
Table 1: Truth Table for an OR Gate

• In order to start ISE, double click the desktop icon:

Or click:
Start  All Programs  Xilinx Design Suite 14.4  ISE Design Tools  64-bit
Project Navigator
You will be presented with “Tip of The Day”, just click “OK”

Figure 2: Start of Xilinx Navigator

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• Create a new project by selecting:

1. File  New Project, the following window will appear

Figure 3: Creating new project using “New Project Wizard”

2. In the “Name” field enter a short name for your project that correctly describes what
you are designing (For now we will use “ORgate”). Also, make sure that your project
name:
o Starts with a letter
o Contains only alphanumeric characters and underscores
o Cannot contain two consecutive underscores.
3. Click the Browse icon (pointed by the arrow in the Figure above) in order to select
the desired location to which you would like to save your project.
4. In the “Top-level source type” field, make sure that HDL is selected – this is selected
if the top level design to be used is in VHDL or Verilog, which can include lower
level modules such as HDL files, schematics or different types.
5. Click “Next”

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6. In the “Project Settings” page shown below, ensure that the following options are set
because they effect the types and processes that will be available for your design:
o “Product Category”  All
o “Family”  Spartan3E
Spartan 3A and Spartan 3AN

o “Device”  XC3S500E
XC3S50A
o “Package”  TQ144FT256
o “Speed”  -5
o “Top-Level Source Type”  HDL (automatically selected)
o “Synthesis Tool”  XST (VHDL/Verilog), which is a technology to
synthesize VHDL, Verilog, or mixed language designs to create “Xilinx-
specific netlist” files.
o “Simulator”  ISim (VHDL/Verilog), allows for running integrated
simulation process as part of your ISE design flow.
o “Preferred Language”  VHDL

Spartan 3A and Spartan 3AN

XCS50A
TQ144

Figure 4: Changing properties of your project

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7. Leave the remaining fields as their default settings.

8. Click “Next” and you will be presented with a summary of your new project as
shown in Figure 5.

Figure 5: Summary of your new project information

 In order to open an existing project in Xilinx, select File  Open Project to show the
lists of projects available in a certain directory, choose the project you want and check
“OK”

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9. Click “Finish” and you will exit the “New Project Wizard” and be taken back to the
original “ISE Project Navigator” window, but a new project hierarchy is generated
with the “ORgate” design file displayed in the “Hierarchy Pane” as shown in Figure
6.

Figure 6: “ISE Project Navigator” after creating a new project

5. Creating VHDL Source Files

 The “Create New Source Wizard” will enable you to create a VHDL source input file
(.vhd) for a combinational logic design that will contain information about the design of
the 2-input “or gate”…. (Any other text editor can be used to do so)

1. Click on the “New Source” icon , which is to the left of the “Hierarchy Pane.”
This can also be done by right clicking on “ORgate” source file in the “Hierarchy
Pane” and clicking “New Source,” as shown in Figure 7. This will take us to the
“New Source Wizard” as shown Figure 8.

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Create New
Source

Add Source

Add Copy of
Source

Figure 7: Creating a new source

Figure 8: “New Source Wizard”

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2. Select “VHDL Module” as a source file type to be added to the project since our files
will contain VHDL design code, so our files will have “.vhd” extension.
3. In the “File name” field, enter a name of the entity for which you are creating input
and output ports for. Remember to follow the conventions mentioned earlier (in
Section 4, step 2) for naming the project. In this case, enter “ORgate”.
4. For the “Location” field, click the browse icon to navigate to the appropriate folder,
which should be the same one used for creating the project.
5. Make sure that the “Add to project” checkbox is selected to automatically add this
source to your project so that you don’t need to add it to the project again manually.
6. Click “Next”, the wizard will take you to the “Define Module” page as shown below,
where I/O of the module (OR gate) will get defined. As you can see, the entity name
is there, but can be changed if you want and the architecture name is “Behavioral” by
default.

Figure 9: Define VHDL source window

7. “Direction” field is used to describe the mode, which is how data is transferred
through the port. We are concerned with 3 modes: in – data flowing into the port; out
– data flowing out of the port; inout – data flowing into and out of the port (bi-
directional). Since we have 2 inputs and 1 output, in the first 3 fields under port name,
we type “a”, “b” and “c” and set the “Direction” fields as “in” for the first two fields
and “out” for the third field (c).

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8. Click “Next” to view and verify the summary of the information about the new
source created. If any changes are to be made, just click cancel.

Figure 10: New source information window

9. After making sure that the description of the module is correct, click “Finish.” The
source file will be now displayed in “ISE Project Navigator” as shown below; the
workspace window will be used as a text editor to make necessary changes to the
source file. All the input and output ports that we specified will be displayed.

Figure 11: VHDL source code editor window in the Project Navigator

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6. Editing VHDL Source Code

Now we have an “ORgate.vhd” file in the ISE text editor, where only entity declarations that
we have created using the “New Source Wizard” are available (You can make changes to
ports if needed). We can change the architecture name to “Dataflow” since that is the style
we will be using. We are missing the architectural body.

In the statement part, we will write one statement that describes how our or gate works, in
the following manner:

Target (output) C <= ( A OR B );

Signal

Signal Assignment Operator Source (input) Signal

Figure 12: OR gate description using dataflow architecture

After writing the statement, we click save icon to save our work or do it through File  Save

 Note: VHDL programs can be edited using any text editor (not recommended) and then

add them to the project directory using “Add Copy of Source” icon .

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7. Synthesizing VHDL Code

The design has to be synthesized before it can be checked for correctness by running
functional simulation. XST will analyze the VHDL code and try to gather building blocks in
order to create efficient implementation by performing resource sharing to reducing area
while increasing clock frequency. In other words, synthesis will convert the code into digital
circuit by transforming it into a netlist of gates.

1. Make sure that “Implementation” checkbox is checked from the “View Pane” in the
“Design” Panel.
2. From the “Process Pane” in the “Design” Panel, double click on the “Synthesize –
XST” function as shown in Figure 13, which will check the syntax of your code and give
you warning and error messages if any are present in the “Transcript Window”, where
you can click “Errors” or “Warnings” tab. Errors are indicated by next to the
message and warnings are indicated by . You can right click the message and select
“Search for Answer Record” to open the Xilinx website and show any related answer.
Otherwise, you can just right click the message and select “Go to Source” to go directly
to the error. These errors must be corrected, saved, and fresh synthesis (compilation)
needs to be done again before you move to the next step; otherwise, you won’t be able to
simulate your design. After correcting the errors (if any), the synthesis process runs

without errors and displays to the left of “Synthesis – XST”

After a successful Synthesis, you will get a message as shown in Figure 13.

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Figure 13: Successful synthesis of the design

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8. Simulation of Design
In order to do functional and timing simulation, we will create a test bench for our VHDL
code which will help in debugging our design. This allows us to verify that our design
functions as expected (given inputs in our truth table, we get desired outputs). In order to test
the gate completely, we shall provide all the different input combinations.

1. From the tool bar, select Project  New Source

Figure 14: Create a new test bench source File

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2. From the “Select Source Type” options select “VHDL Test Bench”

Figure 15: Add test bench to the design project

3. In the “File name” field choose a name that signifies the test bench and adheres to the
naming conventions mentioned earlier. Type “testorgate”
4. For the “Location” field, click the browse icon to navigate to the appropriate folder,
which should be the same one used for creating the project.
5. Click “Next”

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6. The following window allows you to select which design you want to create a test
bench for, in our case “ORgate” since it is the only module we have; however, for
your future designs, you can make test benches for individual components of your
designs as well as the top-level design which ties it all together.

Figure 16: Associating a model to a test bench

7. Click “Next”
8. A summary window like the one shown below will appear, click “Finish”

Figure 17: Test Bench information window

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9. Now you will view the test bench file (testorgate.vhd), shown below, that Xilinx has
generated in the workspace window.

Figure 18: Test bench source file

 Now going to our test bench file, we can see that it consists of the same two main parts of
a normal VHDL design, which is the entity and architecture. The entity is left blank
because we are simply supplying inputs and observing outputs to the design in test. The
architecture part will consist of the design we are testing as a component, input and
output signals, a port map of the component for the UUT (Unit Under Test), a process to
run the clock and a stimulus process, which will be responsible for running the tests that
are written to test the design.

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10. Let’s modify the default code by removing the highlighted code shown below, which
is the clock process that is generated by default, which divides the clock period by
two. We also want to remove the stimulus process.

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The “testORgate.vhd” file will look as follows:

Figure 19: Test Bench source file after code deletion

11. Replace the deleted code with the following code segment, which will perform a
very simple initial test of the design for simulation by giving different values of
inputs:

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 In our modified code, we have chosen to wait for 100 ns, which means the time delay for
which the input has to maintain the current value; i.e., after 100 ns have elapsed the next
set of values can be assigned to the inputs.
12. The testbench file does not appear in the “Hierarchy” Pane of the “Design” Panel.
This is because there is a separate view for implementation and test files. In order to
view test files, select the box of “Simulation” in the “View Pane” of the “Design”
panel. In the “Process Pane,” double click on the “Behavioral Check Syntax” to
make sure that you didn’t make any syntax errors while making changes.
13. Save your work.

Figure 20: Successful syntax check of test bench file

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14. Double click on “Simulate Behavioral Model” in the “Process Pane”, which will
open the ISim software with your test bench loaded.

Figure 21: Successful Simulation of the test bench source file

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15. ISim simulator window will open with your simulation executed, as shown in Figure
22, where you are able to simulate your designs and check for errors. You can step
through your VHDL designs and check the states of signals and set the simulation to
run for specific period of time. Make sure to check the results of the simulation output
against your truth table results to verify the correctness of the design. The resolution
of the simulation is set to 1 picosecond to ensure correct processing of your design.

Figure 22: Behavioral Simulation Output Waveform

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16. To get a better view of the simulation waveforms, from the tool bar, click on View 
Zoom  Full View or use F6 or click on the shortcut “Zoom to Full View” icon
. This will give you a better view of what your simulation is doing.

Zoom to Full View

Run

Figure 23: Full view of the behavioral Simulation Output Waveform

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17. In the text box located near the run button, you may specify amount of time for the
simulation to run; the button to the left of the box will execute the simulation for the
time you have specified. After setting the new simulation time, click on Re-Start to
clear the previous simulation result and then click on Run to start simulating with
new time setting. Below is an example of 2us of simulation time:

Figure 24: Change of Simulation Run time

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18. You can change the default simulation run time. This will help to avoid setting the
run time again every time you launch the simulation. This can be done by setting the
properties of your project in Xilinx. Right click on Simulate Behavioral Model, and
then click on Process Properties… An ISim property window will appear. You can
modify the simulation run time from value textbox as in Figure

Figure 25: ISim properties

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Figure 26: Modification of default simulation run time

19. In some cases, you want to change the display format of a specific signal from binary
format into other format. This can be done by doing a right click on that signal, then
click on Radix and choose your desired display format. Below is an example of
changing display format from binary number to hexadecimal number:

Figure 27: Changing of Radix

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20. When your design is big, it is not easy to just look at into your HDL code to find the
mistake. In this case, you may want to see the internal signals of a specific component
to see if it is working properly or not. To do this, you will need to open both panels
Instances and Processes and Objects

Figure 28: “Instances and Processes” and Objects panel

 Click on utt in Instances and Processes panel, then all of the instantiated
components will be listed. Then, click on a specific instantiated component. All of
the signals belongs to this component will appear in the Objects panel. Now, you
can drag and drop these signals into the waveform panel then restart and run your
simulation again to see the values of these signals. The figure 29 is an example of
displaying signals of program counter component in a CPU.

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Drag & Drop and Re-run the simulation

Figure 28: Display internal signals

9. Simulation Printouts

1. From the tool bar, select File  Print

Figure 24: Printing the correct design simulation

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2. “ISim Print Setup” window like the one shown in Figure 25 will appear, from “Time
Range” select the checkbox for “Full Simulation”.

Figure 25: Setup for printing the simulation of the design

3. Click “OK”
4. Select “D119 …” printer ( Or, you can use Adobe PDF to print out your simulation
waveform to pdf format and paste it into your report)

Figure 26: Printer selection

5. Click “Finish”
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Good Luck!
You’re all set to start using the Xilinx ISE Simulator to write VHDL code for digital circuits,
synthesize and simulate your designs. Save often, watch out for syntax errors, correct your errors
before proceeding to simulating your design, and remember to include enough input cases in
your test bench to verify the correctness of your design. Don’t worry if the different styles of
architectural body seem a little confusing now, you will get into more depth in class and a good
bit of practice is necessary to use them effectively.

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Appendix – Downloading and Installing Xilinx ISE Webpack (Student Version 14.4)

1. Navigate to http://www.xilinx.com/support/download/index.htm
2. Click on the appropriate file download for your system, mostly “Full Installer for
Windows”

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3. You will be redirected to a “Sign in” page. If you already have an account, sign in using
your username and password; otherwise create an account.

4. You will be directed to a “Download Manager” page and prompted in the top bar of
your window whether you give permission to run it, so click run and download will start.
5. The downloaded tar file might not be recognized by your computer so I recommend
downloading WinRAR free trial from http://www.rarlab.com/download.htm or any
program of your own choice.
6. Unzip the file – all files will be extracted to a folder as shown below.

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7. Double click the folder shown in the figure above, and then double click on “xsetup.exe”
to start installation.

8. Click “Next” in the following welcome page.

9. Check the box for accepting the first page of agreement and the second page of
agreement and click “Next” after each.
10. Select the “ISE WebPack + Vivado WebPack” not the default selection and click
“Next”

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11. Choose directory of file, click “Next” on the following two windows, and then click
“Install”.
12. When the installation is done, “Xilinx License Configuration Manager” will pop up so
you can obtain a free license. Click “Get Free ISE WebPack License” in the “Acquire
a License” tab.
13. Click “Next” where you will be directed to Xilinx webpage.
14. Log in using your username and password.
15. At the following window ensure that “Vivado and ISE Suit: WebPack License” is
checked and click on “Generate Node-Locked License”.

16. Click “Next” on the “Generate License” window that pops up.
17. Click “Next” on the “Review License Request” window.

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18. Click the download button from the manage licenses tab.

19. You will be presented with a “Congratulations” window for successfully generating a
license and a “.lic” file will be downloaded in your “Downloads” folder.
20. In the Xilinx “License Manager” window, click on “Copy” and the license will be
copied to Xilinx directory.

 You are now able to use the “ISE Design Suite 14.4”.

References

[1] ISE Simulator – In Depth Tutorial,

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/ug682.pdf

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