CPE421

King Khalid University

College of Computer Science

Department of Computer Engineering

CPE-421
Integrated Circuit Design
LAB MANUAL
Student name:-
ID Number:- Serial Number:-..
Group Number: - (..)

Prepared by
Syed Asif Basha
1436-1437 1st Semester
CPE 421-Integrated Circuit Design Lab Manual- Syllabus and Course Outline KKU-CS-CE

Syllabus and Course Outline

Course Outline:

Week Experiment
Name of the experiment Date
Number Number
1 Start of classes and Manual Registration 23-27/8/2015
2 Experiment 1 Introduction to VHDL language & Xilinx ISE environment. 30-3/8,9/2015
Program to simulate a Half Adder using 1.Data flow Model. 2. Behavioral
3 Experiment 2 6-10/9/2015
Model. Generate a synthesis report and generate bit file (bit stream).
Program to simulate a Full Adder using 1.Data flow Model. 2. Behavioral 13-17/9/2015
4 Experiment 3
Model and generate a synthesis report.
5 Mid Semester Vacation 18-28/9/2015
Program to simulate a 8x1 Multiplexer using Behavioral model and generate 29-1/9,10/2015
6 Experiment 4
a synthesis report
Program to simulate a 1x8 De-multiplexer using data flow model and 4-8/10/2015
7 Experiment 5
generate a synthesis report
Program to simulate a 8x3 Encoder using data flow model and generate a
8 Experiment 6 11-15/10/2015
synthesis report
9 18-22/10/2015
Midterm Practical Examination
Program to simulate a 3x8 Decoder using data flow model and generate a
10 Experiment 7 25-29/10/2015
synthesis report
Program to simulate a J-K Flip-flops using data flow model and generate a
11 Experiment 8 1-5/11/2015
synthesis report
Program to simulate a Up-down Counter using data flow model and generate
12 Experiment 9 8-12/11/2015
a synthesis report
Program to simulate a BCD to 7-Seg Decoder using data flow model and
13 Experiment 10 14-19/11/2015
generate a synthesis report
Program to simulate a Mealy state machine using Behavioral model and
14 Experiment 11 29-3/11,12/2015
generate a synthesis report
15 Home Work 6-10/12/2015
16 Final Practical Examination 13-19/12/2015
Grades:
MID Term Exam 7 marks
Final Exams 10 marks
Lab Record 3 marks
Home Work 5 marks
Lab Policy:
Attendance is Mandatory.
Copying in labs will get a ZERO grade.
There are exercises at the end of each lab experiment, students should solve this and submit it in the next session.
Lab reports are due at the beginning of the next lab session. LATE lab reports will have a 20% penalty, if they are given
within one week of the due date.
Report Format:
The report should consist of the following sections:
Cover Page: Include your name, student id number, lab number, topic of the experiment, experiment number
my name as a teacher assistant (the cover page uploaded in the Black Board)
Report Body: consist of the following sections

Computer Engineering Dept. Syed Asif Basha

PageI
CPE 421-Integrated Circuit Design Lab Manual- Syllabus and Course Outline KKU-CS-CE
Objective/Theory: In no more than four sentences, state in your own words the purpose of performing
the experiment and theory of it.
Exercises: Your report should include answers for the exercise at the end of each experiment.
Conclusion/Comment: Write a paragraph or two that describes the major points of the lab. Also feel free
to discuss any problems you had performing the experiment would like to share
Academic Calendar Year 1436-1437 H
First Semester 1436-1437

Computer Engineering Dept. Syed Asif Basha Page II

CPE 421-Integrated Circuit Design Lab Manual- Experiment #1 KKU-CS-CE

Experiment #1
Introduction to VHDL Programming Language and Xilinx ISE environment
Aim: To study the Basics of VHDL Programming Language and Xilinx ISE environment.
Objective: Write a VHDL Program for 2-input AND gate using dataflow modelling and generate
a synthesis report.
Software Used: Xilinx ISE 8.2i
Theory:
HDLs: Hardware description Languages are used to describe any Hardware such as AND gate, OR gate,
Multiplexer, Decoder, Counter and Registers
2 types:
1. VHDL: In VHDL V stands for VHSIC (Very High Speed Integrated Circuit) Hardware description
language.
2. Verilog
Logic Circuits: All digital logic circuits are classified into 2 types
1. Combinational Logic circuits
2. Sequential Logic Circuits
1. Combinational Logic circuits: In these Circuits the output at any time only depends on present value of
input.
Examples. All logic gates such as and ,or, not and xor gates, multiplexer, de-multiplexer, decoder, encoder,
half adder and full adder
2. Sequential Logic Circuits: In these Circuits the output at any time not only depends on present value of
input but also on the past value of output.
Examples. All Flip Flops such as S-R,J-K,T and D flip Flops, counters, shift registers and state machines

General Structure of VHDL Program:

Entity: A VHDL entity specifies the name of the entity, the ports of the entity and entity-related information.
All designs are created using one or more entities.
Architecture: Architecture describes the behavior of the entity. A single entity can have multiple
architectures. One architecture might be behavioral while another might be a structural description of the
design.
Types of modelling: 1. Data flow modelling
2. Behavioral Modelling
3. Structural Modelling

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #1 KKU-CS-CE
Procedure: How to execute a VHDL Program in Xilinx ISE 8.2i
1. Double click on Xilinx ISE 8.2i Design Suit icon on the Desktop.
2. Click on file New project Enter the project name & Location, Select top level source type as HDL. Click
NextNext click on New Source select VHDL Module write Module Name Next write input and
output ports and Finish.
3. Click Next Next Next Finish.
4. Type program in the work space window and save the program.
5. In the sources window choose behavioral simulation.
6. In the process window expand the + symbol on Xilinx ISE Simulator Double click on check syntax.
7. After successful verification of syntax double click on simulate behavioural model.
8. Add an appropriate test bench waveform from the project new source choose test bench Waveform name
the test bench waveform next Finish.
9. select appropriate test bench input waveform save.
10. In the process window expand the + symbol on Xilinx ISE Simulator Double click on Generate expected
Simulation results yes yes.
11. To view synthesis report chooses synthesis in the sources window.
12. In process window expand the implement design expand synthesis XST double click on view synthesis

Report. Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AND2 is
Port ( a,b : in STD_LOGIC;
y : out STD_LOGIC);
end AND2;
architecture Behavioral of AND2 is
begin
y<= a and b;
end Behavioral;

Timing Diagram: it a plot of time both input and output signals of a system with time on x-axis and
logic value on the y-axis
Example: Timing diagram of a 2-input AND gate is as follows.

Lab Exercise:
1.Program to simulate a 3-input xor gate using data flow Model and generate and generate generate a
synthesis report.

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #2 KKU-CS-CE

Experiment #2
Half Adder
Aim: To Implement a Half Adder using Xilinx ISE 8.2
Objective: Write a VHDL program to simulate a Half Adder using behavioural modelling and generate a
synthesis report.
Software Used: Xilinx ISE 8.2i

Theory: A Half Adder is a combinational logic circuit, it has 2 inputs and 2 outputs

Procedure:
1. Double click on Xilinx ISE 8.2i Design Suit icon on the Desktop.
2. Click on file New project Enter the project name & Location, Select top level source type as HDL. Click
NextNext click on New Source select VHDL Module write Module Name Next write input and
output ports and Finish.
3. Click Next Next Next Finish.
4. Type program in the work space window and save the program.
5. In the sources window choose behavioral simulation.
6. In the process window expand the + symbol on Xilinx ISE Simulator Double click on check syntax.
7. After successful verification of syntax double click on simulate behavioural model.
8. Add an appropriate test bench waveform from the project new source choose test bench Waveform name
the test bench waveform next Finish.
9. select appropriate test bench input waveform save.
10. In the process window expand the + symbol on Xilinx ISE Simulator Double click on Generate expected
Simulation results yes yes.
11. To view synthesis report chooses synthesis in the sources window.
12. In process window expand the implement design expand synthesis XST double click on view synthesis
Report.

Program1: VHDL Program for Half Adder using behavioral modelling

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity halfadder is
port ( a, b : in std_logic;
sum, carry : out std_logic);
end halfadder;
architecture behavioral of halfadder is
begin
process(a,b)

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #2 KKU-CS-CE
begin
if (a = 0 and b = 0) then
sum<= 0;carry<= 0;
elsif (a = 0 and b = 1) then
sum<= 1; carry<= 0;
elsif (a = 1 and b = 0) then
sum<= 1; carry<= 0;
else sum<= 0; carry<= 1;
end if;
end process;
end behavioral;

Timing Diagram:

Lab Exercises:
1. Write a VHDL Program for Half Substractor shown below using dataflow modeling and generate a
synthesis report.

2. Write a VHDL Program for Full Adder shown below using dataflow modeling and generate a synthesis
report.

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #3 KKU-CS-CE

Experiment #3
Full Adder
Aim: To Implement a Full Adder using Xilinx ISE
Objective: Write a VHDL program to simulate a Full Adder using behavioral modelling and generate a
synthesis report.
Software Used: Xilinx ISE 8.2i
Theory: A Full Adder is a combinational logic circuit, it has 3 inputs and 2 outputs

Procedure:
1. Double click on Xilinx ISE 8.2i Design Suit icon on the Desktop.
2. Click on file New project Enter the project name & Location, Select top level source type as HDL. Click
NextNext click on New Source select VHDL Module write Module Name Next write input and
output ports and Finish.
3. Click Next Next Next Finish.
4. Type program in the work space window and save the program.
5. In the sources window choose behavioral simulation.
6. In the process window expand the + symbol on Xilinx ISE Simulator Double click on check syntax.
7. After successful verification of syntax double click on simulate behavioural model.
8. Add an appropriate test bench waveform from the project new source choose test bench Waveform name
the test bench waveform next Finish.
9. select appropriate test bench input waveform save.
10. In the process window expand the + symbol on Xilinx ISE Simulator Double click on Generate expected
Simulation results yes yes.
11. To view synthesis report chooses synthesis in the sources window.
12. In process window expand the implement design expand synthesis XST double click on view synthesis
Report.

Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladder is
port(a, b, c:in std_logic;
sum, carry: out std_logic);

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #3 KKU-CS-CE
end fulladder;
architecture behavioral of fulladder is
begin
process (a,b,c)
begin
if (a = 0 and b = 0 and c = 0 ) then
sum<= 0;carry<= 0;
elsif (a = 0 and b = 0 and c = 1 ) then
sum<= 1; carry<= 0;
elsif (a = 0 and b = 1 and c = 0 ) then
sum<= 1;carry<= 0;
elsif (a = 0 and b = 1 and c = 1 ) then
sum<= 0;carry<= 1;
elsif(a = 1 and b = 0 and c = 0 ) then
sum<= 1; carry<= 0;
elsif(a = 1 and b = 0 and c = 1 ) then
sum<= 0; carry<= 1;
elsif(a = 1 and b = 1 and c = 0 ) then
sum<= 0; carry<= 1;
else sum<= 1; carry<= 1;
end if;
end process;
end behavioral;

Timing Diagram:

Lab Exercise:
1. Write a VHDL Program for Half adder shown below using behavioral modelling and generate a
synthesis report.

2. Write a VHDL Program for a 2 input Nand gate using behavioral modelling and generate a
synthesis report.

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #4 KKU-CS-CE

Experiment #4
Multiplexer
Aim: To Implement a 2nx1 Multiplexer using Xilinx ISE
Objective: Write a VHDL program to simulate a 8x1 Multiplexer using dataflow modelling and

generate a synthesis report.

Software Used: Xilinx ISE 8.2i

Theory: A 2nx1 Multiplexer is a combinational circuit that selects information from 2n input lines to one
output line based on the select lines.

For n=3(select lines) it becomes a 8x1 Multiplexer it has 8 input lines and 1 output line

For n=2(select lines) it becomes a 4x1 Multiplexer it has 4 input lines and 1 output line

For n=1(select lines) it becomes a 2x1 Multiplexer it has 2 input lines and 1 output line

Procedure:
1. Double click on Xilinx ISE 8.2i Design Suit icon on the Desktop.
2. Click on file New project Enter the project name & Location, Select top level source type as HDL. Click
NextNext click on New Source select VHDL Module write Module Name Next write input and
output ports and Finish.
3. Click Next Next Next Finish.
4. Type program in the work space window and save the program.
5. In the sources window choose behavioral simulation.
6. In the process window expand the + symbol on Xilinx ISE Simulator Double click on check syntax.
7. After successful verification of syntax double click on simulate behavioural model.
8. Add an appropriate test bench waveform from the project new source choose test bench Waveform name
the test bench waveform next Finish.
9. select appropriate test bench input waveform save.
10. In the process window expand the + symbol on Xilinx ISE Simulator Double click on Generate expected
Simulation results yes yes.
11. To view synthesis report chooses synthesis in the sources window.
12. In process window expand the implement design expand synthesis XST double click on view synthesis
Report.

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #4 KKU-CS-CE
Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux8x1 is
Port (d: in std_logic_vector (7 downto 0);
s: std_logic_vector (2 downto 0);
f: out std_logic);
end mux8x1;
architecture behavioral of mux8x1 is
begin
f<= d(0) when s="000" else
d(1) when s="001" else
d(2) when s="010" else
d(3) when s="011" else
d(4) when s="100" else
d(5) when s="101" else
d(6) when s="110" else
d(7) when s="111";
end behavioral;
Timing Diagram:

Lab Exercise:
1. Write a VHDL Program for 4x1Multiplexer shown below using dataflow modeling and generate a
synthesis report.

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 CPE 421-Integrated Circuit Design Lab Manual- Experiment #5 KKU-CS-CE

Experiment #5
Demultiplexer
Aim: To Implement a 1x2n Demultiplexer using Xilinx ISE
Objective: Write a VHDL program to simulate a 1x8 Demultiplexer using dataflow modelling and

generate a synthesis report.

Software Used: Xilinx ISE 8.2i

Theory: A 1x2n Demultiplexer is a combinational circuit that passes information from 1 input line to one
2n output line based on the select lines.

For n=3(select lines) it becomes a 1x8 Demultiplexer it has 1 input line and 8 output lines

For n=2(select lines) it becomes a 1x4 Demultiplexer it has 1 input line and 4 output lines

For n=1(select lines) it becomes a 1x2 Demultiplexer it has 1 input line and 2 output lines

Procedure:
1. Double click on Xilinx ISE 8.2i Design Suit icon on the Desktop.
2. Click on file New project Enter the project name & Location, Select top level source type as HDL. Click
NextNext click on New Source select VHDL Module write Module Name Next write input and
output ports and Finish.
3. Click Next Next Next Finish.
4. Type program in the work space window and save the program.
5. In the sources window choose behavioral simulation.
6. In the process window expand the + symbol on Xilinx ISE Simulator Double click on check syntax.
7. After successful verification of syntax double click on simulate behavioural model.
8. Add an appropriate test bench waveform from the project new source choose test bench Waveform name
the test bench waveform next Finish.
9. select appropriate test bench input waveform save.
10. In the process window expand the + symbol on Xilinx ISE Simulator Double click on Generate expected
Simulation results yes yes.
11. To view synthesis report chooses synthesis in the sources window.
12. In process window expand the implement design expand synthesis XST double click on view synthesis
Report.

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 CPE 421-Integrated Circuit Design Lab Manual- Experiment #5 KKU-CS-CE
Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux1x8 is
port(f:in std_logic;
s:in std_logic_vector(2 downto 0);
y:out std_logic_vector(7 downto 0));
end demux1x8;
architecture behavioral of demux1x8 is
begin
y(0)<=f when s="000"else'0';
y(1)<=f when s="001"else'0';
y(2)<=f when s="010"else'0';
y(3)<=f when s="011"else'0';
y(4)<=f when s="100"else'0';
y(5)<=f when s="101"else'0';
y(6)<=f when s="110"else'0';
y(7)<=f when s="111"else'0';
end behavioral;

Timing Diagram:

Lab Exercise:
1. Write a VHDL Program for 1x4 Demultiplexer using dataflow modeling and generate a synthesis report.

y(0)

1x4 y(1)
f
Demultiplexer y(2)
y(3)

S(1) S(0)

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 CPE 421-Integrated Circuit Design Lab Manual- Experiment #6 KKU-CS-CE

Experiment #6
Encoder
Aim: To Implement a 2nxn Encoder using Xilinx ISE
Objective: Write a VHDL program to simulate a 8x3 Encoder using dataflow modelling and generate

synthesis report.
Software Used: Xilinx ISE 8.2i
Theory: An encoder is a circuit that converts information from one format to another, A 2nxn Encoder
converts information from 2n input lines to n output lines.

For n=3 8x3 Encoder it has 8 input lines and 3 output lines

For n=2 4x2 Encoder it has 4 input lines and 2 output lines

For n=1 2x1 Encoder it has 2 input lines and 1 output line

Procedure:
1. Double click on Xilinx ISE 8.2i Design Suit icon on the Desktop.
2. Click on file New project Enter the project name & Location, Select top level source type as HDL. Click
NextNext click on New Source select VHDL Module write Module Name Next write input and
output ports and Finish.
3. Click Next Next Next Finish.
4. Type program in the work space window and save the program.
5. In the sources window choose behavioral simulation.
6. In the process window expand the + symbol on Xilinx ISE Simulator Double click on check syntax.
7. After successful verification of syntax double click on simulate behavioural model.
8. Add an appropriate test bench waveform from the project new source choose test bench Waveform name
the test bench waveform next Finish.
9. select appropriate test bench input waveform save.
10. In the process window expand the + symbol on Xilinx ISE Simulator Double click on Generate expected
Simulation results yes yes.
11. To view synthesis report chooses synthesis in the sources window.
12. In process window expand the implement design expand synthesis XST double click on view synthesis
Report.

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 CPE 421-Integrated Circuit Design Lab Manual- Experiment #6 KKU-CS-CE
Program:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity encoder8x3 is
Port ( i : in std_logic_vector (7 downto 0);
y : out std_logic_vector (2 downto 0));
end encoder8x3;
architecture behavioral of encoder8x3 is
begin
with i select
y<="000" when "00000001",
"001" when "00000010",
"010" when "00000100",
"011" when "00001000",
"100" when "00010000",
"101" when "00100000",
"110" when "01000000",
"111" when others;
end behavioral;
Timing Diagram:

Lab Exercise:
1.Write a VHDL Program for 4x2 Encoder shown below using dataflow modelling and generate synthesis
report.

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 CPE 421-Integrated Circuit Design Lab Manual- Experiment #7 KKU-CS-CE

Experiment #7
Decoder
Aim: To Implement a nx2n Decoder using Xilinx ISE
Objective: Write a VHDL program to simulate a 3x8 Decoder using dataflow modelling and generate a
synthesis Report.
Software Used: Xilinx ISE 8.2i
Theory: A Decoder is a circuit that converts information from one format to another, A nx2n Decoder
converts information from n input lines to 2n output lines.

For n=3 3x8 Decoder it has 3 input lines and 8 output lines

For n=2 2x4 Decoder it has 2 input lines and 4 output lines

For n=1 1x2 Decoder it has 1 input lines and 2 output line

Procedure:
1. Double click on Xilinx ISE 8.2i Design Suit icon on the Desktop.
2. Click on file New project Enter the project name & Location, Select top level source type as HDL. Click
NextNext click on New Source select VHDL Module write Module Name Next write input and
output ports and Finish.
3. Click Next Next Next Finish.
4. Type program in the work space window and save the program.
5. In the sources window choose behavioral simulation.
6. In the process window expand the + symbol on Xilinx ISE Simulator Double click on check syntax.
7. After successful verification of syntax double click on simulate behavioural model.
8. Add an appropriate test bench waveform from the project new source choose test bench Waveform name
the test bench waveform next Finish.
9. select appropriate test bench input waveform save.
10. In the process window expand the + symbol on Xilinx ISE Simulator Double click on Generate expected
Simulation results yes yes.
11. To view synthesis report chooses synthesis in the sources window.
12. In process window expand the implement design expand synthesis XST double click on view synthesis
Report.

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 CPE 421-Integrated Circuit Design Lab Manual- Experiment #7 KKU-CS-CE
Program:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dec3x8 is
Port (i: in std_logic_vector (2 downto 0);
y : out std_logic_vector (7 downto 0));
end dec3x8;
architecture behavioral of dec3x8 is
begin
with i select
y<="00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
end behavioral;
Timing Diagram:

Lab Exercise:
1.Write a VHDL Program for 2x4 Decoder shown below using dataflow modeling and generate a synthesis
Report.

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #8 KKU-CS-CE

Experiment #8
Flip-Flops
Aim: To Implement a Flip-Flop using Xilinx ISE
Objective: Write a VHDL program to simulate a J-K Flip-Flop using behavioral modeling and generate a
synthesis Report.
Software Used: Xilinx ISE 8.2i

Theory: A Flip-Flop is a sequential logic circuit, in which the output not only depends on present input
but also on the past output. The symbol & truth table of a J-K flip-flop is shown below.

Where Q(n+1) next state (the value after the clock is applied)
Q(n) present state (the value before the clock is applied)
X dont care
Procedure:
1. Double click on Xilinx ISE 8.2i Design Suit icon on the Desktop.
2. Click on file New project Enter the project name & Location, Select top level source type as HDL. Click
NextNext click on New Source select VHDL Module write Module Name Next write input and
output ports and Finish.
3. Click Next Next Next Finish.
4. Type program in the work space window and save the program.
5. In the sources window choose behavioral simulation.
6. In the process window expand the + symbol on Xilinx ISE Simulator Double click on check syntax.
7. After successful verification of syntax double click on simulate behavioural model.
8. Add an appropriate test bench waveform from the project new source choose test bench Waveform name
the test bench waveform next Finish.
9. select appropriate test bench input waveform save.
10. In the process window expand the + symbol on Xilinx ISE Simulator Double click on Generate expected
Simulation results yes yes.
11. To view synthesis report chooses synthesis in the sources window.
12. In process window expand the implement design expand synthesis XST double click on view synthesis
Report.

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #8 KKU-CS-CE

Program:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jkff is
Port ( clk,j,k,reset : in std_logic;
q,qb : out std_logic);
end jkff;
architecture Behavioral of jkff is
signal state: std_logic;
signal input: std_logic_vector (1 downto 0);
begin
input <= j&k;
process(clk,reset) is
begin
if reset = '1' then
state <= '0';
elsif (rising_edge(clk)) then
case (input) is
when"11" => state <= not state;
when"10" => state <= '1';
when"01" => state <= '0';
when others =>null;
end case;
end if;
end process;
q <= state;
qb<=not(state);
end Behavioral;
Timing Diagram:

Lab Exercise:
1. Write a VHDL program to simulate a T-Flip-Flop using behavioral modeling and generate a synthesis
Report.

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #8 KKU-CS-CE

T q

clk T- Flip Flop

qb

2. Write a VHDL program to simulate a D-Flip-Flop using behavioral modeling and generate a synthesis
Report.

D q

clk D- Flip Flop

reset qb

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #9 KKU-CS-CE

Experiment #9
Up-down counter
Aim: To implement a up down counter using Xilinx ISE
Objective: Write a VHDL program to simulate a 3-bit up-down counter using behavioral modelling and
generate a synthesis Report.
Software Used: Xilinx ISE 8.2i
Theory: A 3bit-up down counter is a sequential logic circuit, in which the output is incremented by 1 if
The direction input is1 and the output is decremented by 1 if the direction input is 0. The symbol &
truth table of a 3bit-up down counter is shown below.

direction
Cout[2]
clk
3-bit up-down Cout[1]
counter
Cout[0]

Procedure:
1. Double click on Xilinx ISE 8.2i Design Suit icon on the Desktop.
2. Click on file New project Enter the project name & Location, Select top level source type as HDL. Click
NextNext click on New Source select VHDL Module write Module Name Next write input and
output ports and Finish.
3. Click Next Next Next Finish.
4. Type program in the work space window and save the program.
5. In the sources window choose behavioral simulation.
6. In the process window expand the + symbol on Xilinx ISE Simulator Double click on check syntax.
7. After successful verification of syntax double click on simulate behavioural model.
8. Add an appropriate test bench waveform from the project new source choose test bench Waveform name
the test bench waveform next Finish.
9. select appropriate test bench input waveform save.
10. In the process window expand the + symbol on Xilinx ISE Simulator Double click on Generate expected
Simulation results yes yes.
11. To view synthesis report chooses synthesis in the sources window.
12. In process window expand the implement design expand synthesis XST double click on view synthesis
Report.

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #9 KKU-CS-CE

Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity updowncounter is
Port ( clk, direction: in STD_LOGIC;
cout: out STD_LOGIC_VECTOR (2 downto 0));
end updowncounter;
architecture Behavioral of updowncounter is
signal cin : std_logic_vector(2 downto 0) := "000";
begin
process(clk)
begin
if clk='1' and clk'event then
if direction='1' then
cin<= cin + 1;
else
cin <= cin - 1;
end if;
end if;
end process;
cout<= cin;
end Behavioral;

Timing Diagram:

Lab Exercise:
1. Write a VHDL program to simulate a decade counter using behavioral modeling and generate a synthesis
Report.

Cout[3]

clk
decade Cout[2]
counter Cout[1]
Cout[0]

Hint: The counter counts binary number from (0-9) in ascending order.

Computer Engineering Department- Syed Asif Basha Page-

CPE 421-Integrated Circuit Design Lab Manual- Experiment #10 KKU-CS-CE

Experiment #10
BCD to 7-Segment Decoder
Aim: To Implement a bcd to 7-segment decoder using Xilinx ISE
Objective: Write a VHDL program to simulate a bcd to 7-segment decoder using behavioral modelling
and generate a synthesis Report.
Software Used: Xilinx ISE 8.2i

Theory: A bcd to 7segment display is a combinational logic circuit, in which the input is a bcd number
from 0-9 and the output is a 7segment code to display the corresponding number on a 7segment display as
shown below.

Procedure:
1. Double click on Xilinx ISE 8.2i Design Suit icon on the Desktop.
2. Click on file New project Enter the project name & Location, Select top level source type as HDL. Click
NextNext click on New Source select VHDL Module write Module Name Next write input and
output ports and Finish.
3. Click Next Next Next Finish.
4. Type program in the work space window and save the program.
5. In the sources window choose behavioral simulation.
6. In the process window expand the + symbol on Xilinx ISE Simulator Double click on check syntax.
7. After successful verification of syntax double click on simulate behavioural model.
8. Add an appropriate test bench waveform from the project new source choose test bench Waveform name
the test bench waveform next Finish.
9. select appropriate test bench input waveform save.
10. In the process window expand the + symbol on Xilinx ISE Simulator Double click on Generate expected
Simulation results yes yes.
11. To view synthesis report chooses synthesis in the sources window.
12. In process window expand the implement design expand synthesis XST double click on view synthesis
Report.

Computer Engineering Department- Syed Asif Basha Page-

CPE 421-Integrated Circuit Design Lab Manual- Experiment #10 KKU-CS-CE
Program:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bcd_7seg is
Port (bcd: in std_logic_vector(3 downto 0);
zero_blank : in std_logic;
disp: out std_logic_vector(6 downto 0);
zero_blank_out: out std_logic);
end bcd_7seg;
architecture Behavioral of bcd_7seg is
begin
process(bcd, zero_blank)
begin
case bcd is
when"0000" =>
if zero_blank ='1' then
disp <= "0000000";
zero_blank_out <= '1';
else
disp <= "1111110";
end if;
when"0001" => disp <= "0110000";
when"0010" => disp <= "1101101";
when"0011" => disp <= "1111001";
when"0100" => disp <= "0110011";
when"0101" => disp <= "1011011";
when"0110" => disp <= "1011111";
when"0111" => disp <= "1110000";
when"1000" => disp <= "1111111";
when others=> disp <= "1001111";
end case;
end process;
end Behavioral;
Timing Diagram:
U

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CPE 421-Integrated Circuit Design Lab Manual- Experiment #11 KKU-CS-CE

Experiment #11
Finite State Machine
Aim: To Implement a finite state machine using behavioral modeling in Xilinx ISE
Objective: Write a VHDL program to simulate the mealy state machine described by the following state
diagram using behavioral modeling and generate a synthesis Report.

Software used: Xilinx ISE 8.2i

Theory:
Finite State Machine (FSM): A finite state machine (FSM) or simply a state machine, is a sequential machine with
"random" next-state logic used to implement functions that are realized by carrying out a sequence of steps. It is
commonly used as a controller in a large system. It has finite number of states.
2-types: 1.Mealy state Machine 2.Moore state Machine

Mealy state Machine:

Outputs of Mealy machines are a function of the present state and all the inputs.
Outputs transistors are asynchronous to the clock (They change immediately when the inputs change)
A Mealy machine works one clock cycle in advance of a Moore machine
Moore state Machine:
Outputs of Moore machine are functions of the present state only
Output transitions are synchronous to system clock
Propagation delay through output logic nevertheless leads to asynchronous outputs which can lead to slower operating
frequencies

Procedure:
1. Double click on Xilinx ISE 8.2i Design Suit icon on the Desktop.
2. Click on file New project Enter the project name & Location, Select top level source type as HDL. Click
NextNext click on New Source select VHDL Module write Module Name Next write input and
output ports and Finish.
3. Click Next Next Next Finish.
4. Type program in the work space window and save the program.
5. In the sources window choose behavioral simulation.
6. In the process window expand the + symbol on Xilinx ISE Simulator Double click on check syntax.
7. After successful verification of syntax double click on simulate behavioural model.
8. Add an appropriate test bench waveform from the project new source choose test bench Waveform name
the test bench waveform next Finish.
9. select appropriate test bench input waveform save.
10. In the process window expand the + symbol on Xilinx ISE Simulator Double click on simulate behavioral model
yes yes.
11. To view synthesis report chooses synthesis in the sources window.
12. In process window expand the implement design expand synthesis XST double click on view synthesis
Report.

Computer Engineering Department- Syed Asif Basha Page-

CPE 421-Integrated Circuit Design Lab Manual- Experiment #11 KKU-CS-CE
Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mealy is
port (clk,x: in STD_LOGIC;
z: out STD_LOGIC);
end mealy;
architecture Behavioral of mealy is
type state_type is (S0,S1,S2);
signal state:state_type:=S0;
begin
process (clk,state,x)
begin
if clk'event and clk = '1' then
case state is
when S0 =>
if x = '0' then z <= '0'; state <= S0;
elsif x = '1' then z <= '1'; state <= S2;
end if;
when S1 =>
if x = '0' then z <= '0'; state <= S0;
elsif x = '1' then z <= '0';state <= S2;
end if;
when S2 =>
if x = '0' then z <= '1'; state <= S2;
elsif x = '1' then z <= '0';state <= S1;
end if;
end case;
end if;
end process;
end Behavioral;
Timing Diagram:

Lab Excercise: Write a VHDL program to simulate the mealy state machine described by the following
state diagram using behavioral modeling and generate a synthesis Report.

Computer Engineering Department- Syed Asif Basha Page-

CE421: Integrated Circuit Design Lab Manual- Refrences KKU-CS-CE

References

1. Douglas L. Perry,VHDL Programming By Example,4th Edition,McGraw-Hill 2002.

2. Stephen Brown,Zvonko Vranesic,Fundamentals of Digital Logic with VHDL,3rd Edition,McGraw-Hill 2008.
3. Jayaram Bhasker ,A VHDL Primer,Prentice Hall,3rd Edition 1999.
4. M.H. Hassan,Fundamentals of Digital Logic Design with VHDL, Create Space Independent Publishing Platform,1st
Edition 2015.
5. Erik Brunvand,Digital VLSI Chip Design with Cadence & Synopsys CAD Tools, Pearson, 1st Edition 2009.
6. Mohammed Ferdjallah,Introduction to Digital Systems: Modeling, Synthesis, & Simulation Using VHDL, Wiley,1st Edition
2011.
7. Sung-Mo Kang and Yusuf ,CMOS Digital Integrated Circuits Analysis & Design, McGraw-Hill Education, 4th Edition
2014.

Computer Engineering Dept. Syed AsifBasha