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EE Department
CIIT, Lahore
Lab Instructor
M Ali Raza
EE Department
Objectives:
In this Lab you will be able to:
CIIT, Lahore
Lab Instructor
M Ali Raza
EE Department
Introduction
Nios II System
The Nios II processor can be used with a variety of other components to form a complete
system. These components include a number of standard peripherals, but it is also
possible to define custom peripherals. Alteras DE2-70 Development and Education
board contains several components that can be integrated into a Nios II system. An
example of such a system is shown in Figure 1.
CIIT, Lahore
Lab Instructor
M Ali Raza
EE Department
The Nios II processor and the interfaces needed to connect to other chips on the DE2-70
board are implemented in the Cyclone II FPGA chip. These components are
interconnected by means of the interconnection network called the Avalon Switch Fabric.
Memory blocks in the Cyclone II device can be used to provide an on-chip memory for
the Nios II processor. They can be connected to the processor either directly or through
the Avalon network. The SRAM and SDRAM memory chips on the DE2-70 board are
accessed through the appropriate interfaces. Input/output interfaces are instantiated to
provide connection to the I/O devices used in the system. A special JTAG UART
interface is used to connect to the circuitry that provides a Universal Serial Bus (USB)
link to the host computer to which the DE2-70 board is connected. This circuitry and the
associated software is called the USB-Blaster. Another module, called the JTAG Debug
module, is provided to allow the host computer to control the Nios II processor. It makes
it possible to perform operations such as downloading programs into memory, starting
and stopping execution, setting program breakpoints, and collecting real-time execution
trace data.
Since all parts of the Nios II system implemented on the FPGA chip are defined by using
a hardware description language, a knowledgeable user could write such code to
implement any part of the system. This would be an onerous and time consuming task.
Instead, one can use the Qsys tool in the Quartus II software to implement a desired
system simply by choosing the required components and specifying the parameters
needed to make each component fit the overall requirements of the system.
CIIT, Lahore
Lab Instructor
M Ali Raza
EE Department
Qsys Tool
Qsys is a powerful system integration tool which is included as part of the Quartus II
software. Qsys captures system level hardware designs at a relatively high level of
abstraction and also automates the task of defining and integrating customized HDL
components, which may include IP cores, verification IP, and other design modules. Qsys
facilitates design reuse by packaging and making available your custom components and
systems. Qsys integrates your custom components with Altera and third-party developer
components. In some cases, you can implement an entire design using components from
the Altera component library. During system generation, Qsys automatically creates highperformance interconnect logic from the connectivity options you specify, eliminating the
error-prone and time-consuming task of writing HDL to specify the system-level
connections.
Qsys provides the following advantages for hardware system design:
CIIT, Lahore
Lab Instructor
M Ali Raza
EE Department
On-chip memory
JTAG UART
ALTPLL
System ID peripheral
You use Qsys to generate the Nios II processor system, adding the desired components,
and configuring how they connect together. To create a new Qsys system, click Qsys on
the Tools menu in the Quartus II software. Qsys starts and displays the System Contents
tab as shown in figure 2.
CIIT, Lahore
Lab Instructor
M Ali Raza
EE Department
CIIT, Lahore
Lab Instructor
M Ali Raza
EE Department
Clock Settings
On the Clock Settings tab shown in figure 2, double-click the clock frequency in the MHz
column for clk_0 is the default clock input name for the Qsys system. The frequency you
specify for clk_0 must match the oscillator that drives the FPGA. Type the clock
frequency and press Enter.
Next, you begin to add hardware components to the Qsys system. As you add each
component, you configure it appropriately to match the design specifications.
CIIT, Lahore
Lab Instructor
M Ali Raza
EE Department
7. In the Name column of the system contents table, right-click the on-chip memory and
click Rename.
8. Type onchip_mem and press Enter.
CIIT, Lahore
Lab Instructor
M Ali Raza
EE Department
CIIT, Lahore
10
Lab Instructor
M Ali Raza
EE Department
3. Enter your desired frequency in the frequency tab in the editor window.
4. Select the output clocks tab, and select the output clock frequency by check the box
shown in figure 5.
5. Click Finish. You return to the Qsys System Contents tab, and an instance of the
ALTPLL appears in the system contents table.
6. In the Name column, right-click the altpll_0 and click Rename.
7. Type pll_0 and press Enter.
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Lab Instructor
M Ali Raza
EE Department
CIIT, Lahore
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Lab Instructor
M Ali Raza
EE Department
10. Double-click the Nios II processor row of the system contents table to reopen the
Nios II Processor parameter editor.
11. Under Reset Vector, select onchip_mem.s1in the Reset vector memory list and type
0x0 in the Reset vector offset box.
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Lab Instructor
M Ali Raza
EE Department
Figure 7: Caches and Memory Interfaces tab of the Nios II Processor parameter editor
12. Under Exception Vector, select onchip_mem.s1in the Exception vector memory list
and type 0x20in the Exception vector offset box.
13. Click the Caches and Memory Interfaces tab. Figure 7 shows the GUI.
14. In the Instruction cache list, select 2Kbytes.
15. In the Burst transfers list, select Disable.
16. In the Number of tightly coupled instruction master port(s) list, select None.
17. Click Finish. You return to the Qsys System Contents tab.
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Lab Instructor
M Ali Raza
EE Department
CIIT, Lahore
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Lab Instructor
M Ali Raza
EE Department
3. Click Finish. You return to the Qsys System Contents tab, and an instance of the
JTAG UART appears in the system contents table.
4. In the Name column, right-click the JTAG UART and click Rename.
5. Type jtag_uart and press Enter.
6. Connect the c0 port of the pll to the clk port of the JTAG UART
7. Connect the data_master port of the Nios II processor to the avalan_jtag_slave port of
the JTAG UART.
8. Connect the interrupt port of the Nios II processor to the interrupt port of the JTAG
UART.
Add the System ID Peripheral
The system ID peripheral safeguards against accidentally downloading software
compiled for a different Nios II system. If the system includes the system ID peripheral,
the Nios II SBT for Eclipse can prevent you from downloading programs compiled for a
different system.
Perform the following steps to add the system ID peripheral:
1. On the Component Library tab, expand Peripherals, expand Debug and Performance,
and then click System ID Peripheral.
2. Click Add. The System ID Peripheral parameter editor appears shown in figure 9.
3. Click Finish. You return to the Qsys System Contents tab, and an instance of the
system ID peripheral appears in the system contents table.
4. In the Name column, right-click the system ID peripheral and click Rename.
5. Type sysid and press Enter.
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Lab Instructor
M Ali Raza
EE Department
6. Connect the c0 of the pll to the clk port of the system ID peripheral.
.
7. Connect the data_master port of the Nios II processor to the control_slave port of the
system ID peripheral.
CIIT, Lahore
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Lab Instructor
M Ali Raza
EE Department
CIIT, Lahore
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Lab Instructor
M Ali Raza
EE Department
3. Click Generate. The Save changes? dialog box appears, prompting you to save your
design.
4. Type first_nios2_system in the File name box and click Save. The Generate dialog
box appears and system generation process begins.
The generation process can take several minutes. Output messages appear as
generation progresses. When generation completes, the final "Info: Finished: Create
HDL design files for synthesis" message appears. Figure 11 shows the successful
system generation.
CIIT, Lahore
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Lab Instructor
M Ali Raza
EE Department
CIIT, Lahore
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Lab Instructor
M Ali Raza