Proc. of Int. Conf.

on Recent Trends in Signal Processing, Image Processing and VLSI, ICrtSIV

Dual Node CPU Card for Spacecraft

Seema R Karanth1, Shubha G N2 and Kavitha T M3
1,2,3

DonBosco Institute of Technology, Bangalore, India

1
Email: seemakaranth.85@gmail.com
2
Email: shubhagn24@gmail.com
3
Email: kavithatm8004 @gmail.com

Abstract This paper purposes Dual Node Military Standard (MIL STD) 1553B for
Attitude and Orbit Control Electronics (AOCE) of Spacecraft. The existing system is for
only one node for AOCE functions. The major contribution of this paper is to develop a
dual node for AOCE and Telemetry/ Telecommand (TM/TC). In this paper, simulation of
Dual Node MIL STD 1553B for AOCE of Spacecraft is carried out The design is coded
using Very High Speed Integrated Circuits(VHSIC) Hardware Descriptive
Language(VHDL) and targeted on Field Programmable Gate Arrays(FPGA). FPGA
implementation of this design has minimum number of hardware components. The Dual
Node MIL STD 1553B On Board Computer (OBC) configuration is transparent to the
choice of the processor and can be upgraded to more advanced processors in future. The
design is aimed at good performance with improved reliability and flexibility. The design is
compatible with MIL STD 1553 B standards and as well as compatible with one node MIL
STD 1553 B design.
Index Terms MIL STD 1553B, AOCE, TM / TC.

I. INTRODUCTION
The design of Spacecraft electronics has always governed by an overriding concern to minimize power,
weight and volume. With the advent of high speed processors, Application Specific Integrated Circuits
(ASIC)/ FPGA [1], the various functions such as Sensor electronics, command processing, Data Acquisition
and Processing, Attitude and Orbit control, Telemetry and House keeping and Thermal management have
been traditionally allotted to different sub-systems have been integrated into a single Bus Management Unit
(BMU)/On Board Control System (OBCS) framework [2]. The Bus Management Unit (BMU) is a
centralized electronics system interfacing with most of the other subsystems. The total satellite electronics
systems are monitored and controlled by a central processor. The OBC implements the 1553 protocol for
interfacing with other sub-systems of the spacecraft such as Star Sensor, GPS etc, the OBC configuration has
been evolved as a modular framework so that it can be scaled to meet the mission requirements of Small sat/
IRS/ Recovery satellite/ GEOsat programs[3]. The design of the OBC is governed by compact realization at
package level, Minimizing and simplifying routing inter package and intra package harness, Minimal
interfaces at spacecraft level due to 1553 Operational consideration at mission level.
The rest of this paper is organized as follows. Section II describes related work in the area of single node
MIL STD 1553B [4] for Spacecraft. Section III presents our FPGA interface blocks for dual node MIL STD
1553B for AOCE of Spacecraft. Section IV presents the experimental results. Finally, Section V concludes
this paper.
DOI: 03.AETS.2014.5.433
Association of Computer Electronics and Electrical Engineers, 2014

II. RELATED WORK

The NCE-11501 AOCE CPU [5] card has been designed and developed to meet the following changes due to
the enhanced requirements in terms of processing speed and memory. They are Processor change from
MAR281 to MA31750, FPGA for CPU Interface logics instead of ASIC, Addition of MIL STD 1553b
interface, extended program memory upto 128K x 16 bits from 48K x 16 bits earlier, extended RAM upto
24K x16 bits from 16K x 16 bits earlier, EDAC removed for PROM, retained for RAM. In NCE-11-501,
high density RAM is used which will reduce board space requirement. In processor, memory interface
scheme based on direct usage of CPU data bus against FPGA buffered data bus to minimize bus delays in
data to be considered. Memory Management Unit MAR31751 is used to address 8M words in 1750B
mode.
The BMU design team presented the configuration of the advanced BMU [2]. The configuration change
proposed is mainly due to non-availability of space qualified radiation hardened FPGAs. The AOCE
team is in the advanced stage of developing Rad-Hard ASICs [6] for implementing in the next version of
BMU. The main changes in the new BMU design are ASICs instead of FPGA, Redesign of PCBs for Trays
(Subsystems), Interconnection between Trays using Flexible PCB and connectors and Redesign of Sensor
Electronics Trays ( for new sizes)
III. FPGA INTERFACES BLOCKS
The GEC Plessey MA31750 [7] is a single chip microprocessor that implements the full MIL-STD-1750A
Instruction set architecture and option 2 of draft MIL-STD-1750B. The MA31750 offers a considerable
performance by using a 32- bit internal bus structure with a 24*24 bit multiplier and 32- bit ALU. These subsystems allow the MA31750 to perform multi-bit shifts, multiplications, divisions and normalisations in a
fraction of the clock cycles required on machines not having such resources. This is especially true of
floating-point operations, in which the MA31750 excels. Such operations constitute a large proportion of the
Digital Avionics Instruction Set (DAIS) mix and generally a high percentage of many signal processing
algorithms, therefore having a significant impact on system performance. The processor can directly access
64k words of memory in full accordance with MIL STD 1750A mode. This increase to 1Mwords when used
with the optional MA31751 [8] Memory Management Unit (MMU) and the 1750B mode allows the system
memory to be expandable to 8MW.
To interface memory, I/O devices, Memory Management Unit (MMU), and many other logic devices with
CPU, the FPGA [9] chip is used. This contains.
Configuration Register Unit
Interface with MMU, I/O Data Latch
EDAC and FLAG LOGIC
Wait State Logic and Clock generation
ADD bus selection , Decoding Logic for memory and I/O
Data Bus Routing
Interface to MIL STD 1553 Protocol chip
Miscellaneous signals
A. Configuration Register Unit (config_word)
This block provides External Configuration Register interface. The processor to function with a variety of
different system configurations reads this information Bit ON Power-up, MMU_PR_ABn, and
MODE_1750_A_Bn, which are necessary for the system configuration, are made selectable. To read this
external configuration register, the processor generates a signal CONFWn (active low). The 16- bit
information is routed to processor data bus through I/O data lines during read.
B. Interface with MMU (latch_mmu)
This block generates 20- bit address bus, which is used when memory Expansion through MMU is enabled (20bit to access 1MW and 23- bit to access 8MW). Here, Extended Address lines EA [3:10] from the MMU are used
in addition to BA [4:15] to derive the 20-bit address bus, AA [19:0].

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Fig1: Block Diagram of FPGA interfaces

C. I/O Data Latch (io_port)

The I/F provides necessary interface signals to communicate with 1553 chip. The interface signals such as
MBRn_1553_1, MBRn_1553_2, reset signals for Single Error & Double Error Flag Counters and 1553
interrupt signals such as Int_1553_clr_1, Int_1553_clr_2 are realized through an output port.

Fig 2: Functional Schematic of I/O Data Latch

D. EDAC and FLAG logic (edac_inf)

The EDAC [10] logic generates the Check Bits during the Memory Write operation. During Memory Read
operation, it provides the corrected data and flags the Single Error Flag (SEF), if Single- Bit Error occurs. In
case of two-Bit error, it does not correct the data but flags the Double Error Flag (DEF).The EDAC logic can
be enabled by EDACn signal. The EDAC logic gets enabled only for RAM. It provides counters for counting
the occurrence of flags SEF and DEF generated by EDAC.
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Fig 3: Functional Schematic of EDAC Logic

During a memory write cycle, six check bits (CB0-CB5) are generated by eight input parity generators
using the data bits as shown in the truth table below. During a memory read cycle, the 6-bit check word
is retrieved along with the actual data. Error detection is accomplished as the 6-bit check word and the 16bit data word from memory are applied to internal parity generators/checkers. If the parity of all six
groupings of data and check bits is correct, it is assumed that no error has occurred and both error flags
will be low. If the parity of one or more of the check groups is incorrect, an error has occurred and
the proper error flag or flags will be set high. Any single error in the 16-bit data word will change the
sense of exactly three bits of the 6-bit check word. Any single error in 6-bit check word changes the
sense of only that one bit. In either case, the single error flag will be set high while the dual error flag will
remain low. The 2-bit error is not correctable since the parity tree can only identify single bit errors.
Both error flags will be set high when any 2-bit error is detected. Error correction is accomplished by
identifying the bad bit and inverting it.
E. Wait state logic (wait_st_logic)
This block generates the Wait State signal, CPU_RDYn, START_CYCLE, MWRn, MRDn, and IOWRn.
This logic helps processor to interface slower memory and I/O devices. Four selectable wait state provisions
has been provided for both memory and I/O. DUE to EDAC, automatically extra one wait-state is exerted for
RAM write/read operation.

Fig 4: Functional Schematic of Wait state logic

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F. Wait state logic (wait_st_logic)

This block generates the Wait State signal, CPU_RDYn, START_CYCLE, MWRn, MRDn, and IOWRn.
This logic helps processor to interface slower memory and I/O devices. Four selectable wait state provisions
has been provided for both memory and I/O. DUE to EDAC, automatically extra one wait-state is exerted for
RAM write/read operation.

Fig 5: Functional Schematic of Wait state logic

G. Clock Generation (clk_gen)

This block generates following clocks using PCLK i.e... Divide by 120 clock. This is connected as TCLK
input of processor.

Fig 6: Functional schematic of Clock generation

H. ADD Bus Selection and Decoding logic for Memory (mem_decoder)

This generates Memory address lines MA [16: 0], and chip select signals. The chip select signals CS_RAM
[6:1] n_128k, CS_PROM [7:1] n_32k are generated. The signal CS_1553_1 and CS_1553_2 are generated to
access the 1553 bus. The signal RAM_SEL is used to enable the EDAC for RAM only.

Fig 7: Functional Schematic of Memory decoder

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Fig 8: Memory map with MMU

I. Decoding Logic for I/O (io_dec)

This block generates the I/O Chip Selects and IO_DIS signal. To have port address compatibility with
existing AOCE, AOCE_BMUn signal is used. The Chip Select signals are SEF_CSn, DEF_CSn for reading
the single and double error flag counters (SFD and DFD).The IOCS1n is used for generating 1553 interface
signals

Fig 9: Functional Schematic Decoding Logic for I/O

J. Data Bus Routing

It is responsible for generating Bi-Directional data bus for memory. It also provides interface logic for SEF,
DEF counters and Configuration register

Fig 10: Internal Schematic of Data bus routing

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K. Interface to MIL STD 1553 Protocol Chip (int_1553)

This block provides interface for UTMC MIL STD 1553 devices [11]. If UTMC device is to be interfaced
with CPU, the 1553 shared RAM can be the internal DPRAM or the External RAM, determined by the
RAM_INT_EXTn pin. If the CPU and UTMC access external RAM simultaneously, the arbitration logic
gives priority to CPU access. Else, whichever is accessed first gets the priority and the access to the other one
is held. Contention occurs when there are simultaneous requests from CPU to access UTMC registers and
UTMC to access external RAM. Also, contention can occur when both CPU and UTMC try to access the
external RAM.

Fig 11: Functional Schematic of Interface to MIL STD Protocol Chip

When CPU is accessing external RAM and UTMC also tries to access the external RAM, Arbitration logic
generates grant signals accordingly. For the CPU access to the external RAM, CS_1553n_UTMC,
RDn_1553_1/ WRn_1553_1, RDn-1553_2/WRn_1553_2, A1553_EN1, A1553_EN1, A1553_EN2,
D1553_EN_1, D1553_EN2 are generated In case, UTMC is accessing these signals are tri-stated from the
FPGA. DTACKn_1, DTACKn_2 are generated to indicate the close cycle for UTMC device. When CPU
access UTMC registers and UTMC accesses external RAM, the arbitration logic generates the grant signal
for this contention also. When CPUENn_1, CPUENn_2 are granted, accordingly SUM_RBWn_1,
SUMRBWn_2 SUM_REGCSn_1 and SUM_REGCSn_2 are generated. When UTMC is accessing the
external RAM, UTMC will provides A1553_EN1, D1553_EN1, A1553_EN2, D1553_EN2 are generated
and RDn_1553_1, WRn_1553_1, RDn_1553_2, WRn_1553_2 are tri- stated from the FPGA. DTACKn_1,
DTACKn_2 for UTMCs are generated in the FPGA.
IV. EXPERIMENTAL RESULTS
In this paper, simulation results are verified for PROM Read cycle, RAM Read/ Write cycle, IO Read/ Write
cycle, MIL STD 1553B Node 1/ Node 2 Read/ write cycle by CPU, MIL STD 1553B Node 1/ Node 2 Read/
write cycle by UTMC device. In case of PROM Read cycle and RAM Read cycle, the device is reset, then
memory address is read by CPU and MMU generating chip select signals, memory read signal. Once
memory read signal is generated, data is read from data bus of memory to CPU data bus. After completion of
read cycle, CPU Ready signal is generated. In RAM Write cycle, EDAC logic is enabled, which corrects the
single bit error data. During Memory Write cycle, check bits are generated any single error in 6-bit check
word changes the sense of only that one bit. In either case, the single error flag will be set high while the
dual error flag will remain low Any 2-bit error will change the sense of even number of check bits. The
2-bit error is not correctable since the parity tree can only identify single bit errors. Both error flags will
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be set high when any 2-bit error is detected. hree or more simultaneous bit errors cause the EDAC to give
erroneous results.
In case of MIL STD 1553B Node1/ Node2 Read cycles, the system is reset first, then addresses are latched
through address bus on CPU and MMU, generating corresponding chip select signals. During 1553 read
cycle by CPU, address enable signal and 1553 read signal are generated. Fig 15 shows MIL STD 1553B
Node1/ Node2 Write cycles. During 1553 write cycle by CPU, address enable signal and 1553 write
signals are generated. Once 1553 Write signals are generated, now data is ready to write on to CPU
generating data enable signals. Fig 16 shows MIL STD 1553B Node1/ Node 2 Read cycle and Write cycle
by UTMC device. In UTMC Read cycle, once address is being latched and for given read cycle and
Dmarn, Dmackn uses Direct Memory Access, generating Dtackn, Dmagn and Address enable signals. In
UTMC Write Cycle, address enable signal is generated and now data is ready to write on UTMC RAM
thereby generating data enable signal. At the end of Read/ write cycle, CPU ready signal is generated Fig
17 shows I/O read /write cycle. I/O read is similar to PROM Read cycle but generated IODIS signal is
disabled and enables IODIR signal indicating that I/O reads the data CPU data bus. In I/O write cycle,
IOWRn signal is generated.
V. CONCLUSION
This paper presented Dual Node MIL STD 1553B for AOCE of Spacecraft. In this paper architecture and
function of Dual Node MIL STD 1553B have been designed and developed and simulated. The existing
system is only for one node. The main objective of this paper is to develop a Dual Node MIL STD 1553B for
Spacecrafts used for AOCE and TM/TC functions. The designed is coded using hardware descriptive
language i.e. VHDL [12] [13] and is targeted on Field Programmable Gate Arrays (FPGA). The FPGA
implementation of this project has only minimum hardware requirements. The design is aimed at good
performance with improved flexibility and reliability. The design is compatible with MIL STD 1553B
standards and also with only one node MIL STD 1553B design.
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