ABSTRACT

Wavelet Transforms are being adapted for Signal Processing, Image Processing
and Communication applications. One of the major challenges in DWT is the
computation complexity, thus for video compression. This work presents an
implementation of Discrete Wavelet Transform (DWT) using Systolic architecture in
VLSI. This architecture consists of Input delay unit, filter, register bank and control unit.
This performs the calculation of high pass and low pass coefficients by using only one
multiplier.
A detailed analysis of the effect of finite precision of data and wavelet filter
coefficients on the accuracy of the DWT coefficients is presented. This architecture have
been simulated and implemented in VLSI.

The hardware utilization efficiency of this proposed work has been more than
the referred. The systolic nature of this architecture corresponding to a clock speed of N
MHz Optimized area, time and power obtained from this architecture for various
devices. The architecture is simple, modular, and cascadable for computation of one, or
multi-dimensional DWT.

LIST OF FIGURES

Page No.

Fig 1.1

Image Compression Model

Fig1.2

Image Decompression Model

Fig2.1

Fourier analysis

Fig2.2

Short-Time Fourier analysis

Fig2.3

Wavelet Analysis

Fig2.4

Comparison of time-based, frequency-based and STFT

Fig2.5

Sine wave

Fig2.6

Sinusoidal Signal

10

Fig2.7

Fourier coefficients and wavelet coefficients

10

Fig2.8

Continuous Wavelets of different frequencies

12

Fig2.9

Continuous Wavelets of different scales and positions

12

Fig2.10

Mother Wavelet and its scaled versions

14

Fig2.11

Scaling Sinusoid Signal

16

Fig2.12

Scaling Wavelet

16

Fig2.13

Shifting Wavelet

17

Fig2.14

One-Stage Decomposition

18

Fig2.15

Two-Stage Decomposition

18

Fig2.16

Importance of Low Frequency Signal

19

Fig2.17

Decomposition and Reconstruction

19

Fig2.18

Reconstruction Filters

21

Fig 2.19

Reconstruction of Samples

21

Page No.
Fig 2.20

Reconstruction of Approximation signal

22

Fig 2.21

Reconstruction of Details signal

22

Fig 2.22

Reconstruction of Signal Components

23

Fig 2.23

Wavelet Function Position

24

Fig 2.24

Fourier basis functions

26

Fig2.25

Daubechies wavelet basis functions

27

Fig3.1

Three stage DWT decomposition using pyramid algorithm 29

Fig3.2

(a) Wavelet transforms decomposition of an image into

4 sub-images. (b) A three level image decomposition

Fig 3.3

Ideal DWT coefficients and errors due to 12 bit precision

of coefficients for step input.

Fig 3.4

35

Ideal DWT coefficients and errors due to 12 bit precision

of coefficients for sinusoidal input.

Fig 3.5

37

Performance variation with respect to filter

Coefficient precision

Fig 3.6

30

37

Performance variation with respect to a) filter coefficients and

b) DWT coefficients precision.

38

Fig 4.1

Example of two dimensional systolic array

39

Fig 4.2

Example of systolic array

40

Fig 5.1

DWT-SA Architecture

Fig 5.2

The systolic architecture of a six tap filter

44
45

Page No.
Fig 5.3

Proposed Filter Cell

46

Fig 5.4

The Control Unit

49

Fig 5.5

Flow chart of entire project

51

Fig 5.6

Flow chart of proposed architecture

52

Fig 6.1

Input Image

53

Fig 6.2

Modelsim output of implemented DWT

54

Fig 6.3

Output from Matlab after performing DWT

55

Fig 6.4

Synthesis report of design

56

Fig 6.5

Schematic view of design

57

LIST OF TABLES
Page No.

Table1

Dynamic range of DWT coefficients for various stages

33

Table2

Scaling factors: to obtain the ideal coefficients

33

Table3

Schedule for one complete set of computations

47

Table4

Activity periods for intermediate results

48

Table5

Comparison of Systolic DWT with Lifting DWT

56

TERMINOLOGY
Description
FRA

Forward Register Allocation

FBRA

Forward Backward Register Allocation

CU

Control Unit

RB

Register Bank

ID

Input Delay

SA

Systolic Array

FU

Filter Unit

MHz

Mega Hertz

FC

Filter Cell

MAC

Multiplication & Accumulation

CWT

Continuous Wavelet Transform

PE

Processing Element

DWT

Discrete Wavelet Transform

VLSI

Very Large Scale Integrated Circuit

MODELSIM

Model Simulator

DCT

Discrete Cosine Transform

VHDL

VHSIC hardware description language

ISE

Integrated Software Environment