www.universityquestions.in Reg. No.: Question Paper Code : 44130 M.E. DEGREE EXAMINATION, MAY/JUNE 2015. Third Semester ‘VISI Design ‘VL 7301 — TESTING OF VLSI CIRCUITS (Common to M.E. Applied Electronics) Regulation 2018) ‘Time : Three hours WWW-UNiversityquestions.in ypocisum : 100 marks Answer ALL questions. PART A— (10 x 2=20 marks) 1. State the lemma rale. 2. What are the types of fault models? 3. Draw the hardware model for delay fault testing. 4. Mention any four methods used in test generation for combinational circuits. 5. Define two important attributes to testability. 6. Whatare the various LSSD Design rules? 7. What are the advantages and disadvantages of Exhaustive testing? 8. List the types of coupling faults exist in memories. 9. Give the flowchart of testing and diagnosis process in COMET. 10. Enlist the merits of guided probe testing. ‘ww.universityquestions.in1 www.universityquestions.in PART B — (5 x 16=80 marks) (®) Discuss on the various types of fault simulation techniques used in digital cirenits. (6) Or ©) (i) Explain any two delay models with suitable example. ® (ii) Prove thet in a combinational circuit, if two faults dominate each other, then they are functionally equivalent. ®) 12. (@) Explain PODEM algorithm and using PODEM, find a test vector for the 18. fault ‘X S/O’ in the circuit shown in Figure—1. (6) 5 < x9 = q e Figure 1 Or ) @ Using the five logic values of the D-Algorithm, the consistency check works as follows: Let u' be the value to be assigned to a line and v be its current value. Then wv’ and v are consistent if v = x or » =v’. Formulate a consistency check for the 9-V algorithm. (10) . (ii) Determine the primitive cubes and the propagation D-cubes for an exclusive-OR module with two inputs. ©) () Explain the following rules of Adhoc Design for testability with suitable examples : (@ Disable internal one-shots during test. i) Partition large counters and shift registers into smaller units. (i) Avoid the use of redundant logic. (16) Or (®) Briefly explain the various types of Generic sean based designs in detail. a6) www.universityquestions.in 2 4413014 (a) (b) 18. (a) tb) www.universityquestions.in Discuss the fault models used in memories and explain how test generation is done for Embedded RAM. 16) Or Explain with neat circuit diagram, the different types of BIST architectures available and list out each advantages and disadvantages (16) Coneider a system whose diagnostic graph has 5 nodes {0, 1, 2, 3, 4} and an edge from { to (+ 1) mod 6 and from é to (i+ 2) mod 5 for all i (Prove that ouch a system is one-step two-fault diagnosable and sequentially two-fault diagnosable. (ii) What is the maximum number of edges that can be removed from this graph so that it is still one-step two-fault diagnosable, or so that itis still sequentially two-fault diagnosable? (16) Or @ Consider a 7 bit Hamming single-error correction code. For each of the following, assuming almost a single bit error, determine the erroneous bit if any. 0101100, 0101101, 0111101. @) (i) Prove that Berger codes detect all unidirectional errors. @ 3 44130