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Q1/
Instruction Execution Cycle :
the
, oae v e eo eamat
2- Indirect
mode:
3- index mode:
the
address
of
the
operand
is
obtained
by
adding
4- Relative mode:
is the same as indexed addressing except that the program counter
(PC) replaces the index register.
5- Autoincrement mode:
uses a register to hold the address of the operand.
Q/
Cache ::
instructions and data the processor has recently used. Thanks to its
proximity to the main computing engine inside the processor
of
the
way
most
time
software
works,
processors
eor eeample, when you hit the uacs button on your browser, the seb
paie loaes almost instantly because the files the browser neees are
nearby
If their is no cash or empty cash in browsers?????
it going back to the previous page would take just as long as when you
called it up in the first place.
L1 AND L2 IS :
E o amuma et
om a
ami
em
ommimommoeam dm eom i e maae . Tom ewe amumaa mtm ee oew aeam eom
om a ioma
i e maae
L2
2MB (
L2 IIS
IIIs 512KB .
Q/Interrupt can divide to five groups or what is the group that the
interrupt can divide to ?
1.hardware interrupt
2.Non-maskable interrupt
3.Software interrupt
4.Internal interrupt
5.Reset
!
Hardware interrupt : The primary sources of interrup
The 8259A programmable interrupt: controller chip accepts interrupts
from up to eight different devices. If any one of the devices requests
service,