RAJALAKSHMI ENGINEERING COLLEGE

LESSON PLAN UNIT-III

Faculty Name K.Poornimathi Faculty Code IT116 21 Fundamental Concepts-Processor 412-420
Subject Name Computer Architecture Subject code CS1251 22 Execution of complete instruction, 421-422
Class III year ECE ‘A’ & ‘B’ Date of Compilation 25-11-09 23 multiple bus organization 423-424
DEFINITION 24 Hardwired control 425-428
 Study of basic structure of a digital computer and the organization of the
25 Microprogram Control 429-443
Control unit, the Arithmetic and Logical unit, the Memory unit and the I/O
unit 26 Pipelining ,Basic concepts 454-458
OBJECTIVES 27 Data Hazards 461-464
 To have a thorough understanding of the basic structure and operation of a 28 Instruction Hazards 465-476
digital computer. 29 Instruction Hazards 465-476
 To discuss in detail the operation of the arithmetic unit including the 30 Influence on instruction sets, data path 476-480
algorithms & implementation of fixed-point and floating-point addition, and control consideration
subtraction, multiplication & division. 31 Superscalar operation 481-486
 To study in detail the different types of control and the concept of pipelining. UNIT-IV
 To study the hierarchical memory system including cache memories and 32 Basic concepts-Memory system 292-294
virtual memory. 33 Semiconductor RAM, Speed ,size & 295-308
 To study the different ways of communicating with I/O devices and standard cost
I/O interfaces. 34 ROM, Speed, size & cost 309-313
35 Cache memory, Performance 314-336
S.No Date Period Topic Page No consideration
UNIT- I 36 Basic concepts-Memory system 292-294
1 Functional Units 3-6 37 Semiconductor RAM, Speed ,size & 295-308
2 Basic operational concepts 7-8 cost
3 Bus structure, Software performance 9-18 38 Virtual memory 337-342
4 Memory location & addressing 33-36 39 Memory management requirements 343-344
5 Memory operations 37 40 Secondary storage 344-358
6 Instruction & instruction Sequencing 38-47 UNIT V
7 Addressing Modes 48-57 41 Accessing I/O devices 204-207
42 Interrupts 208-223
8 Assembly language 58-64
43 DMA 234-239
9 Basic I/O operations 65-67
44 Buses 240-247
10 Stacks & Queues 68-71
45 Interface circuits 248-258
UNIT-II 46 Standard I/O Interfaces PCI 259-265
11 Addition & subtraction of signed 368-369 47 SCSI 266-271
numbers 48 USB 272-282
12 Design of Full Adder 371-375 49 Accessing I/O devices 204-207
13 Design of Full Adder 371-375
14 Multiplication of positive number 376-379 TEXTBOOKS
15 Signed operand multiplication and Fast 380-389 1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, 5th Edition ,
multiplication Computer Organization”, McGraw-Hill, 2002.
16 Signed operand multiplication and Fast 380-389 REFERENCES
multiplication 1. William Stallings, “Computer Organization and Architecture – Designing
17 Integer division, 390-393 for Performance”, 6th Edition, Pearson Education, 2003.
18 Floating point number and Operation 394-402 2. David A.Patterson and John L.Hennessy,“Computer Organization and
design: The hardware / software interface”, 2nd Edition, Morgan Kaufmann,
19 Design of Full Adder 371-375
2002.
20 Design of Full Adder 371-375
3. John P.Hayes, “Computer Architecture and Organization”, 3rd Edition,
McGraw-Hill, 1998

Signature of Faculty Signature of HOD