CCE 529 Lect 2 (New)

CCE 514 Computer Architecture – 3 Units
Lecture 2
Engr. Dr. Christopher U. Ngene, Dept. of Communication and Computer Engineering, ATBU , email:ngene@unimaid.edu.ng 1
MICROCONTROLLERS: AN
INTRODUCTION
 A microcontroller (or MCU) is a special-purpose computer-on-a-
chip . As a computer it has a CPU.
 Features of MCU
 dedicated to one task and run one specific program.
 MCU are often low-power devices. A desktop computer is almost always
plugged into a wall socket and might consume 50 watts of electricity. A battery-
operated MCU might consume 50 milliwatts.
 has a dedicated input device and May or may contain a small LED or LCD
display for output.
 Takes input from the device it is controlling and controls the device by sending signals to
different components in the device.
 For example, the microcontroller inside a TV takes input from the remote control and
displays output on the TV screen. The controller controls the channel selector, the speaker
system and certain adjustments on the picture tube electronics such as tint and
brightness.
 integrates memory (ROM and RAM) and input-output interfaces
MICROCONTROLLERS: AN
INTRODUCTION...
 Processors used in MCU. The actual processor used to implement
a microcontroller can vary widely
 The Z-80 is an 8-bit microprocessor
 Some designs include general-purpose microprocessor cores, with one or
more ROM, RAM, or I/O functions integrated onto the package.
 Types of MCU
 The Motorola 6811
 Intel 8051
 PIC microcontrollers" created by a company called Microchip.
 e.t.c.
MCU Chips
 Broad Classification of different microcontroller chips could be as
follows
 Embedded (Self -Contained) 8 - bit Microcontroller
 16- to 32-bit Microcontrollers
 Digital Signal Processors
 Features of Modern MCU

 Built-in Monitor Program
 Built-in Program Memory
 Interrupts
 Analog I/O
 Serial I/O
 Facility to Interface External Memory
 Timers
Internal Structure of a MCU
Power
Control Store
Power Distribution
ROM
Reset Reset and

I/O Pins
Control
ALU
I/O
and e
Clocking P
Clock and O
Registers
Timing R
T
S
External External
Peripherals e
Interrupts Memory
Interrupt
Circuits
Internal RAM
Princeton Architecture
 Single memory interface
Instruction Decoder
Example : An instruction "Read a data
byte from memory and store it in the
Program
accumulator" is executed as follows: -
ROM
Data
Cycle 1 - Read Instruction
Address Memory
Interface Processor Cycle 2 - Read Data out of RAM
Unit and and put into Accumulator
Built-in
Registers
RAM Control
CPU
Harvard Architecture
 Separate Program and Data Memory interfaces
Data
Instruction Decoder
Address
Control
Register
Program Space/Data
ROM PC Stack Memory
RAM
Data
Processor
and Address
Register Interface
Control
CPU
Harvard Architecture...
The same instruction (as shown under Princeton
Architecture) would be executed as follows:
Cycle1
 Complete previous instruction
 Read the "Move Data to Accumulator" instruction
Cycle 2
 Execute "Move Data to Accumulator" instruction
 Read next instruction
Hence each instruction is effectively executed in one

instruction cycle
 Exception: Instructions that modify the content of the program
counter. For example, the "jump" (or call) instructions takes 2 cycles.
Thus, due to parallelism, Harvard architecture executes more
instructions in a given time compared to Princeton Architecture.
Microprocessor vs Microcontroller
 Microprocessor :
 requires an external memory for program/data storage.
 Instruction execution requires movement of data from the external memory to
the microprocessor or vice versa.
 Usually, microprocessors have good computing power and they have higher
clock speed to facilitate faster computation.
 Microcontroller :
 has required on-chip memory with associated peripherals. A microcontroller can
be thought of a microprocessor with inbuilt peripherals.
 does not require much additional interfacing ICs for operation and it functions
as a standalone system. The operation of a microcontroller is multipurpose.
 are also called embedded controllers. A microcontroller clock speed is limited
only to a few tens of MHz. Microcontrollers are numerous and many of them are
application specific.
Intel 8051 Family Features

 The 8051 is one of the most popular microcontrollers in use today.
Many derivative microcontrollers have since been developed that are
based on--and compatible with--the 8051
Device Internal Memory 16-Bit Interrupts Full

Timer/Event Duplex
Data Program Counter I/O
8031 128 x 8 RAM None 2 x 16-Bit 5 1

8032 256 x 8 RAM none 2 x 16-Bit 6 1
8051 128 x 8 RAM 4k x 8 ROM 2 x 16-Bit 5 1
8052 256 x 8 RAM 8k x 8 ROM 3 x 16-Bit 6 1
8751 128 x 8 RAM 4k x 8 EPROM 2 x 16-Bit 5 1
8752 256 x 8 RAM 8k x 8 EPROM 3 x 16-Bit 6 1
AT89C51 128 x 8 RAM 4k Flash Memory 2 x 16-Bit 5 1
AT89C52 256 x 8 RAM 8k Flash memory 3 x 16-Bit 6 1
Intel 8051 MCU:Block Diagram

External Interrupts
Timer 1 Counter
Interrupt 4K ROM 128 Bytes Inputs
Control RAM Timer 0
CPU
Bus Serial
Oscillator 4 I/O Ports
Control Port
P0 P2 P1 P3 TXD RXD
Address/Data
8051 MCU...
 The 8051 MCU family are 8-bit units which can address 64 Kbytes of
memory
 All of the family members have some RAM on the chip and different
members of the family have some ROM or EPROM also included on
the chip
 If an application does not require any memory other the on-chip, then
all 4 ports are available for use as input or output ports.
 If additional memory is needed, then port 0 and port 2 can be programmed to
function as a multiplexed address/data bus.
 When used with external memory, 2 lines on port 3 are used to generate the
and signals
RD WR
Various Features of 8051

8051 employs Harvard architecture. It has some peripherals such as
32 bit digital I/O, Timers and Serial I/O
 8-bit CPU
 16-bit Program Counter
 8-bit Processor Status Word (PSW)
 8-bit Stack Pointer
 Internal RAM of 128bytes
 Special Function Registers (SFRs) of 128 bytes
 32 I/O pins arranged as four 8-bit ports (P0 - P3)
 Two 16-bit timer/counters : T0 and T1
 Two external and three internal vectored interrupts
 One full duplex serial I/O
8051 Clock and Instruction Cycle

 In 8051, one instruction cycle consists of twelve (12) clock cycles.
Instruction cycle is sometimes called Machine cycle
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
S1 S2 S3 S4 S5 S6
One Instruction Cycle
 In 8051, each instruction cycle has six states (S 1 - S 6 ).

 Each state has two pulses (P1 and P2)
8051 Memory
 The 8051 has three very general types of memory.
 On-Chip Memory,
 External Code Memory, and
 External RAM.
 On-Chip Memory refers to any memory (Code, RAM, or other) that
physically exists on the microcontroller itself. On-chip memory can
be of several types.
 External Code Memory is code (or program) memory that resides
off-chip. This is often in the form of an external EPROM.
 External RAM is RAM memory that resides off-chip. This is often in
the form of standard static RAM or flash RAM.
8051 Memory: Code Memory

 Code memory is the memory that holds the actual 8051 program that
is to be run.
 This memory is limited to 64K and comes in many shapes and sizes:
 Code memory may be found on-chip, either burned into the microcontroller as
ROM or EPROM.
 Code may also be stored completely off-chip in an external ROM or, more
commonly, an external EPROM.
 Flash RAM is also another popular method of storing a program.
 However, code memory is most commonly implemented as off-chip
EPROM.
 This is especially true in low-cost development systems and in systems
developed by students.
8051 Memory: External RAM

External RAM is any random access memory which is
found off-chip.
Since the memory is off-chip it is not as flexible in terms of
accessing, and is also slower. For example,
 to increment an Internal RAM location by 1 requires only 1
instruction and 1 instruction cycle.
To increment a 1-byte value stored in External RAM requires 4
instructions and 7 instruction cycles. In this case, external memory
is 7 times slower!
What External RAM loses in speed and flexibility it gains in
quantity.
 While Internal RAM is limited to 128 bytes (256 bytes with an
8052), the 8051 supports External RAM up to 64K.
8051 Memory: On-Chip Memory

 On-chip memory is really one of two types:
 Internal RAM and
 Special Function Register (SFR) memory.
iRAM Description
Addr R – Register
00 R0 – Register 0
R0 R1 R2 R3 R4 R5 R6 R7 Reg- Bank 0
08
R0 R1 R2 R3 R4 R5 R6 R7 Reg- Bank 1 Internal RAM (iRAM)
10
R0 R1 R2 R3 R4 R5 R6 R7 Reg- Bank 2 • fastest RAM available,
18
R0 R1 R2 R3 R4 R5 R6 R7 Reg- Bank 3 • most flexible in terms of reading,
20
Bits- 00 – 3F
writing, and modifying its contents.
00 08 10 18 20 28 30 38
28 • iRAM is volatile, so when the 8051 is
40 48 50 58 60 68 70 78 Bits- 40 – 7F
30 reset this memory is cleared.
General User RAM & Stack Space
(80 bytes, 30h – 7Fh) General iRAM
7F
80
: Special Function Registers (SFRs) SFRs
(80 bytes, 30h – 7Fh)
:
8051 Memory: Register Banks

 The 8051 has four distinct register banks (Bank 0 – Bank 3)
 Each register bank contains 8 registers ‘R’
 These registers are numbered from 0 through 7 (R0, R1, ... R7)
 Each register is 8-bit wide
 These registers are generally used to assist in manipulating values and moving data from
one memory location to another
 When the 8051 is first booted up, register bank 0 (addresses 00h through 07h) is
used by default.
 However, your program may instruct the 8051 to use one of the alternate register
banks; i.e., register banks 1, 2, or 3.
 Address of registers:
 Bank 0
 R0 = 00h, R1 = 01h, R2 = 02h, R3 = 03h, R4 = 04h, ....., R7 = 07h
 Bank 1
 R0 = 08h, R1 = 09h, R2 = 0Ah, R3 = 0Bh, R4 = 0Ch, ....., R7 = 0Fh
 Bank 2
 R0 = 10h, R1 = 11h, R2 = 12h, R3 = 13Bh, R4 = 14Ch, ....., R7 = 17h
 Bank 3
 R0 = 18h, R1 = 19h, R2 = 1Ah, R3 = 1Bh, R4 = 1Ch, ....., R7 = 1Fh
8051 Memory: Bit Memory
 The 8051, being a communications-oriented microcontroller,

gives the user the ability to access a number of bit variables.
 These variables may be either 1 or 0.
 There are 128 bit variables available to the user, numbered 00h
through 7Fh.
 The user may make use of these variables with commands such
as SETB and CLR.
 For example, to set bit number 24 (hex) to 1 you would execute the
instruction: SETB 24h
 Programming Tip:
 If your program does not use bit variables, you may use Internal RAM
locations 20h through 2Fh for your own use.
 But if you plan to use bit variables, be very careful about using addresses
from 20h through 2Fh as you may end up overwriting the value of your
bits!
128 bytes of Internal RAM Structure (lower CCE 514 Computer Architecture – 3 Units
address space)
7Fh
General
Purpose 80 bytes
30h Area
2Fh
Bit Address 16 bytes
30h Area
1Fh
Register
Bank-3 No. of Bits = 16 x 8 = 128 bytes
18h Bit address 00h – 7Fh
17h
Register
10h Bank-2
0Fh
Register
Bank-1
08h 32 bytes= 8 x 4 bytes
07h R7
Register
Bank-0
R1
00h R0
128 bytes of Internal RAM Structure...
 The lower 32 bytes are divided into 4 separate banks.

 Each register bank has 8 registers of one byte each.
 A register bank is selected depending upon two bank select
bits in the PSW register.
 Next 16bytes are bit addressable. In total, 128bits (16x8) are
available in bit addressable area.
 Each bit can be accessed and modified by suitable instructions.
 The bit addresses are from 00H (lsb of the first byte in 20H) to
7FH (msb of the last byte in 2FH).
 Remaining 80bytes of RAM are available for general purpose.
Internal Data Memory and Special Function
Register (SFR) Map

RAM Area SFRs
FFh
Direct Addressing
Indirect Addressing
SFRs
80h
7Fh Direct/Indirect
Addressing
00h
 The SFRs are mapped in the upper 128 bytes of internal data memory address.
 Hence there is an address overlap between the upper 128 bytes of data RAM and SFRs.
Please note that the upper 128 bytes of data RAM are present only in the 8052 family.
 The lower128 bytes of RAM (00H - 7FH) can be accessed both by direct or indirect
addressing while the upper 128 bytes of RAM (80H - FFH) are accessed by indirect
addressing.
 The SFRs (80H - FFH) are accessed by direct addressing only. This feature
distinguishes the upper 128 bytes of memory from the SFRs, as shown above
SFR Map
 The set of Special Function Registers (SFRs) contains important registers such
as:
 Accumulator (A),
 Register B,
 I/O Port latch registers,
 Stack pointer,
 Data Pointer,
 Processor Status Word (PSW) and various control registers
 Some of these registers are bit addressable
PSW CY AC F0 RS1 RS0 OV - P
 PSW register stores the important status conditions of the microcontroller.

It also stores the bank select bits (RS1 & RS0) for register bank selection
PSW
CY PSW.7 Carry flag.
AC PSW.6 Auxiliary carry flag.
-- PSW.5 Available to the user for general purpose
RS1 PSW.4 Register Bank selector bit 1.
RS0 PSW.3 Register Bank selector bit 0.
OV PSW.2 Overflow flag.
-- PSW.1 User definable bit.
P PSW.0 Parity flag. Set/cleared by hardware each

instruction cycle to indicate an odd/even
number of 1 bits in the accumulator.
PSW: Example
 The flag bits affected by the ADD instruction are CY, P, AC, and OV
Example
Show the status of the CY, AC and P flag after the addition of 38H and 2FH in the following
instructions.
MOV A, #38H
ADD A, #2FH ; after the addition A=67H, CY=0
Solution:
D7..............D0
38 00111000
+ 2F 00101111
67 01100111
CY = 0 since there is no carry beyond the D7 bit
AC = 1 since there is a carry from the D3 to the D4 bi
P = 1 since the accumulator has an odd number of 1s (it has five 1s)
PSW: Example...
Example 2
Show the status of the CY, AC and P flag after the addition of 9CH and
64H in the following instructions.
MOV A, #9CH
ADD A, #64H ; after the addition A=00H, CY=1
Solution:
9C 10011100
+ 64 01100100
100 00000000
CY = 1 since there is a carry beyond the D7 bit

AC = 1 since there is a carry from the D3 to the D4 bi
P = 0 since the accumulator has an even number of 1s (it has zero 1s)
Example
Write a program to save the accumulator in R7 of bank 2.

Solution:
CLR PSW.3
SETB PSW.4
MOV R7,A
SETB PSW.4 CLR PSW.3

7 0
PSW CY AC F0 1 0 OV - P
102  210 ( Bank 2)
SFR Map...
 Some of these registers are bit addressable (they are marked with a * in the diagram below)
 The detailed map of various registers is shown in the following figure.

F8H
F0H B*
E8H
I/O Port SFRs
E0H ACC*
D8H
Control SFRs
D0H PSW*
C8H (T2CON)* (RCAP2L) (RCAP2H) (TL2) (TH2)
Other SFRs
C0H
B8H IP*
B0H P3*
A8H IE*
A0H P2*
98H SCON* SBUF
90H P1*
88H TCON* TMOD TL0 TL1 TH0 TH1
80H P0* SP DPL DPH PCON
8051 Addressing Modes

 The 8051 has four addressing modes.
 Immediate Addressing
 Bank Addressing or Register Addressing
 Direct Addressing
 Register Indirect Addressing

Immediate Addressing
 Data is immediately available in the instruction.
 For example:
ADD A, #77; A 77(decimal) + (A)
ADD A, #4DH; A 4D (hexadecimal) + (A)
MOV DPTR, #1000H; Data pointer 1000 (hexadecimal)
Bank Addressing or Register
Addressing
 This way of addressing accesses the bytes in the current register
bank.
 Data is available in the register specified in the instruction.
 The register bank is decided by 2 bits of Processor Status Word
(PSW).

For example:
 ADD A, R0; A (R0) + (A)
Direct Addressing
 The address of the data is available in the instruction.
For example -
This instruction will read the data out of Internal RAM address
MOV A,30h
30 (hexidecimal) and store it in the Accumulator.
 it is important to note that when using direct addressing any

instruction which refers to an address between 00h and 7Fh is
referring to Internal Memory.
 Any instruction which refers to an address between 80h and FFh is
referring to the SFR control registers that control the 8051
microcontroller itself.
Register Indirect Addressing

 The address of data is available in the R0 or R1 registers as
specified in the instruction.
For example:
MOV A, @R0 moves content of address pointed by R0 to A
 Indirect addressing is also the only way to access the extra 128
bytes of Internal RAM found on an 8052.
 Indirect addressing always refers to Internal RAM; it never refers to

an SFR
External Data Addressing

 Pointer used for external data addressing can be either R0/R1 (256
byte access) or DPTR (64kbyte access).
For example:
 There are only two commands that use External Direct addressing
mode:
 MOVX A, @DPTR Moves content of 8-bit address pointed by R0 to A
 MOVX @DPTR, A Moves content of 16-bit address pointed by DPTR to A
 In these instructions, DPTR must first be loaded with the address of

external memory that you wish to read or write.
External Code Addressing

 Sometimes we may want to store non-volatile data into the ROM
e.g. look-up tables.
 Such data may require reading the code memory. This may be done
as follows -
 MOVC A, @A+DPTR; Moves content of address pointed by A+DPTR to A
 MOVC A, @A+PC; Moves content of address pointed by A+PC to A

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CCE 514 Computer Architecture – 3 Units

 Features of Modern MCU

Reset Reset and

 Single memory interface

Hence each instruction is effectively executed in one

Intel 8051 Family Features

Device Internal Memory 16-Bit Interrupts Full

8031 128 x 8 RAM None 2 x 16-Bit 5 1

Intel 8051 MCU:Block Diagram

Various Features of 8051

8051 Clock and Instruction Cycle

One Instruction Cycle

 In 8051, each instruction cycle has six states (S 1 - S 6 ).

8051 Memory: Code Memory

8051 Memory: External RAM

8051 Memory: On-Chip Memory

8051 Memory: Register Banks

8051 Memory: Bit Memory

 The 8051, being a communications-oriented microcontroller,

 The lower 32 bytes are divided into 4 separate banks.

Register (SFR) Map

PSW CY AC F0 RS1 RS0 OV - P

 PSW register stores the important status conditions of the microcontroller.

AC PSW.6 Auxiliary carry flag.

-- PSW.5 Available to the user for general purpose

RS1 PSW.4 Register Bank selector bit 1.

RS0 PSW.3 Register Bank selector bit 0.

OV PSW.2 Overflow flag.

-- PSW.1 User definable bit.

P PSW.0 Parity flag. Set/cleared by hardware each

CY = 0 since there is no carry beyond the D7 bit

AC = 1 since there is a carry from the D3 to the D4 bi

CY = 1 since there is a carry beyond the D7 bit

Write a program to save the accumulator in R7 of bank 2.

SETB PSW.4 CLR PSW.3

102  210 ( Bank 2)

 The detailed map of various registers is shown in the following figure.

8051 Addressing Modes

ADD A, #77; A 77(decimal) + (A)

ADD A, #4DH; A 4D (hexadecimal) + (A)

MOV DPTR, #1000H; Data pointer 1000 (hexadecimal)

 ADD A, R0; A (R0) + (A)

 it is important to note that when using direct addressing any

Register Indirect Addressing

MOV A, @R0 moves content of address pointed by R0 to A

 Indirect addressing always refers to Internal RAM; it never refers to

External Data Addressing

 In these instructions, DPTR must first be loaded with the address of

External Code Addressing

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