Computer Peripheral Units: Central Processing Unit (CPU)

Computer Peripheral Units
Central Processing Unit (CPU)
Bachelor of Science, Electrical Engineering (Communication and

Automation Engineering)
Dr.-Ing. Ali Diab
Summer Semester 2015
Faculty of Mechanical and Electrical Engineering

(Communication Engineering)
Al Baath University
Department of Computer Engineering and Automation
Outline
• Interconnection of Microcomputer System`s Components
• Central Processing Unit (CPU) Architecture
• Programming Languages
• Instructions Execution
• Instructions Pipelining
• CISC and RISC Processors
2
Interconnection of Microcomputer System`s

Components
3
Computer`s Components
Monitor
System unit
Keyboard
Mouse
• From the functional point of view, each computer consists of

– Memory unit
– CPU unit
– I/O units
4
Interconnection between Computer`s Componentss
• Interconnect via buses, which

– Interconnect memory, I/O devices and CPU
• Three types of buses

– Data bus
– Control bus
– Address bus
5
I/O Units
• I/O devices are connected to the computer via I/O ports
• Each I/O port contains registers, some for data and some for
control
• I/O ports are interfaces between the CPU and the memory as well
as I/O devices
– I/O port between the CPU and the memory has an address
– I/O port between the CPU and any I/O device has no address
• There are two types of I/O ports

– Serial (1 bit per time unit)
– Parallel (8, 16, 32, etc. bits per time unit)
6
I/O Units
• Each I/O unit consists of two main parts

– A mechanical part (the device itself)
– An electronic part (the device controller or adapter)
The device controller (electronic

part). All remaining componets
form the mechanical part
7
I/O Units
The rollers that touch the

ball and detect X and Y
motion (infrared sensors
control these rollers and
send signals to the device
controller)
8
I/O Units
An encoder chip (small

processor) that reads the
pulses coming from the
infrared sensors and turns
them into bytes sent to the
computer.
A button that
detects clicks
9
Central Processing Unit (CPU) Architecture
10
CPU Architecture - Abstract View
Execute following tasks

• Fetch instructions
• Decode instructions
• Fetch data
• Process data
• Write data
Computation unit Control unit
Registers
ALU
11
CPU Architecture - More Detailed View
Execution Unit Bus Interface

Unit
12
Registers to save data

temporarly
Note: Registers are not
part of the memory
Main task of EU is the

execution of instructions
Arithmetic Logic Unit (ALU)

• Execution of arithmetic
operations (+,-,*,/)
• Execution of logical
operations (and, or, not)
Aid in operations
13
Main task of the BIU is

the communication
between the EU and the
memory and I/O devices
Instruction queue is used

to save untill 6 words of
instructions (instruction
prefetch)
14
Registers
• Used to save data temporarily inside the CPU

– Goal: aid in operations
– Keep in mind: access to the memory is the most time-consuming
task from the CPU point of view
– How many registers should the CPU have is a trade-off and
optimization task
• Theoritically: the more the number of registers, the less the memory
access
• Practically: not really, there are limits where increasing the number of
registers does not result in more efficiency  an optimization task
– How long should registers be is a question that relates to other factors
• E.g. address registers should be as long as the addresses the CPU uses
• From a functional point of view

– User-visible registers
– Control and status registers
15
Registers
• User-visible registers
– Mostly used by the computation unit to execute instructions
– Classified into
• General purpose registers
• Data registers
• Address registers
• Condition codes registers
• Control and status registers

– Used by the control unit to control the computation unit
– Express the status of the CPU, results, etc.
– Examples
• Carry flag
• Zero flag
• …
16
General Purpose Registers - Examples
• Accumulator (Ax)
– The most important register
• All operations are done by means of AX
• Segment pointers
– Contain the adress of a segment (the address of the byte where the
segment starts)
– Some are used for codes, some for data
– Examples
• Code segment (CS)
– Contains the start address of the program
• Data segment (DS)
– Contains the start address of the block where data are stored
17
General Purpose Registers
• Stack pointer (SP)

– Contains the address of the stack
– Stacks works based on push/pop principle
Push C C Pop C
Address_1 Address_1 Address_1

A (stored in the SP) C (stored in the SP) A (stored in the SP)
B A B
B
18
Control & Status Registers
• Program Counter (PC)

– Contains the address of the next instruction that should be executed
• Instruction Register (IR)
– Contains the instruction the CPU has to process
• Flags
– Determine the status of the result of the last operation
– Examples
• Carry flag (C)
– 1: there is a carry, 0: there is no carry
• Overflow flag (O)
– 1: the result is beyond the range the register can store, 0: the result is inside
that range
• Sign flag (S)
– 1: the result is negative, 0: the result is positive
• Zero flag (Z)
– 1: the result is zero, 0: the result is not zero
19
Programming Languages
20
Programming Languages
• Programming language is a set of instructions and rules used to

implement blocks of software to perform certain operation
• Two types of programming languages

– Low-level languages
• Machine language: the language the CPU understads and executes
• Assemply language: the first level of coding of machine language into
readable instructions
– High level languages

• Written in languages similar to those used in nature
• Simpler and more readable than machine and assemply languages
• Need to be compiled and built
21
Machine Language
• The language the CPU understands
• Set of “1“s and “0“s
• E.g.
– 10100001 00000000 00000000 (fetch the content of the address “0”
and put them in the register AX)
– 00000101 00000100 00000000 (add 4 to AX)
– 10100011 00000000 00000000 (save the content of AX in the

memory under the address “0”)
• Writing programms in machine language is a tough task
22
Assemply Language
• The first level of coding of machine language into readable

instructions
• Write programms using

– Commands: MOV, SUB, XCHNG, etc.
– Register names: AX, BX, CX, etc.
– Memory addresses: [1000H], [2345H], etc.
– Data: A DW 2 (define a variable with the name “A“ and the value “2“)
• Programms written using assemply are faster than those written

using high-level languages
• Programms written using assemply should be converted into

programms written in machine language
– The converter is called assempler
23
Assemply Language
Programms written using Programms written using

assemply assemply
MOV Ax, [0000H]

10100001 00000000 00000000
ADD Ax, 4 00000101 00000100 00000000
10100011 00000000 00000000
MOV [0000H], AX
Assempler
Wireless Internet, Master Program 24

High-Level Languages
• Written in languages similar to those used in nature
• Widely used and acceptable
• E.g.
– C++, Delphi, Java, C#, PHP, TCL, etc.
• Visual versions are widely used
• Programms written using high-level language should be

– Compiled to check for syntax errors
– Built to be converted into programms written assemply language and
machine language
25
26
27
28
The program
written in assembly The registers
of the CPU
The flags
The program
Memory written in machine
content language
29
Instructions Execution
30
How Instructions Are Executed?
• Each Instruction consists of two parts

– Operation Code (OpCode)
– Operands
• E.g.
– Mov (OpCode) AX [1000H] (operands)
• OpCode determines which operation should be done
• Operands are registers and memory addresses
• Instructions are executed in two cycles

– Fetch cycle
– Execution cycle
31
• Fetch cycle
– Fetch the instruction from the memory
• Put the read command on the control bus
• Put the address of the instruction on address bus
• Receive the instruction on data bus and push them into the instruction
queue
– Decode the instruction

• To determine the operation that should be done
– Fetch data from the memory if necessary

• Put the read command on the control bus
• Put the address of the memory location on the address bus
• Read data from the data bus
32
• Execution cycle
– Perform the operation
• ALU execute the operation
• The operation is executed by means of the register AX
– Save the result in the memory if necessary

• Put the save command on the control bus
• Put the operation result on the data bus
• Put the address of the memory location on address bus
• During the execution cycle, the BIU fetches the following

instructions (instruction prefetch)
33
Instructions Execution with Interuption
Start
Fetch next
Fetch cycle
instruction
Execute
Execution cycle
Interrupt disabled Instruction
Interrupt enabled
Halt
Check for interrupt
Interrupt cycle
Process interrupt
34
Indirect Cycle
Indirection
Instruction Operand
fetch fetch
instruction
operands
Request
Multiple
Request
operand
Instruction Instruction Operand

Instruction
address operation address
execution
calculation decoding calculation
Next instruction
35
Data Flow
Address bus
Control bus
Data bus
PC MAR
Memory
Control
unit
IR MBR Fetch cycle
36
Data Flow
Address bus
Control bus
Data bus
MAR
Memory
Control
unit
MBR Indirect cycle
37
Data Flow
Address bus
Control bus
Data bus
PC MAR
Memory
Control
unit
MBR Interrupt cycle
38
Instructions Pipelining
39
Why Was Pipelining Introduced?
• Fetching and execution of instruction serially are note that efficient

– CPU waits till the next instruction is fetched
– After the execution of the instruction, the next is fetched
Wait Wait
New address
Instruction Result
Fetch Instruction Execute
Discard
• Solutions: try to reduce (eliminate in the ideal case) waiting times
 Pipelining
40
How Does It Work?
• Let us assume the handling of an instruction has 6 steps

– Fetch Instruction (FI)
• Bring the instruction from the memory
– Decode Instruction (DI)
• Extract what does the instruction do
– Calculate Operand (CO)
• Calculate the address of the operand
– Fetch Operand (FO)
• Bring the operand from the memory
– Execute Instrruction (EI)
• Execute the instruction on the operand
– Write Operand (WO)
• Write the result in th ememory
• Let us assume that all steps require the same time to operate
41
How Does It Work?
1 2 3 4 5 6 7 8 9 10 11 12 13 14
FI DI CO FO EI WO
Instruction 1
Instruction 2 FI DI CO FO EI WO
FI DI CO FO EI WO
Instruction 3
FI DI CO FO EI WO
Instruction 4
FI DI CO FO EI WO
Instruction 5
FI DI CO FO EI WO
Instruction 7
FI DI CO FO EI WO
Instruction 9
Time
42
How Does It Work?
1 2 3 4 5 6 7 8 9 10 11 12 13 14
FI DI CO FO EI WO
Instruction 1
FI DI CO FO EI WO
Instruction 3
Start fitching instruction 2 FI DI CO FO EI WO

Instruction 4
upon decoding
instruction 1  pipelining FI DI CO FO EI WO
Instruction 5
instruction 2 (do not let
anything waiting)
FI DI CO FO EI WO
Instruction 7
FI DI CO FO EI WO
Instruction 9
Time
43
How Does It Work?
1 2 3 4 5 6 7 8 9 10 11 12 13 14
FI DI CO FO EI WO
Instruction 1
FI DI CO FO EI WO
Instruction 3
FI FO
Instruction 4 (14 time steps) theDItimeCOrequired to
EI WO
operate 9 instructions
• The time required to execute 9 instructions without
FI DI CO FO EI WO
Instruction 5 pipelining is 54 time steps
• The pipelining has reduced them to 14
FI DI CO FO EI WO
Instruction 7
FI DI CO FO EI WO
Instruction 9
Time
44
How Does It Work?
1 2 3 4 5 6 7 8 9 10 11 12 13 14
FI DI CO FO EI WO
Instruction 1
FI DI CO FO EI WO
Instruction 3
FI FO
Instruction 4 (14 time steps) theDItimeCOrequired to
EI WO
operate 9 instructions
FI DI CO FO EI WO
FI DI CO FO EI WO
Instruction 7
FI DI CO FO EI WO
Instruction 9
Time
45
How Does It Work with condition Instructions?
1 2 3 4 5 6 7 8 9 10 11 12 13 14
FI DI CO FO EI WO
Instruction 1
FI DI CO FO EI WO
Instruction 3
Instruction 4
Let us assume that
instruction 3 is a
Instruction 5 condition that lets the
program jummbing to
Instruction 6 instruction 15 (if or case
statement for example)
Instruction 7
Instruction 15
Instruction 16
Time
46
1 2 3 4 5 6 7 8 9 10 11 12 13 14
FI DI CO FO EI WO
Instruction 1
FI DI CO FO EI WO
Instruction 3
FI DI CO FO
Instruction 4
FI DI CO
Instruction 5
Instruction 6 FI DI
FI
Instruction 7
FI DI CO FO EI WO
Instruction 15
FI DI CO FO EI WO
Instruction 16
Time
47
1 2 3 4 5 6 7 8 9 10 11 12 13 14
FI DI CO FO EI WO
Instruction 1
FI DI CO FO EI WO
Instruction 3
FI FO
Instruction 4 (14 time steps) theDItimeCOrequired to operate 5 instructions
FI DI CO
Instruction 6 FI DI
FI
Instruction 7
FI DI CO FO EI WO
Instruction 15
FI DI CO FO EI WO
Instruction 16
Time
48
1 2 3 4 5 6 7 8 9 10 11 12 13 14
FI DI CO FO EI WO
Instruction 1
FI DI CO FO EI WO
Instruction 3
FI FO
Instruction 4 (14 time steps) theDItimeCOrequired to operate 5 instructions
FI DI CO
Instruction 6 FI DI
FI
Instruction 7
FI DI CO FO EI WO
Instruction 15
FI DI CO FO EI WO
Instruction 16
Time
49
More Detailed View
Fetch Fetch
instruction operand
Decode Execute
instruction instruction
Calculate Write
operand operand
No Branch or No
Unconditional
interrupt
branch
Yes Yes
Update
PC
Empty the
pipe
50
CISC and RISC Processors
51
Complex Instruction Set Computer (CISC)
• Has relative large number of instructions

– So, some instructions are rarely used
• Large variety in addressing modes
• Instructions have no fixed length  complex decoding
• There exist instructions to process the operands in the memory
• Compile of programms written in high-level languages is relative simple
• Processors need significant hardware support to provide such features 

processors are complex and expensive, additionally can not be that fast
52
Reduced Instruction Set Computer (CISC)
• Has relative small number of instructions

– So, some instructions are rarely used
• small variety in addressing modes
• Access to the memory only includes write and read in/from the memory
• Instructions have fixed length  simple decoding
• Considerable amount of registers
• Compile of programms written in high-level languages needs support

from the compiler itself
• Processors are less complex and less expensive and faster
53

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Computer Peripheral Units

Central Processing Unit (CPU)

Bachelor of Science, Electrical Engineering (Communication and

Dr.-Ing. Ali Diab

Summer Semester 2015

Faculty of Mechanical and Electrical Engineering

• Interconnection of Microcomputer System`s Components

• Central Processing Unit (CPU) Architecture

• CISC and RISC Processors

Interconnection of Microcomputer System`s

• From the functional point of view, each computer consists of

Interconnection between Computer`s Componentss

• Interconnect via buses, which

• Three types of buses

• I/O devices are connected to the computer via I/O ports

• There are two types of I/O ports

• Each I/O unit consists of two main parts

The device controller (electronic

The rollers that touch the

An encoder chip (small

Central Processing Unit (CPU) Architecture

CPU Architecture - Abstract View

Execute following tasks

Computation unit Control unit

CPU Architecture - More Detailed View

Execution Unit Bus Interface

CPU Architecture - More Detailed View

Registers to save data

Main task of EU is the

Arithmetic Logic Unit (ALU)

CPU Architecture - More Detailed View

Main task of the BIU is

Instruction queue is used

• Used to save data temporarily inside the CPU

• From a functional point of view

• Control and status registers

General Purpose Registers - Examples

General Purpose Registers

• Stack pointer (SP)

Address_1 Address_1 Address_1

Control & Status Registers

• Program Counter (PC)

• Programming language is a set of instructions and rules used to

• Two types of programming languages

– High level languages

• The language the CPU understands

• Set of “1“s and “0“s

– 00000101 00000100 00000000 (add 4 to AX)

– 10100011 00000000 00000000 (save the content of AX in the

• Writing programms in machine language is a tough task

• The first level of coding of machine language into readable

• Write programms using

• Programms written using assemply are faster than those written

• Programms written using assemply should be converted into

Programms written using Programms written using

MOV Ax, [0000H]

Wireless Internet, Master Program 24

• Written in languages similar to those used in nature

• Widely used and acceptable

• Visual versions are widely used

• Programms written using high-level language should be

How Instructions Are Executed?

• Each Instruction consists of two parts