Tibpal 16R8

TIBPAL16L8-15C, TIBPAL16R4-15C, TIBPAL16R6-15C, TIBPAL16R8-15C
TIBPAL16L8-20M, TIBPAL16R4-20M, TIBPAL16R6-20M, TIBPAL16R8-20M

HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019 D3340, FEBRUARY 1984 REVISED MARCH 1992
TIBPAL16L8
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J OR W PACKAGE
High-Performance Operation:
Propagation Delay
C Suffix . . . 15 ns Max
M Suffix . . . 20 ns Max
(TOP VIEW)
I
I
I
I
I
I
I
I
I
GND
Functionally Equivalent, but Faster than

PAL16L8A, PAL16R4A, PAL16R6A, and
PAL16R8A
Power-Up Clear on Registered Devices (All
Register Outputs are Set High, but Voltage
Levels at the Output Pins Go Low)
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
Dependable Texas Instruments Quality and
Reliability
DEVICE
I
INPUTS
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
I/O
PORT
S
PAL16L8
10
PAL16R4
4 (3-state buffers)
PAL16R6
6 (3-state buffers)
PAL16R8
8 (3-state buffers)
20
19
18
17
16
15
14
13
12
10
11
VCC
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
TIBPAL16L8
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
I
VCC
O
I
I
I
I
I
description
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
I/O
I/O
I/O
I/O
I/O
I
GND
I
O
I/O
These programmable array logic devices feature

high speed and functional equivalency when
compared with currently available devices. These
IMPACT circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for futher
reduction in board space.
The TIBPAL16 C series is characterized from 0C

to 75C. The TIBPAL16 M series is characterized
for operation over the full military temperature
range of 55C to 125C.
These devices are covered by U.S. Patent 4,410,987.

IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
Copyright 1992, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TIBPAL16R4-15C, TIBPAL16R6-15C, TIBPAL16R8-15C

TIBPAL16R4-20M, TIBPAL16R6-20M, TIBPAL16R8-20M
TIBPAL16R4
TIBPAL16R4
(TOP VIEW)
18
17
16
15
14
13
12
10
11
VCC
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
I
I
I
I
I
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
TIBPAL16R6
TIBPAL16R6
(TOP VIEW)
20
19
18
17
16
15
14
13
12
10
11
VCC
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
I
I
I
I
I
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
I
GND
I
I
CLK
VCC
I/O
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
GND
TIBPAL16R8
(TOP VIEW)
19
18
17
16
15
14
13
12
10
11
I
I
CLK
VCC
Q
20
VCC
Q
Q
Q
Q
Q
Q
Q
Q
OE
I
I
I
I
I
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
I
GND
Q
Q
Q
Q
Q
TIBPAL16R8
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
GND
I/O
Q
Q
Q
Q
OE
I/O
I/O
19
OE
I/O
Q
20
DALLAS, TEXAS 75265
OE
Q
Q
I
GND
CLK
I
I
I
I
I
I
I
I
GND
I
I
CLK
VCC
I/O
(TOP VIEW)
Q
Q
Q
Q
Q
TIBPAL16L8-15C, TIBPAL16R4-15C
TIBPAL16L8-20M, TIBPAL16R4-20M
functional block diagrams (positive logic)

TIBPAL16L8
&
32 X 64
16 x
I
10
16
16
EN 1
I/O
I/O
I/O
I/O
I/O
I/O
TIBPAL16R4
OE
CLK
EN 2
C1
&
32 X 64
16 x
I
I=1 2
1D
8
16
4
4
16
EN 1
I/O
I/O
I/O
I/O
4
4
denotes fused inputs
DALLAS, TEXAS 75265
TIBPAL16R6-15C, TIBPAL16R8-15C
TIBPAL16R6-20M, TIBPAL16R8-20M
functional block diagrams (positive logic)

TIBPAL16R6
OE
CLK
EN 2
C1
&
32 X 64
16 x
I
I=1 2
1D
8
16
6
2
16
EN 1
I/O
I/O
7
2
6
TIBPAL16R8
OE
CLK
EN 2
C1
&
32 X 64
16 x
I
I=1 2
16
16
8
denotes fused inputs
1D
DALLAS, TEXAS 75265
TIBPAL16L8-15C
TIBPAL16L8-20M
logic diagram (positive logic)

I
1
Increment
First
Fuse
Numbers
12
16
20
24
28
0
32
64
96
128
160
192
224
31
19
256
288
320
352
384
416
448
480
18
512
544
576
608
640
672
704
736
17
768
800
832
864
896
928
960
992
16
1024
1056
1088
1120
1152
1184
1216
1248
15
1280
1312
1344
1376
1408
1440
1472
1504
14
1536
1568
1600
1632
1664
1696
1728
1760
13
1792
1824
1856
1888
1920
1952
1984
2016
12
11
I/O
I/O
I/O
I/O
I/O
I/O
Fuse number = First fuse number + Increment
DALLAS, TEXAS 75265
TIBPAL16R4-15C
TIBPAL16R4-20M

CLK
1
Increment
First
Fuse
Numbers
12
16
20
24
31
19
256
288
320
352
384
416
448
480
18
512
544
576
608
640
672
704
736
I=1
1D
768
800
832
864
896
928
960
992
I=1
1D
1024
1056
1088
1120
1152
1184
1216
1248
I=1
1D
1280
1312
1344
1376
1408
1440
1472
1504
I=1
1D
17
I/O
I/O
C1
16
C1
15
C1
14
C1
1536
1568
1600
1632
1664
1696
1728
1760
13
1792
1824
1856
1888
1920
1952
1984
2016
12
11
28
0
32
64
96
128
160
192
224
DALLAS, TEXAS 75265
I/O
I/O
OE
TIBPAL16R6-15C
TIBPAL16R6-20M

CLK
1
Increment
First
Fuse
Numbers
12
16
20
24
28
31
0
32
64
96
128
160
192
224
19
256
288
320
352
384
416
448
480
I=1
1D
512
544
576
608
640
672
704
736
I=1
1D
768
800
832
864
896
928
960
992
I=1
1D
1024
1056
1088
1120
1152
1184
1216
1248
I=1
1D
1280
1312
1344
1376
1408
1440
1472
1504
I=1
1D
1536
1568
1600
1632
1664
1696
1728
1760
I=1
1D
18
I/O
C1
17
C1
16
C1
15
C1
14
C1
13
C1
1792
1824
1856
1888
1920
1952
1984
2016
12
11
I/O
OE
DALLAS, TEXAS 75265
TIBPAL16R8-15C
TIBPAL16R8-20M

CLK
1
Increment
First
Fuse
Numbers
12
16
20
24
31
I=1
1D
256
288
320
352
384
416
448
480
I=1
1D
512
544
576
608
640
672
704
736
I=1
1D
768
800
832
864
896
928
960
992
I=1
1D
1024
1056
1088
1120
1152
1184
1216
1248
I=1
1D
1280
1312
1344
1376
1408
1440
1472
1504
I=1
1D
1536
1568
1600
1632
1664
1696
1728
1760
I=1
1D
1792
1824
1856
1888
1920
1952
1984
2016
I=1
1D
19
C1
18
C1
17
C1
16
C1
15
C1
14
C1
13
C1
12
C1
11
28
0
32
64
96
128
160
192
224
DALLAS, TEXAS 75265
OE

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 75C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions

VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
IOL
fclock
Low-level output current
tw
Pulse duration, clock (see Note 2)
tsu
th
Setup time, input or feedback before clock
High-level input voltage
MIN
NOM
MAX
UNIT
4.75
5.25
5.5
0.8
High-level output current
3.2
Clock frequency
0
High
Low
Hold time, input or feedback after clock
V
mA
24
mA
50
MHz
ns
15
ns
ns
TA
Operating free-air temperature
0
25
75
C
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are
only for clock high or low, but not for both simultaneously.
DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range

PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.75 V,
VCC = 4.75 V,
II = 18 mA
IOH = 3.2 mA
VOL
VCC = 4.75 V,
IOL = 24 mA
VCC = 5.25 V,
VO = 2.7 V
VCC = 5.25 V,
VO = 0.4 V
II
IIH
VCC = 5.25 V,
VCC = 5.25 V,
VI = 5.5 V
VI = 2.7 V
IIL
IO
VCC = 5.25 V,
VCC = 5.25 V,
VI = 0.4 V
VO = 2.25 V
ICC
VCC = 5.25 V,
VI = 0,
Outputs
IOZH
I/O ports
Outputs
IOZL
I/O ports
MIN
TYP
2.4
3.3
0.35
MAX
UNIT
1.5
V
V
0.5
20
100
20
250
0.1
30
Outputs open
140
V
A
A
mA
20
0.2
mA
125
mA
180
mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
I, I/O
O, I/O
tpd
ten
CLK
OE
tdis
ten
OE
I, I/O
tdis
I, I/O
PARAMETER
fmax
tpd
TYP
MAX
10
15
ns
R1 = 500 ,
12
ns
R2 = 500 ,
12
ns
See Figure 3
10
ns
O, I/O
10
15
ns
O, I/O
10
15
ns
TEST CONDITION
MIN
50
UNIT
MHz
All typical values are at VCC = 5 V, TA = 25C.

The output conditions hace been chosen to produce a current that closely approximates one half of the short-circuit output current, IOS.
10
DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 125C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions

MIN
NOM
MAX
4.5
5.5
UNIT
V
5.5
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
High-level output current
mA
IOL
fclock
Low-level output current
tw
Pulse duration, clock (see Note 2)
tsu
th
Setup time, input or feedback before clock
High-level input voltage
Clock frequency
0
High
10
Low
11
Hold time, input or feedback after clock
12
mA
41.6
MHz
ns
20
ns
ns
TA
Operating free-air temperature
55
25
125
C
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are
only for clock high or low, but not for both simultaneously..
DALLAS, TEXAS 75265
11

electrical characteristics over recommended operating free-air temperature range

PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.5 V,
VCC = 4.5 V,
II = 18 mA
IOH = 2 mA
VOL
VCC = 4.5 V,
IOL = 12 mA
VCC = 5.5 V,
VO = 2.7 V
VCC = 5.5 V,
VO = 0.4 V
VCC = 5.5 V,
VI = 5.5 V
VCC = 5.5 V,
VI = 2.7 V
Outputs
IOZH
I/O ports
Outputs
IOZL
I/O ports
Pin 1, 11
II
All others
MIN
TYP
2.4
3.2
0.25
I/O ports
IOS
ICC
V
V
0.4
20
250
0.2
0.1
V
A
A
mA
50
100
20
I/O ports
All others
1.5
20
All others
IIL
UNIT
100
Pin 1, 11
IIH
MAX
0.25
VCC = 5.5 V,
VI = 0.4 V
VCC = 5.5 V,
VCC = 5.5 V,
VO = 0.5 V
VI = 0,
0.2
30
Outputs open
140
mA
250
mA
190
mA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
I, I/O
O, I/O
tpd
ten
CLK
OE
tdis
ten
tdis
PARAMETER
fmax
tpd
TYP
MAX
10
20
ns
R1 = 390 ,
15
ns
R2 = 750 ,
15
ns
OE
See Figure 4
15
ns
I, I/O
O, I/O
10
20
ns
I, I/O
O, I/O
10
20
ns
TEST CONDITION
MIN
41.6
UNIT
MHz
All typical values are at VCC = 5 V, TA = 25C.

Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid
test equipment degradation.
12
DALLAS, TEXAS 75265

programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Figure 1 and Note 3)

The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With VCC at 5 volts and Pin 1 at VIL, raise Pin 11 to VIHH.

Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the
voltage level at the output pin.
VIHH
Pin 11
VIL
td
tsu
tw
td
VIH
Pin 1
VIL
VIH
Registered I/O
Input
VOH
Output
VIL
VOL
Figure 1. Preload Waveforms

NOTE 3: td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 v
DALLAS, TEXAS 75265
13

power-up reset (see Figure 2)

Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.
VCC
5V
4V
tpd
(600 ns TYP, 1000 ns MAX)
VOH
Active Low
Registered Output
1.5 V
VOL
tsu
VIH
CLK
1.5 V
1.5 V
VIL
tw
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
14
DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

7V
S1
R1
From Output
Under Test
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR

3-STATE OUTPUTS
3.5 V
Timing
Input
1.3 V
3.5 V
High-Level
Pulse
1.3 V
1.3 V
0.3 V
0.3 V
tw
th
tsu
3.5 V
Data
Input
1.3 V
1.3 V
0.3 V
3.5 V
Low-Level
Pulse
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
3.5 V
1.3 V
Input
1.3 V
0.3 V
tpd
tpd
In-Phase
Output
1.3 V
VOH
1.3 V
VOL
tpd
tpd
Out-of-Phase
Output
(see Note D)
1.3 V
VOH
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
ten
tdis
3.5 V
1.3 V
Waveform 1
S1 Closed
(see Note B)
VOL + 0.3 V
VOL
tdis
ten
Waveform 2
S1 Open
(see Note B)
VOH
1.3 V
VOH 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR 1 MHz, tr = tf 2 ns, duty cycle = 50%
D. When measuring propagation delay times of 3- state outputs from low to high, switch S1 is closed.
When measuring propagation delay times of 3- state outputs from high to low, switch S1 is open.
E. Equivalent loads may be used for testing.
Figure 3. Load Circuit and Voltage Waveforms
DALLAS, TEXAS 75265
15

PARAMETER MEASUREMENT INFORMATION

5V
S1
R1
From Output
Under Test
Test
Point
CL
(see Note A)
R2
LOAD CIRCUIT FOR

3-STATE OUTPUTS
3V
Timing
Input
1.5 V
3V
High-Level
Pulse
1.5 V
1.5 V
0
tw
th
tsu
3V
Data
Input
1.5 V
1.5 V
3V
Low-Level
Pulse
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
3V
1.5 V
Input
1.5 V
0V
tpd
tpd
In-Phase
Output
1.5 V
VOH
1.5 V
VOL
tpd
tpd
Out-of-Phase
Output
(see Note D)
1.5 V
VOH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Control
(low-level
enabling)
1.5 V
1.5 V
0
ten
tdis
3.3 V
1.5 V
Waveform 1
S1 Closed
(see Note B)
VOL + 0.5 V
VOL
tdis
ten
Waveform 2
S1 Open
(see Note B)
VOH
1.5 V
VOH 0.5 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR 10 MHz, tr and tf 2 ns, duty cycle = 50%
D. When measuring propagation delay times of 3- state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 4. Load Circuit and Voltage Waveforms
16
DALLAS, TEXAS 75265
SRPS019
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Tibpal 16R8

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TIBPAL16L8-15C, TIBPAL16R4-15C, TIBPAL16R6-15C, TIBPAL16R8-15C

TIBPAL16L8-20M, TIBPAL16R4-20M, TIBPAL16R6-20M, TIBPAL16R8-20M

SRPS019 D3340, FEBRUARY 1984 REVISED MARCH 1992

Functionally Equivalent, but Faster than

These programmable array logic devices feature

The TIBPAL16 C series is characterized from 0C

These devices are covered by U.S. Patent 4,410,987.

PRODUCTION DATA information is current as of publication date.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TIBPAL16R4-15C, TIBPAL16R6-15C, TIBPAL16R8-15C

SRPS019 D3340, FEBRUARY 1984 REVISED MARCH 1992

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SRPS019 D3340, FEBRUARY 1984 REVISED MARCH 1992

functional block diagrams (positive logic)

denotes fused inputs

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SRPS019 D3340, FEBRUARY 1984 REVISED MARCH 1992

functional block diagrams (positive logic)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SRPS019 D3340, FEBRUARY 1984 REVISED MARCH 1992

logic diagram (positive logic)

Fuse number = First fuse number + Increment

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SRPS019 D3340, FEBRUARY 1984 REVISED MARCH 1992

logic diagram (positive logic)

Fuse number = First fuse number + Increment

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SRPS019 D3340, FEBRUARY 1984 REVISED MARCH 1992

logic diagram (positive logic)

Fuse number = First fuse number + Increment

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SRPS019 D3340, FEBRUARY 1984 REVISED MARCH 1992

logic diagram (positive logic)

Fuse number = First fuse number + Increment

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TIBPAL16L8-15C, TIBPAL16R4-15C, TIBPAL16R6-15C, TIBPAL16R8-15C

recommended operating conditions

Low-level input voltage

Low-level output current

Pulse duration, clock (see Note 2)

Setup time, input or feedback before clock

High-level input voltage

High-level output current

Hold time, input or feedback after clock

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TIBPAL16L8-15C, TIBPAL16R4-15C, TIBPAL16R6-15C, TIBPAL16R8-15C

electrical characteristics over recommended operating free-air temperature range

All typical values are at VCC = 5 V, TA = 25C.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TIBPAL16L8-20M, TIBPAL16R4-20M, TIBPAL16R6-20M, TIBPAL16R8-20M

recommended operating conditions

Low-level input voltage

High-level output current