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VR Id
VR Id
AbstractThis paper proposes an autonomous unified var controller to address the system voltage issues and unintentional islanding problems associated with distributed photovoltaic (PV)
generation systems. The proposed controller features the integration of both voltage regulation (VR) and islanding detection (ID)
functions in a PV inverter based on reactive power control. Compared with the individual VR or ID methods, the function integration exhibits several advantages in high PV penetration applications: 1) fast VR due to the autonomous control; 2) enhanced
system reliability because of the capability to distinguish between
temporary grid disturbances and islanding events; 3) negligible
nondetection zone (NDZ) and no adverse impact on system power
quality for ID; and 4) no interferences among multiple PV systems during ID. As the VR and ID functions are integrated in one
controller, the controller is designed to fulfill the requirement of
VR dynamic performance and ensure small ID NDZ simultaneously. The interaction among multiple PV systems during VR is
also considered in the design procedure. Finally, the feasibility of
the proposed controller and the controller design method is validated with simulation using a real-time digital simulator and a
power hardware-in-the-loop testbed.
Index TermsHigh penetration PV systems, islanding detection
(ID), voltage regulation (VR).
UDS
VR
D
f
f
fm in , fm ax
ig
ig q
KI
KI ave
KP ins
KPC
KPW M
Lf
N 844, N 890
Pg
PL
PPV
Q844 , Q890
Qdes
AVC
ID
IVC
NDZ
OF/UF
OV/OU
PCC
PHIL
PLL
RTDS
STS
NOMENCLATURE
Average voltage reference compensator.
Islanding detection.
Instantaneous voltage reference compensator.
Nondetection zone.
Over/under frequency.
Over/under voltage.
Point of common coupling.
Power hardware-in-the-loop.
Phase-locked loop.
Real-time digital simulator.
Static transfer switch.
Manuscript received January 28, 2012; revised May 14, 2012; accepted
September 4, 2012. Date of current version December 7, 2012. This work
was supported in part by the National Science Foundation under Award ECCS1001415 and in part by the U.S. Department of Energy (DOE) Sunshine State
Solar Grid Initiative (SUNGRIN) under Award DE-EE0002063. Recommended
for publication by Associate Editor T. Suntio.
The authors are with the Center for Advanced Power Systems, Florida
State University, Tallahassee, FL 32310 USA (e-mail: zou@caps.fsu.edu;
hli@caps.fsu.edu; liming@caps.fsu.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2012.2218288
Qf
Qg
QL
QPV
Rs
tc
tS
v1
vPCC
V844 , V890
Vave
Vb
Vcom p
Vins
Vm in , Vm ax
Vn
VPCC
VPCC
Xs
P
Q
QPV
VPCC
c
s
NCREASING penetration of distributed PV systems introduces new integration issues concerning the safe operation of
distribution systems [1], [2]. The voltage rise due to the reverse
power flow and voltage fluctuations associated with the irradiation variation has been envisioned from field observations
and research results [3][5]. Possible false tripping of mass
distributed PV systems as a result of the tight anti-islanding
voltage/frequency settings could lead to unacceptable low voltage [1]. These problems impose more stress on the utility voltage
regulation (VR) devices, and even cause them to malfunction.
Therefore, it is important to research effective methods to mitigate the impact of the distributed PV systems on the feeder
voltage profiles.
To actively involve distributed PV systems in feeder VR
is one of the promising solutions for the potential voltage issues [6][10]. In fact, they can assist and coordinate with the
low-speed utility VR devices to form a two-layer (low and high
speed) VR system [1]. The state-of-the-art inverter-based VR
methods mainly include power curtailment [3], [7], volts/var
droop control [7], [8] and communication-based PI control [9],
[10]. In order to ride through the grid disturbances, loose antiislanding voltage/frequency trip settings are recommended [11],
but it increases the possibility of islanding detection (ID) failure.
Consequently, it is necessary to develop more intelligent active
ID algorithms to ride through voltage disturbances without expanding the islanding nondetection-zone (NDZ) [12].
However, there are possibilities of operation conflicts between
VR and active ID algorithms implemented in the same PV inverter. On one hand, some VR and ID methods cannot be realized
simultaneously because the same control variable is employed
for different objectives. Typically, the frequency positive feedback ID method [13] cannot work with the reactive-power-based
VR method [7][10], since they control the reactive power based
on voltage frequency and amplitude feedback, respectively. On
the other hand, an incorrect response of VR or ID algorithms
to the instantaneous voltage variation without distinguishing
the cause may result in function failures. This possibility is
due to the fact that both islanding and short-duration voltage
events [14] could induce an instantaneous voltage change. For
example, if there is a voltage sag event, the voltage positive
feedback ID [13] method will reduce the inverter real power
output which leads to further feeder voltage decrease. More-
2827
2828
Fig. 1.
(1)
where V1 is the amplitude of v1 ; is the phase difference between vPCC and v1 . The detailed derivation of (1) is shown in
Appendix A. As required by the local utility operator or standards such as ANSI C84.1, VPCC needs to be maintained within
the permitted voltage range by certain measures. Equation (1)
illustrates that VPCC can be regulated through adjusting PPV
and QPV from distributed PV systems. The real power control
is usually employed to eliminate PCC overvoltage by forcing the
PV system operation away from the maximum power point [3],
[7]. The reactive power control can contribute to network voltage regulating both dynamically and statically [7][10].
Subsequent to an islanding event when the UDS is open, the
PCC voltage deviation directly depends on the power mismatch
and f are defined as
between the PV and the load. If VPCC
the new PCC voltage and frequency after islanding, and P +
jQ = (PPV PL ) + j (QPV QL ) is the power mismatch
between the PV and load, the relationship between them can be
described as follows [22]:
P
V2
= 1 PCC
2
PPV
VPCC
f 2
Qf
f P
f
Q
+
1
1
f PPV
QPV
f2
tan
f
(2)
(3)
Fig. 2.
2829
The voltage controller, which is an integral regulator, KI dt,
is the key component of the unified var controller to integrate the
VR and ID functions. The reference of the voltage controller is
is generated autonomously
In the proposed controller, VPCC
by an adaptive voltage reference generation mechanism. This
is different from the communication-based PI control, in which
2830
Fig. 3.
QPV Xs
VPCC
(4)
s Q L X s
where Vb = V1 + (P P V PVLP)R
represents the system disCC
turbance that affects the PCC voltage.
Because the purpose of VR is to compensate the system disturbance, the PCC voltage disturbance rejection capability is of
great interest. It can be described in (5) according to Fig. 4
VPCC
s ( s + 1)
=
Vb
s ( s + 1) + 0.5 Gc (s) KI XS
(5)
ig q
ig q
KPC KPW M (c s + 1)
.
s c Lf s3 +c Lf s2 +KPC KPW M c s+KPC KPW M
(6)
1 1 2 KI XS
.
(7)
s=
2
When 1 2 KI XS 0, the voltage regulating response is
overdamped and the response settling time equals to tS =
8
. In this case, tS can be decreased by increas1 12 K I X S
ing KI . However, when 1 2 KI XS < 0, 1 2 KI XS becomes the imaginary part of the pole and further increase of KI
only increases the response oscillation frequency. Therefore, the
voltage response settling time is limited to tS = 8 due to the
RMS calculation delay.
In addition, since the current control loop has finite bandwidth, its influence on VR response can be illustrated in Fig. 5
by examining the system root locus. The root locus was derived
based on the selected PV system parameters given in Appendix
B. It is indicated that tS can be further decreased as compared
with 8 , but this is accompanied by a higher frequency response
oscillation. Moreover, the voltage response oscillation may become undamped when KI is even larger, in which case the
voltage controller poles move to the right-hand plane.
In practical implementation, the required settling time of VR
does not need to be as short as 8 . Also, PCC voltage oscillation is not desired during voltage regulating. Therefore, the
optimized VR performance can be achieved by designing the
voltage controller poles on the real axis, as seen from Fig. 5.
With this design criterion, the coupling between the voltage
Fig. 4.
2831
Appendix A
QPV i Xsi
QPV j Xsi
+
V
= Vb +
PCCi
VPCCi
VPCCj
VPCCj
+
= VPCCi +
VPCCj
VPCCj
(9)
where
Vb = V1 +
+
Fig. 5.
VPCCi
0.5KI j XS j s (i s + 1) Gcj (s)
=
Vb
Ci (s) Cj (s) 0.25KI i KI j XS2 i Gci (s)Gcj (s)
(10)
Fig. 6.
VPCCj
s (i s + 1) (j s + 1)
=
Vb
Ci (s) Cj (s) 0.25KI i KI j XS2 i Gci (s)Gcj (s)
control and the current control loop becomes negligible. Detailed explanation is provided in Appendix C. Consequently,
the voltage controller design procedure can be simplified by employing an ideal current control loop. The condition of assigning
the voltage controller poles on the real axis can be implemented
as
1 2 KI XS 0.
(8)
(11)
where Ci (s) = s (i s + 1) + 0.5KI i XS i Gci (s) and Cj (s) =
s (j s + 1) + 0.5KI j (XS i + XS j ) Gcj (s).
It is noticed the two subsystems share the same characteristic equation, which equals to the sum of the term
0.25KI i KI j XS2 i Gci (s)Gcj (s) and the multiplication of each
single systems characteristic equation. The additional term,
0.25KI i KI j XS2 i Gci (s)Gcj (s), is the result of system interaction and is affected by both the network impedance and controller parameters. Moreover, extra system zeros, which are contributed by the simultaneous response of multiple systems to reject the disturbance, are added in each subsystem. These added
zeros could lead to faster VR dynamics. Nevertheless, undesired
VR overshoot may also exist. It is unavoidable when there is
no communication between systems. To further look into the
system stability, the dynamic of the current control loop can
be ignored because it has minor affect on the VR stability, if
the aforementioned voltage controller design criterion is met.
Accordingly, the two-PV system characteristic equation is sim-
2832
plified to
C(s) = [s (i s + 1) + 0.5KI i XS i ]
[s (j s + 1) + 0.5KI j (XS i + XS j )]
0.25KI i KI j XS2 i .
(12)
A+B
1
p1 =
2
2
AB
1
p2 =
2
2
A+B
1
+
p3 =
2
2
AB
1
p4 =
+
(13)
2
2
where
A = 1 KI i XS i KI j (XS i + XS j ) and B =
2 [0.5KI i XS i 0.5KI j (XS i + XS j )]2 + KI i KI j XS2 i .
The calculated poles p1 p4 are all in the left-hand plane
because A + B < 1 and A B < 1. Therefore, the interaction
does affect the VR dynamics but the system stability is still
guaranteed, which implies that the voltage controller design
criteria obtained in single-PV case can be applied for multiplePV case. The following aspects have been considered in the
analysis.
1) The influence of i and j are neglected because of the
small values, but in fact i and j will dynamically change
during voltage regulating because of the PV reactive power
injection. If the change of i and j during voltage regulating becomes significant, then more detailed analysis
should be performed. However, this is the rare case which
happens only when the change of PV reactive power is
comparable to load power in the network.
2) The current control dynamic is neglected in the analysis
due to the loose coupling between the voltage control and
the current control loop. However, the interaction among
multiple current control loops could also cause system instability [28]. Therefore, the current control loop stability
should be ensured first in the design process. Detailed discussion of the current control loop design considering the
system interaction can be found in [28] and [29].
IV. ID CHARACTERISTIC ANALYSIS
A. NDZ of the Proposed Method
After KI is identified according to the requirement of VR
dynamics, it is necessary to examine its effect on the ID performance. The NDZ is the primary index to evaluate the ID
performance. There are several approaches to define the NDZ,
such as the power mismatch space, RLC load space, and the
Qf versus load resonant frequency space. The power mismatch
space represented by the space formed by the P /PPV and
Q/PPV boundaries [30] is used here to determine the NDZ
of the proposed ID method.
1
(14)
Vm ax
PPV
Vm in
2
2
f
f
Q
Qf 1
Qf 1
(15)
fm in
PPV
fm ax
where Vm in and Vm ax are the OV/UV protection thresholds;
fm in and fm ax are the OF/UF protection thresholds.
The proposed unified var controller facilitates the ID through
reactive power injection at the islanding moment. If in the prescribed islanding clearing time, the reactive power is accumulated to a value outside of the region defined in (15), the islanding network can be detected. From the control block diagram
shown in Fig. 4, the accumulative reactive power output after
grid disconnection is
KI VPCC
VPCC ) dt
QPV =
(VPCC
2
KI V n
(VPCC
VPCC ) dt
(16)
=
2
where the integral part does not include the initial value obtained
before islanding.
It is shown that both KI and the PCC voltage deviation
2
2
P
Vn2
Vn2
1
1 (17)
PPV
Vn2 + K2QI t2c
Vn2 + K2QI t1c
where tc is the required islanding clearing time, Q1 = PPV
Qf (1 ( f mf i n )2 ) and Q2 = PPV Qf (1 ( f mfa x )2 ). The aforementioned real power mismatch region strongly depends on the
value of KI and PPV . To exhibit the performance improvement
of the proposed ID method, the system provided in Appendix B
is employed as an example to specify the NDZ.
According to the IEEE Std. 1547 [23], the OV/UV and OF/UF
protection thresholds are set as
Vm ax = 110% Vn ,
fm ax = 60.5 Hz
and
Vm in = 88% Vn
fm in = 59.3 Hz.
2833
QPVtotal =
QPV x
x=1
n
KI x VPCCx
x=1
Fig. 7. NDZ of the passive anti-islanding method and the proposed method
(a) theoretical analysis according to the IEEE std. 1547 requirement; (b) simulation validation; and (c) theoretical analysis with widened protection settings
and with different clearing time.
(VPCCx
VPCCx ) dt (18)
2834
Fig. 8.
signal is sent to the PEBBs control system through the digital/analog converter (DAC) and reproduced at the PEBB inverter
stage output. The actual PV inverter output current is measured
and fed back into the simulated circuit through the analog/digital
converter (ADC). A coefficient k in series with the ADC is used
to virtually scale up/down the PV inverter power rating [33].
The proposed unified var controller is implemented in both the
PV inverter hardware and rest of the PV inverters simulated in
RTDS. Therefore, the PHIL testbed provides an environment in
which not only the proposed controller can be verified experimentally, but also the interaction among multiple PV systems
can be investigated. In addition, the PHIL experimental results
are also compared with pure RTDS software simulation results
and they are consistent with each other.
2835
Fig. 9. One-line diagram of the modified IEEE 34 node test feeder with high
penetration PV systems.
TABLE I
UNIFIED VAR CONTROLLER PARAMETERS FOR THE PV INVERTERS
AT NODE 844 AND 890
Fig. 10. Overvoltage test case: RTDS simulation results of (a) node 890 PCC
voltages; (b) node 890 reactive power outputs; (c) node 844 PCC voltages and
(d) node 844 reactive powers outputs.
2836
Fig. 11. Overvoltage test case: PHIL experimental waveforms of the hardware
PV inverter reactive power output and PCC voltage.
Fig. 12. Momentary voltage sag test case: RTDS simulation results of
(a) node 844 PCC voltages; (b) node 844 reactive power outputs; (c) node
890 PCC voltages and (d) node 890 reactive power outputs.
Fig. 14.
2837
ID test circuit.
Fig. 13. Momentary voltage sag test case: PHIL experimental waveforms of
the hardware PV inverter reactive power output and PCC voltage.
Fig. 15. Single-PV-inverter ID test when the unified var controller was
disabled.
C. ID Test Cases
The ID test cases were conducted based on a standard test
circuit, shown in Fig. 14. There are two reasons of using this
circuit instead of the IEEE 34 node test feeder. First, the circuit
given in Fig. 14 is a standard inverter anti-islanding test circuit
adopted in IEEE Std. 1547, IEEE Std. 929, and UL 1741. The
same circuit was also widely used by researchers studying ID
algorithms [34][37]. Second, by changing the RLC load power
rating and quality factor, the circuit can represent the islanding
networks formed in the IEEE 34 node test feeder.
As explained in Section IV, higher Qf leads to larger NDZ.
Therefore, a relatively high Qf = 2.5 is selected in the following
test and the RLC load was adjusted to resonate at 60 Hz . The PV
Fig. 16.
enabled.
2838
Fig. 17. Multiple-PV-inverter ID test when the unified var controller was
enabled: simulation waveforms.
Fig. 18. Multiple-PV-inverter ID test when the unified var controller was
enabled: PHIL experimental waveforms.
Fig. 19. Multiple-PV-inverter ID test when the unified var controller was
disabled: PHIL experimental waveforms.
VI. CONCLUSION
Theoretical analysis revealed that the VR and ID functions can
be integrated in a PV inverter by means of real/reactive power
control. The unified var controller, composed of the voltage controller and adaptive voltage reference generator, was presented
to achieve the function integration autonomously. With the proposed controller implemented in the distributed PV systems,
the potential system voltage issues can be mitigated and the
false tripping of the PV systems can be avoided. The feasibility
and advantages of the proposed controller were validated in the
RTDS and PHIL testbed. The voltage controller design criterion
was provided by investigating the limitations of VR dynamics
based on a single PV system model. The analysis illustrated
that the design criterion is applicable in multiple-PV scenario
as well, which was confirmed by the simulation/PHIL test results. Several design considerations for IVC and AVC were also
given.
2839
QPV j Xsi
.
VPCCj
(22)
Similarly
VPCCj j = vPCCi
(PPV j PL j ) j(QPV j QL j )
+
(Rsj + jXsj )
VPCCj j
Fig. 20.
(23)
APPENDIX A
TABLE II
PARAMETERS OF A SINGLE PV SYSTEM
(PPV PL ) j (QPV QL )
(Rs + jXs )
VPCC
[(PPV PL ) j(QPV QL )]
(cos + j sin )(Rs + jXs )
= V1 +
. (19)
VPCC
VPCC = V1 +
APPENDIX C
(20)
(P
PV i PL i ) j(QPV i QL i )
the real-axis segment. The breakaway points at the real axis
1
VPCCi i
(Rsi + jXsi ) of the two curves are both at s = 2 . The KI values at the
= V1 +
2840
Yan Zhou (S10) received the B.S. and M.S. degrees in electrical engineering from the Huazhong
University of Science and Technology, Hubei, China,
in 2007 and 2009, respectively. He is currently working toward the Ph.D. degree in the Department of
Electrical and Computer Engineering, Florida State
University, Tallahassee.
His research interests include grid-connected PV
system control, PV microinverter, GaN FETs application, and high PV penetration integration issues.
2841