Nyquist-Rate D/A Converters

David Johns and Ken Martin

University of Toronto
(johns@eecg.toronto.edu)
(martin@eecg.toronto.edu)

University of Toronto

slide 1 of 20
D.A. Johns, K. Martin, 1997

D/A Converter Basics.

B in

V out

D/A

V ref
B in is a digital signal (or word),
B in = b 1 2

+ b2 2

+ + bN 2

(1)

b i equals a 1 or a 0 (i.e. a binary digit).

V ref an analog reference; V out output .
V out = V ref ( b 1 2

+ b2 2

+ + bN 2

(2)

Define V LSB to be LSB signal change, V LSB V ref 2

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slide 2 of 20
D.A. Johns, K. Martin, 1997

D/A Converter Basics

For errors, define units of LSB 1 LSB = 1 2

A multiplying D/A allows V ref to be a varying input

V out proportional to multiplication of V ref and B in .
For ideal D/A , output signal is a well defined value
no quantization error!
V out
--------V ref
1
3/4
1/2

V LSB
----------- = 1/4 = 1 LSB
V ref

1/4
0

00

01

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10

11 (100)

B in

slide 3 of 20
D.A. Johns, K. Martin, 1997

D/A Resistor-String (Hamad, JSSC, Dec. 1978)

V ref
Guaranteed monotonic

b3
b3

Integrated with better than 10-bits

absolute accuracy.

b2

b3
b2

b3

b1

V out

Delay through the switch network

major speed limitation
Resistors might be realized using
polysilicon

b3

Resistors

b3

b2

If n-channel only used, can be laid

out small

b3
b3

b2

b1

Requires 2N resistors

3-bit

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slide 4 of 20
D.A. Johns, K. Martin, 1997

D/A Resistor-String Digital Decoding

V ref

Resistors

3 to 1 of 8 decoder

Higher speed implementation

(less resistance thru transistors)
Large cap load on buffer input

b1

Can pipeline digital decoding for

faster speed

b2

Requires 2N resistors

b3

V out
3-bit

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slide 5 of 20
D.A. Johns, K. Martin, 1997

Folded-resistor-string D/A
(Abrial, JSSC, Dec. 1988)
V ref

Less capacitance load

over the single bus
approach

b2

Requires 2N resistors
bit lines

b1

2 to 1 of 4 decoder

word lines

V out
2 to 1 of 4 decoder

b3 b4
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4-bit
slide 6 of 20
D.A. Johns, K. Martin, 1997

Binary-Weighted Resistor D/As.

RF
b1

b2

b3

b4

2R

4R

8R

16R

V ref
V out

V out

4-bit

b1 b2 b3

= R F V ref ------- ------- -------

2R 4R 8R

(3)

Only N resistors
Resistor and current ratios are on the order of 2N
No guarantee of monotonicity.
Prone to glitches (more later).
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slide 7 of 20
D.A. Johns, K. Martin, 1997

Reduced Spread Binary Resistor D/A

RF

2R

2R

4R
3R

V ref

V out

4R

4R

1
V A = --- ( V ref )
4

4-bit

Reduced resistor spread

Keep repeating this procedure > R-2R ladder

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slide 8 of 20
D.A. Johns, K. Martin, 1997

R-2R Based D/A Converters

R 1 R' 1

R 2 R' 2
R

R 3 R' 3
R

R 4 R' 4
R

2R

V ref
2R

2R
V
ref
-----------2R

2R
V
ref
-----------4R

2R
V
ref
-----------8R

V
ref
-----------16R

R' 4 = 2R
R 4 = 2R || 2R = R
R' 3 = R + R 4 = 2R
R 3 = 2R || R' 3 = R

(4)

Small size, good matching (only R and 2R)

University of Toronto

slide 9 of 20
D.A. Johns, K. Martin, 1997

R-2R Based Resistor Ladders

Example D/A converter
RF

b1
Ir

V ref

b2
I
----r
2

2R
R
Ir

b3

2R
R

I
----r
4

Ir 2

b4

2R
R
Ir 4

I
----r
8

V out

2R
2R
Ir 8

4-bit

Currents through the switches are scaled

Should scale switch sizes for good accuracy
No node voltage changes except for output > fast
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slide 10 of 20
D.A. Johns, K. Martin, 1997

R-2R Based Resistor Ladders

Slower circuit having equal current through switches
2R

R
R

Rf

2R
R

Vo
b4
I

b3

b2

b1

-5V

4-bit

Node voltages change slower circuit

No need to scale switch sizes (smaller size)

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slide 11 of 20
D.A. Johns, K. Martin, 1997

Glitches
Different delays for switching the different currents
MSB change often worst case
Rf

I1

V out

t
1

I2
t

I1

2
I2

I1 + I2
t
Glitches can be minimized by limiting the bandwidth
but that slows down circuit
Use thermometer code to reduce glitches
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slide 12 of 20
D.A. Johns, K. Martin, 1997

Charge-Redistribution SC D/As
Programmable SC gain amplifier.
16C

1 ( 2 )

V ref

8C 4C 2C C
b1 b2 b3 b4

2
1

2
2 ( 1 )

C2

V out

4-bit

Sign bit realized by interchanging input phases

Carefully clock-waveforms required to minimize
voltage dependency of clock-feed-through.
Digital codes should be changed when input side of
capacitors are connected to ground. Requires extra
digital complexity.
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slide 13 of 20
D.A. Johns, K. Martin, 1997

Thermometer D/A Converters

Binary

Thermometer Code

Decimal

b1

b2

b3

d1

d2

d3

d4

d5

d6

d7

0
1
2
3
4
5
6
7

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
1

0
0
0
0
0
0
1
1

0
0
0
0
0
1
1
1

0
0
0
0
1
1
1
1

0
0
0
1
1
1
1
1

0
0
1
1
1
1
1
1

0
1
1
1
1
1
1
1

b1

b2

b3

Binary-to-thermometer code conversion

d1

d2

d3

d4

d5

d6

d7

d1

d2

d3

d4

d5

d6

d7

Rf

V out

ref

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slide 14 of 20
D.A. Johns, K. Martin, 1997

Thermometer Code D/A Converter

01
01

2NC

Vref
02

01

02
Vout

C
Top Capacitors are
Connected to Ground

02

C2

2 N unit sized caps

Bottom Capacitors are

Connected to Vref

Guaranteed monotonic
C

Much lower glitching

Low DNL

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slide 15 of 20
D.A. Johns, K. Martin, 1997

Current-Mode D/As
Vout

Thermometer-code
High-speed, output feeds
directly to resistor
Important that delay to
all the switches are equal.

Column Decoder

di

di

di

Row

Bias

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Row Decoder

Vout

Col.

Overlapped clocks much

better than having nonoverlapped clocks.

I - Src
Array

slide 16 of 20
D.A. Johns, K. Martin, 1997

Current-Steered D/A [Colles, 88]

Operates as cascode current sources.
For max speed, keep voltage swing at source of Q1
small (just turned off)
Switching feed-through from the digital input
enhances switching speed.
V

ref

V
V

d
bias

1
Q

2
V

ref
R

bias

bias

ref

V out
50

University of Toronto

slide 17 of 20
D.A. Johns, K. Martin, 1997

Segmented D/A
Schoeff, 79; Saul, 85; Grebene, 84
R/2

Combine
thermometer
binary

Vout

and

Accuracy needed
for LSB reduced
Glitches reduced
2R
Vref

2R

2R
R

2R
R

Very popular
R

+
Vref
2R

2R

2R

2R

2 MSBs

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2R

4 Bit

Binary LSB - Segment

slide 18 of 20
D.A. Johns, K. Martin, 1997

Dynamically-Matched Current Sources

Schouwenaar, 88
0

Shift Register
1
0

Each current source

calibrated with a
I ref is
single reference

64 used so D/A can

continue operating

I d1 I d2 I d3

I d4 I d5

Switch Network

To

I 64

Achieved 92 dB
SNDR, and 20 mW
with 3V.
Used
for
application

audio

D/A

Dynamic technique with current switching for

realizing very well-matched current sources
Up to 16 bit accuracy
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slide 19 of 20
D.A. Johns, K. Martin, 1997

Dynamically-Matched Current Sources

I ref

I out
S2

I out

I ref
S2

I d1

I d1

S1
Cgs
S1

Cgs
Q1

0.9Iref

Calibration

0.9Iref

Current source 0.9I

added so a low gm
device used (W/L
equal to 10/75)
Re-calibrate before
leakage
causes
0.5LSB error

Q1

Regular Usage

Minimize clock-feedthrough and charge-injection by

having capacitance Cgs and bias voltage V GS large
Implies voltage error causes less current deviation.

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slide 20 of 20
D.A. Johns, K. Martin, 1997