The Economic Impact of Single Wafer Multiprocessors

Samuel C. Wood, Krishna C. Saraswat, J. Michael Harrison

Center for Integrated Systems, Stanford University, Stanford, CA 94305
Abstract
Single wafer multiprocessors, generally in the form of cluster tools, are gaining increasing importance
in commercial semiconductor product manufacture. This paper describes potential cost-related and timerelated advantages that could come from the multipmcessors. Next, hypothetical conventional and clusterbased fabs are simulated. The simulations results are discussed in terms of their evidence for the cost
and time advantages of the fabs. One general conclusion is that cluster tools can be used to achieve very
short throughput times at a premium cost per wafer. Finally, based on the potential advantages and the
simulation results, three areas of non-process issues are discussed which will determine the extent of the
multiprocessors' economic utility. These areas are cost, time, and fab management related.

1 Introduction
1.1 Background
Over the last few years, conferences such as this one have shown Rapid Thermal Multiprocessing to be
a quickly emerging technology. A rapid thennal process is typically performed one wafer at a time in a
chamber with some vacuum capability. The process times per wafer are also typically much faster than than
their conventional batch counterparts. The chambers may be capable of a variety of processes (e.g., cleaning,
nitridation, oxidation, and annealing), or single processes. In commercial production environments, chambers
such as these are already being connected together to form cluster tools capable of rapid multiprocessing of
wafers. The authors of this paper believe this cluster form of multiprocessor to be the most likely one over
the next five to ten years. This paper seeks to identify and to some extent, analyze the potential advantages
of this type of multipmcessor.
Over the last few years, it has become increasingly apparent that cluster tools for semiconductor processing will play a significant mie in semiconductor IC manufacturing. For example, IBM has announced the
use of clustering of "as many sequential process operations as practicable" in its 16Mb DRAM production
[1]. Texas Instruments' five-year Microelectronics Manufacturing Science and Technology Program is also
focused at developing flexible cluster processing for diverse families of low volume products [2]. Finally,
cluster tools have been gaining prevelance both in trade publications such as Semiconductor International
and trade shows such as Semicon West. [3]
Despite this growing prevelance, there is still controversy over how these cluster tools will be configured
and used in general commercial IC production. However, some resonable hypotheses can be made based
on current academic and industry-based publications. (e.g., [4], [5], [6]). This paper will assume that the
cluster tools of the mid to late 1990s will have the following features:

1. Single wafer processing modules will be potentially capable of any standard semiconductor process
other than lithography and ion implantation.

2. These chambers will be integrated into cluster tools such as those shown in Figure 1. A cassette
of wafers is placed in the loadlock and then wafers are moved one at a time by a central handler
to process modules. It will be possible to integrate modules, handlers, and loadlocks from different
equipment manufacturers.

36

/ SPIE Vol. 1393 Rapid Thermal and Related Processing Techniques (1990)

Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

LOADLOCK
LOADLOCK

Figure 1 : This paper defines a cluster tool as a system consisting of one or more loadlocks, a wafer handler,
and one or more processing modules.

3. The cluster tools will be instrumented to allow rapid processing and monitoring, while keeping
equipment-related overhead times low.

4. The cluster tool control system will be flexible enough to handle a wide variety of process diversity.

1.2 Scope of Paper

The economic advantages of these tools can be grouped into three categories:

Strategic: advantages related to the semiconductor finn's position in its industrial environment. For example: "The flexibility of cluster-based fabs could make it economically feasible to produce diverse low
volume, high profit margin products."
Fab Performance: improvements in the speed and cost of the production of conventional products. For
example: "The decreased time a wafer spends actually being processed could translate into an overall decrease in the time required to produce a completed wafer."

Technological: improvements in the process techology. For example: "The ability to quickly move a
wafer from one process to another under vacuum makes advanced multi-layer deposition of metals practical."

The scope of this paper will be limited to the second category of economic advantages in this list: potential
advantages in production of existing commercial products. The next section of this paper will identify the
potential time and cost based advantages of cluster-based fabs. After these potential advantages are described, the third section of this paper will present an example of how one would quantitatively determine
the extent (if any) of these advantages. Based on this analysis, the final section of this paper will discuss
what features of the cluster tools are likely to be important in determining the extent of the fab performance
advantages.

SPIE Vol. 1393 Rapid Thermal and Related Processing Techniques(1990) / 37

Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

Comparison of Annual Revenues

to Cost of a Fab
10

L.

10

>1

Co io2
>1
10

10

0
1960

year
Figure 2: The cost of a typical high volume commercial fab compared to the annual revenues of four major
U.S. merchant semiconductor firms.

2 Potential Advantages
2.1 Potential Cost Advantages
Figure 2 suggests an impending capital cost problem for semiconductor fabs. The running five-year average
revenues were taken from four major U.S. merchant semiconductor maufacturers (i.e., 1980 represents the
average of the annual revenues earned from 1978 to 1982) [71. The cost of a large commercial fab, when
plotted on the same log scale (extrapolated past 1990), shows that the cost of fabs is rising faster than the
revenues they are producing. This problem is likely to become significant as fab costs approach the annual

net profits, and then the annual revenues of these firms. Most of the cost of a fab today is due to the
processing equipment, whose cost is also generally rising at the same exponential rate as. fabs in Figure
2. [8]. This trend not only makes commercial scale production more expensive, it also makes technology
development more risky. This is because the rising equipment costs make the cost of the minimal fab
necessary to develop and evaluate a new technology more expensive.
The impact of cluster tools on this problem clearly depends on the capital cost of future cluster tools,
a subject of great uncertainty. Currently a typical four process module cluster may cost $1 million to $2
million, with the modules responsible for roughly half the cost. [6] Based on these numbers, cluster tools are
more expensive than their conventional counterparts for a given throughput rate, particularly when compared
to furnaces and other large batch machines. Nevertheless, many expect cluster tools to have a positive impact
on the capital cost rise of fabs for the reasons that follow.
First, cluster tools allow process equipment manufacturers to develop and sell specific technologies
without having to develop such additional "redundant" technologies as user interfaces, automated loading,
or loadlocks. These technologies would only need to be developed by the handler manufacturer, who could
presumeably reap advantages of mass production. In other words, future process technology in the form of
process modules could ultimately cost less than the same technologies in the form of stand-aloneconventional
machines. [6]
The modularity of the cluster tools suggests a second capital cost advantage. Retooling a cluster-based
fab for a new technology, such as the next generation of DRAMs, may cost less than retooling a similar
conventional fab. In a cluster fab, only obsolete process modules will need to be replaced, while the majority

38 / SPIE Vol. 1393 Rapid Thermal and Related Processing Techniques (1990)
Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

of the fab, including loadlocks and handlers, remain intact. As the technology advances, more modules can
be replaced. In a conventional fab, a relatively larger portion of the fab may need to be replaced. [611 For
this reason, the exponential rise in the capital cost of fabs with new technologies may at least be slowed by
cluster tools.
Finally, cluster tools may have a significant impact on the financial risk associated with developing a
new process. Because of their processing flexibility, a cluster-based minimal fab, necessary to process one
wafer, may require less total pieces of equipment than an equivalent minimal conventional fab. Even though
the cluster-based fab would have a smaller capacity, it could be used to develop, evaluate, and ramp up the
yield of the product, postponing capital outlays for volume ramp up and decreasing the financial penalty for
unsuccessful process technologies or process steps.
Incidentally, one should be aware that there are potential capital cost savings from technological advantages as well. For example, the existence of a loadlock in front of most of a fab's equipment may make
vacuum or nitrogen-filled carriers more practical, which could loosen clean room class requirements, which
could decrease the cost per foot of building and maintaining the clean room facility. [2]
An entire paper could be written predicting the cost of future cluster tools. The arguments would probably
need to include considerations of learning curves, inflation, industry structure, and the specific capabilities
of different modules. The Analysis section of this paper will instead make some simple assumptions about
cost, and show how this cost can affect the overall cost performance of the fab. Before doing that however,
it is important to identify another set of potential advantages stemming from the speed of cluster tools.

2.2 Potential Time Advantages

The time-based potential economic advantages of cluster tools are essentially based on the argument that
cluster-based fabs will be able to produce completed wafers in a shorter period of time than their conventional
counterparts can. Potential time savings stem from shorter process times, pipelining of process sequences,
and possibly less variations in process times resulting in shorter queue times. How well these factors actually
improve production times will be further examined in the next section of this paper. If the time improvements
can be demonstrated however, there are a number of potential economic advantages that could result, which
are described below.
One time-based candidate for improvement is the time to develop a new technology (e.g., the next
generation of DRAMs). The typical life cycle of many new semiconductor products has shrunk to two or
three years. [6] As products mature and grow obsolete, the market price and therefore profit margin of the
product may fall quite rapidly. Because of this, the financial success of a technology may depend on its
rapid introduction; introducing some products even a few months after competitors have introduced similar
products may result in as much as a 30% potential revenue loss. [9] Much of the technology development
may involve running small sequences of process steps over and over on a few wafers at a time, as well
as running the entire process sequence on a few wafers at a time. Reducing small volume process times
could therefore translate into faster process/evaluate cycles, which could speed learning and ultimately the
development of the product. [6] (The technological advantage of improved process monitoring and control
could have a similar impact on technology development time.)
A second time-based candidate for improvement is product prototype time. This is the time required to
produce a given design (i.e., mask set defined circuit) within an existing technology family. In a poll of
potential ASIC customers taken by Intel, prototype time was given as the second most important product
criterion (behind working the first time). Prototype time was ranked above high performance, unit cost,
device density, and development cost. In addition to increasing demand, fast prototype times may also result
in price premiums and therefore higher profit margins. [10]
A third time-based candidate for improvement is the throughput time of the fab. This paper defines
throughput time as the time elapsed from when the wafer enters the front end fab until it leaves the fab.
Other terms for throughput time have included cycle time, turnaround time, and manufacturing interval.
Throughput time has been gaining importance as a measure of fab performance for a number of reasons:

SPIE Vol. 1393 Rapid Thermal and Related Processing Techniques (1990) / 39
Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

First, lower throughput times result in a shorter time from process to functional testing, which meansprocess
problems such as out-ofspec process steps are discovered faster. Correcting such problems faster could result
in improved yields. Throughput time based yield improvements could also come from less total time exposed
to potential contamination. Second, lower throughput times could result in improved market responsiveness.
[1 1] A manager's choice of mix and volume of product starts is based to a large extent on predictions of
market demand at the time those wafers are completed. Decreasing that lead time could make costly bad
predictions less likely. Third, for a given throughput rate (i.e., wafers/month), decreasing throughput time
decreases work in process inventory. The market responsiveness just described previously could also reduce
finished goods inventory. Decreasing inventory levels can decrease wafer or chip carrying costs.

3 Analysis
The previous section of this paper has been generally speculative. It has basically described the advantages
that could be accrued if there were cost and time performance advantages associated with cluster-based fabs.
This section of the paper will focus on determining whether such cost and time performance advantages
exist. The main analysis technique is using a simulation and cost analysis program written at Stanford and
Texas Instruments. After presenting the results, the major sources of throughput time and wafer cost will be
described.

3.1 Simulation/Cost Analysis

The software used to perform the time and cost analysis is written as a series of Fortran submutines which in
turn call subroutines provided by a commercial queueing analysis software package called Siman. [12] The
software can be divided into three parts. The first part of the software reads in data from the eleven input
files described in Table 1. The second part runs performs a monte carlo simulation of the fab, producing
such statistics as throughput time for each lot, and equipment utilizations. The third part converts this data
into the summary statistics in the four output files listed in Table 2.

The results of the simulations clearly depend to a large extent on the input data. The simulations
described in this section compare a conventional, circa 1987 fab to a hypothetical cluster-based fab. One
twin-well, 2 metal layer, 1.5 micron CMOS process, based on Stanford's CMOS process is simulated in
each fab. To reflect a wide variety of low volume products, a lot size of 12 wafers is assumed. Module
process times were based on experience at Stanford with single-wafer processing as well as a survey of the
literature. Typical module processing times varied from 30 seconds to 4 minutes. The cluster-based fab
consists of 38 process modules arranged into 15 clusters. Each cluster has one loadlock. The cluster fab
also includes two veriticle batch furnaces, each with a capacity of 25 wafers, capable of high pressure/high
temperature oxidation and oxidation enhanced diffusion. The cluster-based lithography area is assumed to
be pipelined; that is, wafers are moved one at a time through the lithography seqence. Cluster tools are
assumed to have a six minute lot load time and a five minute unload time. Two minutes is assumed to pass
from the time a module is finished processing a wafer until the wafer is in the loadlock or next module.
Modules are assumed to have in situ process monitoring. Only circuit functionality is tested ex situ. Both
fabs are relatively small: the conventional fab has a maximum throughput of approximately 3400 wafers per
month; the cluster-based fab has a maximum throughput of approximately 2000 wafers per month.
The reader should be aware that many of these assumptions bias the results in favor of the conventional
fab. In particular, information made available after the simulations were performed suggest that the module
cost estimate is high, as is the estimate of the non-process overhead times associated with the clusters. In
addition, the conventional fab represents a 1987 technology, while the cluster-based fab represents a 1994
technology. Finally, the addition of more loadlocks to the clusters would have almost certainly improved the
cost performance of the cluster fab. Despite the fidelity of the input data, the general results are assumed to
still be valid. The qualitative results and tradeoffs, i.e., the shapes and relative positions of the curves, are

40

/ SPIE Vol. 1393 Rapid Thermal and Related Processing Techniques (1990)

Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

1. Product Mix: volume and recipe

index of each product

2. Process Recipes: lists of

operation sets for each recipe
3. Operation Sets: lists of steps

8. Operators: qualified machines, cost

9 Downtimes: random or deterministic up and

down times

4. Steps: setup and process time,

operator time, cost,
machine group

o. Overhead: recurring or nonrecurring,

5. Machine Groups: lists of machines

6. Machines: capacity, cost, area,
conditional setup time

7 Clusters: load/unload and transfer times,

configuration, cost

deterministic or a function of wip or area;

Depreciation time for nonrecurring
1 1 . Control: wip, screen volume,
simulate volume

Table 1 : Model input files

1.

Summary Statistics: Throughput rate, throughpt time, cost per wafer,

simulated time, etc.

2. Cost Statistics: Breakdown by source: by wafer and by year.

3. Machine Statistics: How the machine spends its time: processing,

down, idle, etc.; Average queue waiting time

4. Operator Statistics: How the operator spends time: load/unload,

process tend, idel, etc.; Average time full machine waits for operator.

Table 2: Model output files

SPIE Vol. 1393 Rapid Thermal and Related Processing Techniques (1990) / 41
Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

600

Throughput 4
rats

400

Median

Throughput

uster

(wafers

per hour) 2

Tim.
(hours)

ion

0
0

150
100
Work in Progress (lots)

50

200
0

200

100
50
150
Work in Progress (lots)

200

Figure 3: Simulation results show the effect of loading the different fabs. A high wip level implies heavy
loading.
600
Median

1200

400

Cost p.r

Throughput

Tim.
(hours)

ist.r

800

Wafer

200

iuster

0
0

(dollars) 400

6
4
2
Throughput Rat. (wafers p.r hour)

0
0

2
4
Throughput Rat. (waf.rs per hour)

Figure 4: As the throughput rate increases, congestion in fab increased, and throughput time degrades. On
the other hand, there are more wafers to amortize overhead, so cost per wafer goes down.
expected to be consistent with higher fidelity input data.
The reader should also be aware that the expense of carrying a large inventory (due to carrying costs
or yield loss), and an increased throughput time (due to customer loss or yield loss) are not included in the
model.
The eleventh file in Table 1 describes the parameters that control the simulation. In the simulation, the
work-in-pmcess inventory (or wip level) is held constant: when one lot leaves the fab, another enters the fab.
This allows one to easily see the effect of loading the fab. No statisitics are taken while the first screened
lots are completed, to avoid transient effects. Then the simulation is run until another specified number of
lots is completed. Figure 3 shows two plots of performance parameters versus the wip level. Each point
on a given plot represents a seperate simulation. These plots are mainly shown to provide insight into the
evaluation software; they are intermediate in obtaining the more meaningful plots in the next few figures.
The two plots of Figure 3 can be combined to form the left plot in Figure 4 by plotting the throughput
time versus the throughput rate for each wip level. The minimum throughput time, which is particularly
relevant to the potential advantage of fast technology development and rampup, can be read at the left side
of this plot. As the fab becomes more heavily loaded, utilization improves, but congestion gets worse. This
results in the throughput rate improving at the expense of throughut time. Eventually a throughput rate
assymptote is approached, where the idle time of the bottleneck machines goes to zero. In this region, the
plot reflects the cluster fab having a smaller capacity than the conventional fab.
The right-hand plot in Figure 4 shows how cost varies by throughput rate. The cost per wafer is calculated

42 / SPIE Vol. 1393 Rapid Thermal and Related Processing Techniques (1990)
Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

1200

cost p.r
wsf.r
(dollars)

800

0
0

400
200
msdlsn throughput time (hours)

600

Figure 5: The final performance comparison of the two fabs. The cluster fab offers shorter process times,

but at a cost premium.

by adding up all the overhead, such as salaries and equipment depreciation, and dividing that amount by
the number of wafers produced during that period. A processing and raw wafer cost is added to obtain a
final cost per wafer. The plot shows the fact that most of the cost per wafer is due to overhead (particularly
equipment, which is depreciated over five years). Thus, cost drops rapidly as the throughput rate increases.
The plot also shows that at a given throughput rate, the cluster-based fab will probably have a higher cost
per wafer. These plots are still somewhat intermediate, and are combined to form the final performance
analysis shown in Figure 5.
As mentioned in the previous section of this paper, cost per wafer and low throughput time each have
associated economic advantages. Figure 5 shows how these factors trade off against each other. Low
throughput times imply light factory loading which in turn lead to low throughput rates and high costs per
individual wafer. The plot shows a crossover point, where the throughput time is 220 hours and the cost
per wafer is between $650 and $660. This is of course higher than the $230 the conventional fab can
achieve near full utilization. The manager of the fab could then compare this plot to the potential profit
resulting from rapid turnaround semiconductor products and make the decision to invest in the cluster-based
fab accordingly.

3.2 Sources of Cost per Wafer and Throughput Time

Figure 6 shows how the cost per wafer breaks down for the two types of fabs in the region where the
fabs' utilizations are high. A cost of $50 per unprocessed wafer is assumed, which is the largest part of the
variable materials cost. "Other Overhead" includes the building cost, which is depreciated over 25 years,
utilities, and administrative and support salaries. The total cost of the building and electricity for the cluster
fab is less than for its conventional counterpart. This is a result of the smaller footprints of the cluster tools,
resulting in less building space being required.
Table 3 shows where (location) and how (function) the wafer spends its time in the fab. The results
shown were calculated analytically based on the simulation results of moderately loaded fabs. To reflect
recently acquired information on new wafer handlers, the cluster load time plus unload time was decreased
from 1 1 minutes to 7 minutes, and the wafer transfer time inside the cluster was lowered from 2 minutes
to 30 seconds. Depending on the module requirements and cluster control and hardware, the actual cluster
overhead times may even be less. [13]
The most striking part of Table 3 is the fact that in both fabs, the wafer spends most of its time waiting,

SPIE Vol. 1393 Rapid Thermal and Related Processing Techniques (1990) / 43
Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

700
600

E:J

500

materials
operators

cost per wafer

400
(dollars)

other
overhead

. equipment
0

cluster

conventional

Figure 6: Breakdown of cost per wafer in fabs with high utilizations.

CLUSTER

CONVENTIONAL

By Location:

By Location:

in cluster

36.4 hrs 32.2%

18.0%
0.8 hrs
0.7%
probe
between eqpmnt 50.7 hrs 49.2%

in conventional 20.3 hrs

TOTAL

108.2 hrs 100.0%

conventional process 7.4 hrs

TOTAL

104.6 hrs
3.7 hrs

29.2%
II .J
rio,
/0

between eqpmnt 249.7 hrs

69.8%

358.0 hrs 100.0%

TOTAL

By Function:

By Function:
module process
transport
wait/set up

in machines
probe

2.4 hrs
6.8 hrs

6.7%
2.1%
6.0%

96.5 hrs 85.3%

108.2 hrs 100.0%

processing
probe
transport

waitlset up
TOTAL

87.6 hrs
3.7 hrs
9.7 hrs
257.0 hrs

24.5%

II .V
ro,/0

2.7%
71.8%

358.0 hrs 100.0%

Table 3: Breakdown of throughput time by location and by function

44

/ SPIE Vol. 1393 Rapid Thermal and Related Processing Techniques (1990)

Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

wafer transport

th e r ma I

(non-metal) 30.2 mins 1.4%

dry etching

32.3 mins 1.5%

metal
0.5%

CVD/PVD

12.0 mins

resist ash

30.0 mins

clean

39.0 mins 1.8%

TOTAL

1 .4%

36.4

69.0 mins 3.2%

cluster overhead 378.0 mins 17.3%

wait caused by
module cleaning

60.5 mins

2.8%

wait caused by

wafer transport 594.0 mins 27.2%

wait caused by
processing

941.4 mins 43.1%

hrs 100.0%

Table 4: Breakdown of the time a wafer spends in cluster tools

either inside a cluster waiting for a module, or outside a machine, waiting for the machine to become
available. The machine could be either occupied by another lot (most likely), or being serviced or repaired.
(Machine downtimes in the fab generally varied from 5% to 20%). In a heavily loaded fab, the waiting
times between equipment would be even higher.
The time a wafer spends in the cluster is further broken down in Table 4. In this table "cluster overhead"
refers to the sum of the load and unload times (including pumpup/pumpdown). The wait times are also
broken down. CVD modules are assumed to require a 30 second clean between each wafer. It is felt that this
table in particular has strong implications for the design and use of cluster tools for commercial production.
These implications are described in the next section.

4 Implications
The process capability of the modules will always, of course, be a prime determinant of the economic success
of the cluster tool. Another critical technical area is the ability to integrate these processes. The results of
the previous section suggest that there are other issues critical to the economic success of the cluster tool as
well. This section divides these issues into three groups: Cost, Time, and Management.

4.1

Cost

Thecost of process modules and wafer handlers is important in two ways. First, if the clusters are sufficiently
versatile, the cost of a minimum factory necessary to develop and evaluate a new technology may be superior
to its conventional counterpart. Second, the cost per throughput of the machine will probably be the biggest
component of wafer cost in a full scale commercial fab.

The robustness of the wafer handler is also expected to be a big determinant of the cost per wafer as
technologies evolve. The handler and loadlocks may be between one fourth and one half of the total cost of
the cluster, which implies less expensive fab retooling for future technologies, if only obsolete modules need
to be replaced. Therefore, the hardware, control, and standards requirements for achieving such robustness
is an important distinct factor in the clusters' utility.
Finally, the use of clusters instead of conventional tools is likely to have an effect on other costs of the
manufacturing facility. Smaller footprints may imply smaller and thus less expensive clean rooms. Loadlock
capabilities may imply looser clean room requirements. The higher level of complexity of the cluster tools

SPIE Vol. 1393 Rapid Thermal and Related Processing Techniques(1990) / 45

Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

may also imply higher CIM costs. Thus, factors such as footprint, the availability of carriers to prevent lots
from seeing atmosphere, and CIM capabilities are also factors in determining cluster's utility.

4.2 Time
Clearly, process times are a prime component of throughput time and thus the clusters' economic utility.
Although the time a wafer spends being processed may be relatively small, the time the wafer waits while
other wafers are pmcessed is the largest component of the time a wafer spends in the cluster tool. Referring
back to Table 4, one can see the relative contribution of the different processes to the total throughput time.
Note the significance of cleaning. This figure is based on the fairly conservative estimate of two 60 second
cleans before each unintempted sequence of non-metal thermal steps, and one 60 second clean before each
sequence of metal depositions. The state of the art may require longer cleans, especially for such purposes
as particle removal. If cleaning is to be integrated into cluster sequences, which is as likely for technical
reasons as economic reasons, then cleaning is likely to gain particular importance in determining the fab
performance.
The time to get a wafer out of one module and into another module is also a major component of the
cluster throughput time. The actual time the robot is moving the wafer may only be a small fraction of this
time. Other components of this time include communications between the module and the handler, opening
and closing of ports, and wafer flat finding. Communications times may be a factor of software as well as
hardware. The time associated with each of these factors can be significant, and are non-trivial to optimize.
Nevertheless, the total wafer transfer time has been rapidly decreasing as the technology has advanced over
the last few years. [13]
The cluster overhead time associated with loading and unloading lots is also a significant component of
throughput time. Like wafer transfer, this is determined by a wide variety of factors: opening and closing
of ports, pumpup and pumpdown times, communications, and time for the operator to specify the desired
sequence of process steps. The last factor may become particularly important as the variety of products
in the fab increases and the volume of each product decreases, a likely environment for such fabs. [14]
Improvements in hardware, software, and user interfacing suggests a wide variety of potential improvements
in this area.
Other sources of cluster throughput time include module in situ cleans and monitoring. In both cases
the preceding analysis made conservative assumptions. Monitoring could end up being the most critical
non-process issue in determining the economic utility of the cluster tool. As stated before, it is assumed
in this analysis that all thin film measurements can be carried out in the process module as the process
is carried out. Seperate modules for metrology could degrade the performance of the cluster-based fab,
and using conventional diagnostic tools such as stand-alone microscopes and ellipsometers could eliminate
cost/time advantages of the cluster fab in most production environments.

4.3 Management
Given an available set of wafer handlers, modules, and loadlocks, there are still a number of decisions to be
made by a fab manager which could determine the extent of the performance advantages resulting from the
clusters. The management issues that follow, despite their potential significance, are not trivial to solve, and
constitute problems for research themselves. It should also be noted that each of the four issues that follow

configuration, lot size, scheduling, and product mix are all interdependent. That is, one decision effects
the optimum decisions in the other areas.
The first management issue is that of fab configuration. A significant source of the throughput time
improvement as well as wafer cost improvement (through throughput rate improvement) of the cluster fab
is pipelining. Pipelining in this context means dividing the lot into wafers and then processing the stream of
wafers through the sequence of modules. This results in a throughput time improvement since pipelining a
lot is faster than processing all the wafers in the lot on one single-wafer processor before moving the lot to

46

/ SPIE Vol. 1393 Rapid Thermal and Related Processing Techniques (1990)

Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

the next processor. Pipelining results in throughput rate improvements by decreasing the potential utilization
loss of process modules waiting for lot load/unload events. The combination of modules, particularly the
bottleneck module (with the lowest idle rate), determine the extent of these advantages. In the simulations
that were run, it became apparent that a lot would need to visit many clusters more than once, and many times
a lot would not use every module in the cluster. Some work by the authors, done since the simulations, have
also suggested that the number of loadlocks on the cluster can have a dramatic effect on the perfonnance
of the cluster fab. For these reasons, choosing how to arrange the modules into clusters turned out to be a
surprisingly difficult problem.

Lot size is a second issue that is likely to have a much larger impact in cluster-based fabs than in
conventional fabs. This is due to a significant amount of equipment in cluster fabs being single-wafer
processors with overhead times, such as load/unload times, associated with lots. Longer overhead times
result in larger optimum lot sizes, while longer wafer processing times result in smaller optimum lot sizes.
The potential performance improvement of lotsize decisions can be seen by referring back to Tables 3 and
4. Very small lotsizes, for example, have the potential to lower the wait times for module processing and
transport to less than the total process times, but at the expense of increasing waits in between equipment.
Third, there are a number of scheduling issues faced by the manager of a cluster-based fab. Choosing
when to introduce lots into the fab and which waiting lots to process next in a machine have already been
shown in other work to have potential improvements in fab performance. (for example, [15]) In the clusterbased fab there is the additional issue of scheduling which wafer the handler should grab next. This is
a particular challenge when there are multiple loadlocks with lots requiring different process sequences.
Adding even more complexity is the option of ejecting lots to be run in other cluster tools with identical
modules. Initial work with multiple-loadlock systems have shown that significant performance improvements
can result from non-obvious cluster-level scheduling rules.
Finally, product mix may be the most subtle of the four management issues listed. A previous work has
used modeling of small, abstract fabs to illustrate the idea that increased variability in a fab can degrade the
performance of a fab. Sources of this variability include random introduction of a wide variety of process
flows, and unscheduled rather than scheduled downtime. The work also showed that having multiple copies
of equipment improved immunity to this degradation. [16] Thus, many copies of low capacity equipment
may be superior to a collection of unique high capacity machines for high product variability environments.

The prior fab description is likely to apply to a cluster-based fab. A fab manager may be able to take
advantage of this effect by differentiating products and process flows to create user-specific products with
higher profit margins. Clearly, the ability of the fab to handle wide diversity of products also depends on
the control systems and user interfaces of the cluster tools.

Conclusion

This paper has focused on the potential economic advantages that rapid multiprocessors, in the form of cluster tools, offer in the area of fab performance. These potential advantages include less expensive production
of wafers at shorter throughput times. In addition to process technology issues, there are a wide variety of
other unresolved issues that will ultimately determine the extent of these advantages. Examples of these
issues include process times, monitoring, control, and cluster configurations.

Acknowledgements
This work was supported in part by the Semiconductor Research Corporation.

SPIE Vol. 1393 Rapid Thermal and Related Processing Techniques(1990) / 47

Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

suuj;i
[11

SV 'NPU10H A'U ')jJOH

'U!SS)
[zIl

rI

fQ

1Sflj3,, 'SJOOJ 1-I1d :z

Z01i6

.iqwid '0661 sd

Th191 J'JVIU

sqj q oqi Lioioj Jo qi almnd JOJ OUrnIOA-MO'l diq ,UOflOflpOJd '1U04d?1

UOSJAJ pjnoj,,
LZ
1th?1UItf '6861

[l l1!d

sd

PU21UI,, :uissoo.ij LL S0661 'pU.ij JOJ3flpUO3W' 'j'VUOIJVUJdJUJ

69-59

ftl J)I

1 1! P!dL, 11flUJitL U!SSWdfl1flJ1o1 W3! 's!Jo1o1d JIdS

'usaoj

aluo4391aoJ3
[SI

'UEUIO)1?
JOflPUO31U1)S 'lVUolWUJfluj

I(flO

OO1MON

'tfl1UOJ!J .IqO1DO 6861

.iiSfljj,, :sjooj V SSOO.Id

j,UOflfljOs

JOJZfl7YUO3lUI?5 'lVUO?WUJJUJ

OUflf

WfliSOdUIe(SJo _iJiT

iJflf '0661

L8-Z8
[91

L IN qNJ
'0661 soEd

sodj

&quo,, oi qi

[oil

'UtI [E'M UD,,

uo

dn-j SSflOH

JO f std
[jJ j sruuu upd uoanpo.auj
j] [j

o' uvuis

0661

fcIsM .1 USJAI

[j]

'L861

ui "1A

'Ul.fltl3VfflUVJ4J

[9j]

jy

S!

'9 6861

JO

Auudwo3 '11utApy

sws uippo

ssausng 'Ma?tta!

'0P13!MS'Vd i(.flflUf 6861

'1UOWOJ:I

'IUIOJq .iqw1thS '9Z

:inoq oil ia L$ UO!jA uo :iusui 'S3IV 'SdlUO43 Jqtu1thS

ri
sd

y's)
stu

/ 3IdS /A 611 P!de& /ewieqj pue peji

'UOfl11OdJO3

'uiwj oid'>j 'i2OOUIjOJ

'i: tSfl2fly '8861

'UO11?1

'piul 'jcuo:ioj,

1!

Jo1onpuoo!ws

'poo wr 'uos.u1?H

'doysyoj

9t

UO211Ud,,

std z:-i:

ouaiwj

ii

.lc-li7

[T1 1AUJ UOflES1AUOO qip puajy

'E

S1XLL 's1UouJTu1suI

'uu 'saiuoa'q judy '6861 sd L9Z9

u sisv 'sa,iuozwaq isn2ny '9 'L861 sd t9-O9

1XN 3OS

"IP1S

lSfl2flV-iClflf'8861

[j7J]

iusaid

UA! iCq U0p109 JOOIA 11 UOJU%fl '1!1A!Ufl

[61

sd

U!1w 'SSSO3OJd Jopnpuoa?waS 'l'!W'V'I :jsn2nV

11Sflj3,, 'STOOLL U'd :j

E9-sc

01 'SJp1Oq)pO1S WOJJ 0961 oi

[LI pnuuy
Jo1onpuoo!uIS

[sI 'IPL

'6861

oET-cJI

OUtUUOJ1d,,

'JqWOAO 6861

suopavSuVJL uo Jalanpuoa.lwas'

uppo Jo iossoo.idujn 'sqd 3ITS -J,vJI

UISSO3OJd S8flbIUL/3J (0661)

Downloaded From: http://proceedings.spiedigitallibrary.org/ on 12/16/2015 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx