EXPERIMENT NO 12

AIM: INTRODUCTION TO HARWARE DESCRIPTION LANGUAGE (VHDL).

TOOLS REQUIRED:
1) PC WITH WINDOWS XP
2) XILINX ISE 9.2I
PROCEDURE:
1) Double click on XILINX ISE 9.2i icon
2) Select new project and select the VHDL Module.

3) Define the IN and OUT ports

4) Write Code for the circuit to be generated.

5) Select file and check its syntax

6) If no error then view its RTL schematic

7) Again go to new project and select Test bench module and give a file name

8) Select Combinatorial clock

9) Set the waveform as per requirement

9) In source window select Behavioral Simulation and simulate the .tbw file