SEMICONDUCTOR TECHNICAL DATA

  !

 !
 !
HighPerformance SiliconGate CMOS

 
J SUFFIX
CERAMIC PACKAGE
CASE 73203

20
1

The MC54/74HC244A is identical in pinout to the LS244. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed to be
used with 3state memory address drivers, clock drivers, and other
busoriented systems. The device has noninverting outputs and two
activelow output enables.
The HC244A is similar in function to the HC240A and HC241A.

N SUFFIX
PLASTIC PACKAGE
CASE 73803

20
1

DW SUFFIX
SOIC PACKAGE
CASE 751D04

20
1

Output Drive Capability: 15 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 136 FETs or 34 Equivalent Gates

SD SUFFIX
SSOP PACKAGE
CASE 940C03

DT SUFFIX
TSSOP PACKAGE
CASE 948E02

20

20

ORDERING INFORMATION
Ceramic
MC54HCXXXAJ
Plastic
MC74HCXXXAN
SOIC
MC74HCXXXADW
SSOP
MC74HCXXXASD
TSSOP
MC74HCXXXADT

LOGIC DIAGRAM

A1
A2
A3
A4
DATA
INPUTS

B1
B2
B3
B4

18

16

14

12

11

13

15

17

PIN ASSIGNMENT

YA1
YA2
YA3
YA4
NONINVERTING
OUTPUTS

ENABLE A

20

VCC

A1

19

ENABLE B

YB4

18

YA1

A2

17

B4

YB3

16

YA2

A3

15

B3

YB2

14

YA3

YB2

A4

13

B2

YB1

12

YA4

YB3

GND

10

11

B1

YB1

YB4

FUNCTION TABLE
OUTPUT
ENABLES

PIN 20 = VCC
PIN 10 = GND

1
ENABLE A
19
ENABLE B

Inputs

Outputs

Enable A,
Enable B

A, B

YA, YB

L
L
H

L
H
X

L
H
Z

Z = high impedance

2/97

Motorola, Inc. 1997

REV 7

MC54/74HC244A

MAXIMUM RATINGS*
Symbol
VCC

Parameter

DC Supply Voltage (Referenced to GND)

Value

Unit

0.5 to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

0.5 to VCC + 0.5

DC Input Current, per Pin

20

mA

Iout

DC Output Current, per Pin

35

mA

ICC

DC Supply Current, VCC and GND Pins

75

mA

750
500
450

mW

65 to + 150

_C

Iin

PD

Tstg
TL

Power Dissipation in Still Air, Plastic or Ceramic DIP

SOIC Package
SSOP or TSSOP Package
Storage Temperature

This device contains protection

circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

_C

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC, SSOP or TSSOP Package)
(Ceramic DIP)

260
300

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
Ceramic DIP: 10 mW/_C from 100_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
SSOP or TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

v
v

v
v

RECOMMENDED OPERATING CONDITIONS

Symbol
VCC

Vin, Vout

Parameter

DC Supply Voltage (Referenced to GND)

Min

Max

Unit

2.0

6.0

VCC

55

+ 125

_C

0
0
0

1000
500
400

ns

DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr, tf

Input Rise and Fall Time

(Figure 1)

VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

VCC
V

55 to
25_C

85_C

125_C

Unit

VIH

Minimum HighLevel Input

Voltage

Vout = VCC 0.1 V

|Iout|
20 A

2.0
3.0
4.5
6.0

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

1.5
2.1
3.15
4.2

VIL

Maximum LowLevel Input

Voltage

Vout = 0.1 V
|Iout|
20 A

2.0
3.0
4.5
6.0

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

0.5
0.9
1.35
1.8

Minimum HighLevel Output

Voltage

Vin = VIH
|Iout|
20 A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.2
3.7
5.2

VOH

Vin = VIH

MOTOROLA

|Iout|
|Iout|
|Iout|

2.4 mA
6.0 mA
7.8 mA

HighSpeed CMOS Logic Data

DL129 Rev 6

MC54/74HC244A

v
v

v
v

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol
VOL

Parameter

Test Conditions

Vin = VIL
|Iout|
20 A

Maximum LowLevel Output

Voltage

Vin = VIL

Iin
IOZ

Maximum Input Leakage Current

ICC

Maximum Quiescent Supply

Current (per Package)

Maximum ThreeState Leakage

Current

|Iout|
|Iout|
|Iout|
Vin = VCC or GND

2.4 mA
6.0 mA
7.8 mA

Output in HighImpedance State

Vin = VIL or VIH
Vout = VCC or GND
Vin = VCC or GND
Iout = 0 A

VCC
V

55 to
25_C

85_C

125_C

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.4
0.4
0.4

6.0

0.1

1.0

1.0

6.0

0.5

5.0

10

6.0

4.0

40

160

Unit
V

NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola High
Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

S b l
Symbol

P
Parameter

VCC
V

55 to
25_C

85_C

125_C

U i
Unit

tPLH,
tPHL

Maximum Propagation Delay, A to YA or B to YB

(Figures 1 and 3)

2.0
3.0
4.5
6.0

96
50
18
15

115
60
23
20

135
70
27
23

ns

tPLZ,
tPHZ

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

2.0
3.0
4.5
6.0

110
60
22
19

140
70
28
24

165
80
33
28

ns

tPZL,
tPZH

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

2.0
3.0
4.5
6.0

110
60
22
19

140
70
28
24

165
80
33
28

ns

tTLH,
tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

2.0
3.0
4.5
6.0

60
23
12
10

75
27
15
13

90
32
18
15

ns

Maximum Input Capacitance

10

10

10

pF

Maximum ThreeState Output Capacitance (Output in

HighImpedance State)

15

15

15

pF

Cin

Cout

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High
Speed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD

P
Di
i i C
i
(P
ff )*
Power
Dissipation
Capacitance
(Per B
Buffer)*

34

F
pF

* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).

HighSpeed CMOS Logic Data

DL129 Rev 6

MOTOROLA

MC54/74HC244A
SWITCHING WAVEFORMS
tr

tf

DATA INPUT
A OR B

VCC

VCC

90%
50%
10%

GND

tPLH

50%

ENABLE
A OR B

GND
tPZL

tPHL
90%
50%
10%

OUTPUT
YA OR YB

tPZH
tTHL

HIGH
IMPEDANCE

50%

OUTPUT Y

tTLH

tPLZ

OUTPUT Y

tPHZ

10%

VOL

90%

VOH

50%

Figure 1.

HIGH
IMPEDANCE

Figure 2.

TEST CIRCUITS
TEST POINT

TEST POINT

OUTPUT
DEVICE
UNDER
TEST

OUTPUT
DEVICE
UNDER
TEST

CL*

* Includes all probe and jig capacitance

1 k

CL*

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.

* Includes all probe and jig capacitance

Figure 3. Test Circuit

Figure 4. Test Circuit

PIN DESCRIPTIONS
INPUTS

to these pins, the outputs are enabled and the devices function as noninverting buffers. When a high level is applied, the
outputs assume the high impedance state.

A1, A2, A3, A4, B1, B2, B3, B4

(Pins 2, 4, 6, 8, 11, 13, 15, 17)
Data input pins. Data on these pins appear in noninverted
form on the corresponding Y outputs, when the outputs are
enabled.

OUTPUTS
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
(Pins 18, 16, 14, 12, 9, 7, 5, 3)

CONTROLS

Device outputs. Depending upon the state of the output

enable pins, these outputs are either noninverting outputs or
highimpedance outputs.

Enable A, Enable B (Pins 1, 19)

Output enables (activelow). When a low level is applied

MOTOROLA

HighSpeed CMOS Logic Data

DL129 Rev 6

MC54/74HC244A
LOGIC DETAIL
TO THREE OTHER
A OR B INVERTERS

ONE OF 8
INVERTERS
VCC

DATA
INPUT
A OR B

YA
OR
YB

ENABLE A OR
ENABLE B

HighSpeed CMOS Logic Data

DL129 Rev 6

MOTOROLA

MC54/74HC244A
OUTLINE DIMENSIONS

20

11

10

J SUFFIX
CERAMIC PACKAGE
CASE 73203
ISSUE E

NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.

B
A
L

DIM
A
B
C
D
F
G
H
J
K
L
M
N

N
H

MILLIMETERS
MIN
MAX
23.88
25.15
6.60
7.49
3.81
5.08
0.38
0.56
1.40
1.65
2.54 BSC
0.51
1.27
0.20
0.30
3.18
4.06
7.62 BSC
0_
15 _
0.25
1.02

INCHES
MIN
MAX
0.940
0.990
0.260
0.295
0.150
0.200
0.015
0.022
0.055
0.065
0.100 BSC
0.020
0.050
0.008
0.012
0.125
0.160
0.300 BSC
0_
15_
0.010
0.040

SEATING
PLANE

N SUFFIX
PLASTIC PACKAGE
CASE 73803
ISSUE E

A
20

11

10

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

B
L

SEATING
PLANE

M
N

E
G

J
D

T A

11

10X

P
0.010 (0.25)

10

20X

0.010 (0.25)

T A

J
S

F
R X 45 _
C
T
18X

SEATING
PLANE

T B

DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D04
ISSUE E

A
20

20 PL

0.25 (0.010)

20 PL

0.25 (0.010)

MOTOROLA

DIM
A
B
C
D
E
F
G
J
K
L
M
N

INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040

MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R

MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75

INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029

HighSpeed CMOS Logic Data

DL129 Rev 6

MC54/74HC244A
OUTLINE DIMENSIONS
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940C03
ISSUE B
K REF
0.12 (0.005)

20X

20

L/2

T U

0.25 (0.010)
S

N
M

11

N
B

F
DETAIL E

PIN 1
IDENT

10

A
V
0.20 (0.008)

T U

J1

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR INTRUSION SHALL NOT
REDUCE DIMENSION K BY MORE THAN 0.07 (0.002)
AT LEAST MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE W.

K1

DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M

SECTION NN

0.076 (0.003)
T

SEATING
PLANE

C
D

DETAIL E

20X

0.15 (0.006) T U

DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E02
ISSUE A

K REF

0.10 (0.004)

T U

K
K1

2X

L/2

20

11

J J1

B
U

L
PIN 1
IDENT

SECTION NN

10

0.25 (0.010)

N
0.15 (0.006) T U

N
F
DETAIL E
W

C
D

DETAIL E

0.100 (0.004)
T SEATING

INCHES
MIN
MAX
0.278
0.288
0.205
0.212
0.068
0.078
0.002
0.008
0.024
0.037
0.026 BSC
0.023
0.030
0.003
0.008
0.003
0.006
0.010
0.015
0.010
0.013
0.301
0.311
0_
8_

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE W.

A
V

MILLIMETERS
MIN
MAX
7.07
7.33
5.20
5.38
1.73
1.99
0.05
0.21
0.63
0.95
0.65 BSC
0.59
0.75
0.09
0.20
0.09
0.16
0.25
0.38
0.25
0.33
7.65
7.90
0_
8_

DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M

MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50

1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_

INCHES
MIN
MAX
0.252
0.260
0.169
0.177

0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_

PLANE

HighSpeed CMOS Logic Data

DL129 Rev 6

MOTOROLA

MC54/74HC244A

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals
must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
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MOTOROLA

MC74HC244A/D
HighSpeed CMOS Logic Data
DL129 Rev 6