SEMICONDUCTOR TECHNICAL DATA

  

$ "!%$" "
"%$!%$ $ #$"
&$ $ $$ %$!%$# J SUFFIX
CERAMIC PACKAGE
High–Performance Silicon–Gate CMOS 16 CASE 620–10
1
The MC54/74HC595A is identical in pinout to the LS595. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC595A consists of an 8–bit shift register and an 8–bit D–type latch N SUFFIX
with three–state parallel outputs. The shift register accepts serial data and 16 PLASTIC PACKAGE
provides a serial output. The shift register also provides parallel data to the CASE 648–08
1
8–bit latch. The shift register and latch have independent clock inputs. This
device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the Motorola SPI serial data port on D SUFFIX
CMOS MPUs and MCUs. SOIC PACKAGE
16
• Output Drive Capability: 15 LSTTL Loads 1
CASE 751B–05
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA 16
DT SUFFIX
TSSOP PACKAGE
• High Noise Immunity Characteristic of CMOS Devices
1 CASE 948F–01
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 328 FETs or 82 Equivalent Gates ORDERING INFORMATION
• Improvements over HC595 MC54HCXXXAJ Ceramic
— Improved Propagation Delays MC74HCXXXAN Plastic
— 50% Lower Quiescent Power MC74HCXXXAD SOIC
— Improved Input Noise and Latchup Immunity MC74HCXXXADT TSSOP

LOGIC DIAGRAM PIN ASSIGNMENT

SERIAL QB 1 16 VCC
DATA 14 15
A QA QC 2 15 QA
INPUT 1
QB
2 QD 3 14 A
QC
3 PARALLEL QE 4 13 OUTPUT ENABLE
QD
4 DATA QF 5 12 LATCH CLOCK
SHIFT QE OUTPUTS
LATCH 5
REGISTER QF QG 6 11 SHIFT CLOCK
6 QH 7 10 RESET
QG
7
QH GND 8 9 SQH
SHIFT 11
CLOCK
10 9 SERIAL
RESET SQH DATA
LATCH 12 OUTPUT
CLOCK
OUTPUT 13
ENABLE

VCC = PIN 16
GND = PIN 8

10/95

 Motorola, Inc. 1995 1 REV 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC54/74HC595A
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Value Unit This device contains protection

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
due to high static voltages or electric
Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V fields. However, precautions must

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V be taken to avoid applications of any

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
voltage higher than maximum rated
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Iout DC Output Current, per Pin ± 35 mA cuit. For proper operation, Vin and

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vout should be constrained to the
ICC DC Supply Current, VCC and GND Pins ± 75 mA v
range GND (Vin or Vout) VCC. v
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic or Ceramic DIP† 750 mW

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tied to an appropriate logic voltage
SOIC Package† 500
level (e.g., either GND or VCC).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TSSOP Package† 450
Unused outputs must be left open.
_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Tstg Storage Temperature – 65 to + 150
_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package) 260

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Ceramic DIP) 300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage 0 VCC V
(Referenced to GND)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
(Figure 1) VCC = 4.5 V 0 500

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
VCC = 6.0 V 0 400

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC – 55 to
v v 25_C 85_C 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v
Voltage |Iout| 20 µA 4.5 3.15 3.15 3.15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
v
Voltage |Iout| 20 µA 4.5 1.35 1.35 1.35

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 6.0 1.8 1.8 1.8

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VOH Minimum High–Level Output
v
Vin = VIH or VIL 2.0 1.9 1.9 1.9 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Voltage, QA – QH |Iout| 20 µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin = VIH or VIL |Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ |Iout| 7.8 mA 6.0 5.48 5.34 5.2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output
v
Vin = VIH or VIL 2.0 0.1 0.1 0.1 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Voltage, QA – QH |Iout| 20 µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin = VIH or VIL |Iout| 6.0 mA 4.5 0.26 0.33 0.4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ |Iout| 7.8 mA 6.0 0.26 0.33

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
0.4

MOTOROLA 2 High–Speed CMOS Logic Data

DL129 — Rev 6
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC595A

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Continued)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v v
VCC – 55 to

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
v
Voltage, SQH IIoutI 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
vv ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = VIH or VIL IIoutI 4.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
IIoutI 5.2 mA 6.0 5.48 5.34 5.2
VOL Maximum Low–Level Output V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = VIH or VIL 2.0 0.1 0.1 0.1
v
Voltage, SQH IIoutI 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
vv ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 0.1 0.1 0.1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = VIH or VIL IIoutI 4.0 mA 4.5 0.26 0.33 0.4
IIoutI 5.2 mA 6.0 0.26 0.33 0.4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
IOZ Maximum Three–State Leakage Output in High–Impedance State 6.0 ± 0.5 ± 5.0 ± 10 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Current, QA – QH Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Quiescent Supply Vin = VCC or GND 6.0 4.0 40 160 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
Current (per Package) lout = 0 µA

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC – 55 to
v v
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 6.0 4.8 4.0 MHz
(Figures 1 and 7) 4.5 30 24 20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 35 28 24

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Shift Clock to SQH 2.0 140 175 210 ns
tPHL (Figures 1 and 7) 4.5 28 35 42

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 24 30 36

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL Maximum Propagation Delay, Reset to SQH 2.0 145 180 220 ns
(Figures 2 and 7) 4.5 29 36 44

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 6.0 25 31 38

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Latch Clock to QA – QH 2.0 140 175 210 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL (Figures 3 and 7) 4.5 28 35 42
6.0 24 30 36

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ, Maximum Propagation Delay, Output Enable to QA – QH 2.0 150 190 225 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHZ (Figures 4 and 8) 4.5 30 38 45
6.0 26 33 38

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZL, Maximum Propagation Delay, Output Enable to QA – QH 2.0 135 170 205 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZH (Figures 4 and 8) 4.5 27 34 41
6.0 23 29 35

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, QA – QH 2.0 60 75 90 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL (Figures 3 and 7) 4.5 12 15 18

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 10 13 15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, SQH 2.0 75 95 110 ns
tTHL (Figures 1 and 7) 4.5 15 19 22

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 13 16 19

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin Maximum Input Capacitance — 10 10 10 pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cout Maximum Three–State Output Capacitance (Output in — 15 15 15 pF
High–Impedance State), QA – QH
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 300 pF
2
* Used to determine the no–load dynamic power consumption: PD = CPD VCC f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).

High–Speed CMOS Logic Data 3 MOTOROLA

DL129 — Rev 6
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC54/74HC595A

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC 25_C to

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter V – 55_C 85_C 125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tsu Minimum Setup Time, Serial Data Input A to Shift Clock 2.0 50 65 75 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 5) 4.5 10 13 15
6.0 9.0 11 13

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tsu Minimum Setup Time, Shift Clock to Latch Clock 2.0 75 95 110 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 6) 4.5 15 19 22

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 13 16 19

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
th Minimum Hold Time, Shift Clock to Serial Data Input A 2.0 5.0 5.0 5.0 ns
(Figure 5) 4.5 5.0 5.0 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 5.0 5.0 5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
trec Minimum Recovery Time, Reset Inactive to Shift Clock 2.0 50 65 75 ns
(Figure 2) 4.5 10 13 15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 9.0 11 13

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Reset 2.0 60 75 90 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 2) 4.5 12 15 18
6.0 10 13 15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Shift Clock 2.0 50 65 75 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 1) 4.5 10 13 15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 9.0 11 13

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Latch Clock 2.0 50 65 75 ns
(Figure 6) 4.5 10 13 15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 9.0 11 13

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns
(Figure 1) 4.5 500 500 500

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ FUNCTION TABLE

6.0 400 400 400

Inputs Resulting Function

Serial Shift Latch Serial Parallel
Input Shift Latch Output Register Register Output Outputs
Operation Reset A Clock Clock Enable Contents Contents SQH QA – QH
Reset shift register L X X L, H, L L U L U
Shift data into shift H D L, H, L D → SRA; U SRG → SRH U
register SRN → SRN+1
Shift register remains H X L, H, L, H, L U U U U
unchanged
Transfer shift register H X L, H, L U SRN → LRN U SRN
contents to latch register
Latch register remains X X X L, H, L * U * U
unchanged
Enable parallel outputs X X X X L * ** * Enabled
Force outputs into high X X X X H * ** * Z
impedance state
SR = shift register contents D = data (L, H) logic level X = don’t care * = depends on Reset and Shift Clock inputs
LR = latch register contents U = remains unchanged Z = high impedance ** = depends on Latch Clock input

MOTOROLA 4 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC595A

PIN DESCRIPTIONS

INPUTS Latch Clock (Pin 12)

Storage Latch Clock Input. A low–to–high transition on this
A (Pin 14) input latches the shift register data.
Serial Data Input. The data on this pin is shifted into the Output Enable (Pin 13)
8–bit serial shift register. Active–low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
CONTROL INPUTS on this input forces the outputs (QA–QH) into the high–
impedance state. The serial output is not affected by this
Shift Clock (Pin 11) control unit.
Shift Register Clock Input. A low– to–high transition on this
OUTPUTS
input causes the data at the Serial Input pin to be shifted into
the 8–bit shift register. QA – QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Noninverted, 3–state, latch outputs.
Reset (Pin 10) SQH (Pin 9)
Active–low, Asynchronous, Shift Register Reset Input. A Noninverted, Serial Data Output. This is the output of the
low on this pin resets the shift register portion of this device eighth stage of the 8–bit shift register. This output does not
only. The 8–bit latch is not affected. have three–state capability.

High–Speed CMOS Logic Data 5 MOTOROLA

DL129 — Rev 6
MC54/74HC595A

SWITCHING WAVEFORMS

tr tf tw
VCC VCC
SHIFT 90% 50%
50% RESET
CLOCK GND
10% GND
tw tPHL

1/fmax 50%
OUTPUT
tPLH tPHL SQH
90% trec
OUTPUT
SQH 50% SHIFT VCC
10% 50%
CLOCK
tTLH tTHL GND

Figure 1. Figure 2.

VCC
LATCH VCC OUTPUT 50%
50% ENABLE GND
CLOCK
GND tPZL tPLZ
HIGH
50% IMPEDANCE
tPLH tPHL OUTPUT Q
10% VOL
90%
QA–QH 50% tPZH tPHZ
90% VOH
OUTPUTS 10%
OUTPUT Q 50% HIGH
tTLH tTHL
IMPEDANCE

Figure 3. Figure 4.

VCC
SHIFT
VALID 50%
CLOCK
VCC GND
SERIAL
50% tsu
INPUT A
GND VCC
tsu th LATCH
50%
VCC CLOCK
LATCH GND
50% tw
CLOCK
GND

Figure 5. Figure 6.

TEST CIRCUITS

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

* Includes all probe and jig capacitance * Includes all probe and jig capacitance
Figure 7. Figure 8.

MOTOROLA 6 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC595A

EXPANDED LOGIC DIAGRAM

OUTPUT 13
ENABLE

LATCH 12
CLOCK

SERIAL 14 15
D Q D Q QA
DATA
INPUT A SRA LRA
R

1
D Q D Q QB
SRB LRB
R

2
D Q D Q QC
SRC LRC
R

3
D Q D Q QD
SRD LRD PARALLEL
R DATA
OUTPUTS
4
D Q D Q QE
SRE LRE
R

5
D Q D Q QF
SRF LRF
R

6
D Q D Q QG
SRG LRG
R

7
D Q D Q QH
SHIFT
11
CLOCK SRH LRH
R

10 SERIAL
RESET 9 DATA
OUTPUT SQH

High–Speed CMOS Logic Data 7 MOTOROLA

DL129 — Rev 6
MC54/74HC595A

TIMING DIAGRAM

SHIFT
CLOCK
SERIAL DATA
INPUT A

RESET

LATCH
CLOCK

OUTPUT
ENABLE

QA

QB

QC

QD

QE

QF

QG

QH

SERIAL DATA
OUTPUT SQH
NOTE: implies that the output is in a high–impedance
state.

MOTOROLA 8 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC595A

OUTLINE DIMENSIONS

J SUFFIX
–A CERAMIC PACKAGE
– CASE 620–10
NOTES:
16 9 ISSUE V 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
–B 2. CONTROLLING DIMENSION: INCH.
– 3. DIMENSION L TO CENTER OF LEAD WHEN
1 8 FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
C L THE LEAD ENTERS THE CERAMIC BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
–T B 0.240 0.295 6.10 7.49
–
SEATING N K C — 0.200 — 5.08
PLANE D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
E M G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
F G J 16 PL K 0.125 0.170 3.18 4.31
D 16 PL 0.25 (0.010) M T B S L 0.300 BSC 7.62 BSC
M 0° 15° 0° 15°
0.25 (0.010) M T A S N 0.020 0.040 0.51 1.01

N SUFFIX
–A PLASTIC PACKAGE NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
– CASE 648–08 Y14.5M, 1982.
ISSUE R 2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
F DIM MIN MAX MIN MAX
C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.070 1.02 1.77
–T PLANE G 0.100 BSC 2.54 BSC
– H 0.050 BSC 1.27 BSC
K M J
H J 0.008 0.015 0.21 0.38
G K 0.110 0.130 2.80 3.30
D 16 PL L 0.295 0.305 7.50 7.74
M 0° 10° 0° 10°
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

D SUFFIX
PLASTIC SOIC PACKAGE
–A CASE 751B–05
– ISSUE J NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B MOLD PROTRUSION.
P 8 PL 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
–
1 8 0.25 (0.010) M B M PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
G MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45° B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
–T
–
SEATING M J J 0.19 0.25 0.008 0.009
PLANE K 0.10 0.25 0.004 0.009
D 16 PL M 0° 7° 0° 7°
0.25 (0.010) M T B S A S P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

High–Speed CMOS Logic Data 9 MOTOROLA

DL129 — Rev 6
MC54/74HC595A

OUTLINE DIMENSIONS

DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF

ÉÉ
ÇÇ
0.10 (0.004) M T U S V S
NOTES:

ÇÇ
ÉÉ
0.15 (0.006) T U S
K 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

ÇÇ
ÉÉ
K1 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

ÇÇ
ÉÉ
16 9 PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
2X L/2 J1 GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
B SECTION N–N FLASH OR PROTRUSION. INTERLEAD FLASH OR
L PROTRUSION SHALL NOT EXCEED
–U– 0.25 (0.010) PER SIDE.
J
PIN 1 5. DIMENSION K DOES NOT INCLUDE DAMBAR
IDENT. PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
1 8 DIMENSION AT MAXIMUM MATERIAL CONDITION.
N 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
0.25 (0.010) 7. DIMENSION A AND B ARE TO BE DETERMINED AT
0.15 (0.006) T U S DATUM PLANE –W–.
A M
–V– MILLIMETERS INCHES
DIM MIN MAX MIN MAX
N A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
F C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
DETAIL E F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C –W– K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
0.10 (0.004) M 0_ 8_ 0_ 8_
–T– SEATING H DETAIL E
PLANE D G

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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*MC54/74HC595A/D*
◊ CODELINE MC54/74HC595A/D
MOTOROLA 10 High–Speed CMOS Logic Data
DL129 — Rev 6