VHDL LAB Manual Vi Semester B.E (E&C) Vishveshwaraiah Technological University (VTU)

VHDL LAB MANUAL
VI SEMESTER B.E (E&C)

(For private circulation only)
VISHVESHWARAIAH TECHNOLOGICAL UNIVERSITY
NAME
REG NO.
BATCH..
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY

MARLUR, TUMKUR-572105
VHDLLabManual
CONTENTS
Sl.No
ExperimentName
PageNo.
1.
ISEQuickStartTutorial
2.
FullAdderDataFlow/Behavioral
13
3.
FullAdderStructural
14
4.
Multiplexer(8:1)
15
5.
Demultiplexer(1:8)
16
6.
EncoderwithoutPriority
17
7.
EncoderwithPriority
18
8.
Decoder(3:8)
19
9.
2BitComparator
20
10.
BinarytoGray
21
11.
GraytoBinary
22
12.
JKFlipFlop
23
13.
TFlipFlop
24
14.
DFlipFlop
25
15.
AsynchronousBinaryUpCounter
26
16.
SynchronousBinaryUpCounter
27
17.
BCDUpCounter
28
18.
BCDDownCounter
29
19.
DCMotorInterface
30
20.
StepperMotorInterface
31
21.
RelayInterface
32
22.
SevenSegmentDisplayInterface
33
23.
Multiplexer(8:1)Structural
34
24.
BinarytoGrayStructural
35
25.
GraytoBinaryStructural
36
26.
Decoder(3:8)Structural
37
27.
JKFlipFlopStructural
38
28.
TFlipFlopStructural
39
29.
DFlipFlopStructural
40
30.
1BitComparatorStructural
41
31.
PinDetails
43
DepartmentofE&C,SSIT,Tumkur.
Page1
VHDLLabManual
Page2
VHDLLabManual
ISEQuickStartTutorial
GettingStarted
StartingtheISESoftware
ForWindowsusers,startISEfromtheStartmenubyselecting:
Start_Programs_XilinxISE7_ProjectNavigator
TheISEProjectNavigatoropens.TheProjectNavigatorletsyoumanagethesourcesand
processesinyourISEproject.AllofthetasksintheQuickStartTutorialaremanagedfromwithin
ProjectNavigator.
StoppingandRestartingaSession
Atanypointduringthistutorialyoucanstopyoursessionandcontinueatalatertime.
Tostopthesession:
Saveallsourcefilesyouhaveopenedinotherapplications.
Exitthesoftware(ISEandotherapplications).
ThecurrentstatusoftheISEprojectismaintainedwhenexitingthesoftware.
Torestartyoursession,starttheISEsoftwareagain.ISEdisplaysthecontentsandstateofyour
projectwiththelastsavedchanges.
AccessingHelp
Atanytimeduringthetutorial,youcanaccessonlinehelpforadditionalinformationabouta
varietyoftopicsandproceduresintheISEsoftwareaswellasrelatedtools.
ToopenHelpyoumaydoeitherofthefollowing:
PressF1toviewHelpforthespecifictoolorfunctionthatyouhaveselectedorhighlighted.
LaunchtheISEHelpContentsfromtheHelpmenu.Itcontainsinformationaboutcreating
andmaintainingyourcompletedesignflowinISE.
CreatingaNewProjectinISE
Inthissection,youwillcreateanewISEproject.Aprojectisacollectionofallfilesnecessaryto
createandtodownloadadesigntoaselectedFPGAorCPLDdevice.
Tocreateanewprojectforthistutorial:
1. SelectFile>NewProject.TheNewProjectWizardappears.
2. First,enteralocation(directorypath)forthenewproject.
3. TypetutorialintheProjectNamefield.WhenyoutypetutorialintheProjectNamefield,a
tutorialsubdirectoryiscreatedautomaticallyinthedirectorypathyouselected.
4. SelectHDLfromtheTopLevelModuleTypelist,indicatingthatthetoplevelfileinyour
projectwillbeHDL,ratherthanSchematicorEDIF.
5. ClickNexttomovetotheprojectpropertiespage.
6. Fillinthepropertiesinthetableasshownbelow
DeviceFamily:CoolRunnerXPLA3CPLDs
Device:xcr3128xl
Package:TQ144
SpeedGrade:7
TopLevelModuleType:HDL
SynthesisTool:XST(VHDL/Verilog)
Simulator:ModelSim
GeneratedSimulationLanguage:VHDLorVerilog,dependingonthelanguageyouwant
tousewhenrunningbehavioralsimulation.
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VHDLLabManual
When the table is complete, your project properties should look like the following:
7.
Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be
created.
Creating an HDL Source

In this section, you will create a top-level HDL file for your design. Determine the language that you wish to use for the tutorial. Then, continue either to the
Creating a VHDL Source section below.
This simple AND Gate design has two inputs: A and B. This design has one output called C
1.
Click New Source in the New Project Wizard to add one new source to your project.
2.
Select VHDL Module as the source type in the New Source dialog box.
3.
Type in the file name andgate.
4.
Verify that the Add to project checkbox is selected.
5.
Click Next.
6.
Define the ports for your VHDL source.

In the Port Name column, type the port names on three separate rows: A, B and C.
In the Direction column, indicate whether each port is an input, output, or inout. For A and B, select in from the list. For C, select out from the
list.
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VHDLLabManual
7.
Click Next in the Define VHDL Source dialog box.
8.
Click Finish in the New Source Information dialog box to complete the new source file template.
9.
Click Next in the New Project Wizard.
10. Click Next again.

11. Click Finish in the New Project Information dialog box.
ISE creates and displays the new project in the Sources in Project window and adds the andgate.vhd file to the project.
12. Double-click on the andgate.vhd file in the Sources in Project window to open the VHDL file in the ISE Text Editor.
The andgate.vhd file contains:
o Header information.
o Library declaration and use statements.
o Entity declaration for the counter and an empty architecture statement.
13. In the header section, fill in the following fields:
Design Name: andgate.vhd
Project Name: andgate
Target Device: xcr3128xl- TQ144
Description: This is the top level HDL file for an up/down counter.
Dependencies: None
Note: It is good design practice to fill in the header section in all source files.
14. Below the end process statement, enter the following line:
C <= A and B;
15. Save the file by selecting File > Save.
Checking the Syntax of the New Counter Module

When the source files are complete, the next step is to check the syntax of the design. Syntax errors and typos can be found using this step.
1.
Select the counter design source in the ISE Sources window to display the related processes in the Processes for Source window.
2.
Click the + next to the Synthesize-XST process to expand the hierarchy.
3.
Double-click the Check Syntax process.
When an ISE process completes, you will see a status indicator next to the process name.
If the process completed successfully, a green check mark appears.
If there were errors and the process failed, a red X appears.
A yellow exclamation point means that the process completed successfully, but some warnings occurred.
An orange question mark means the process is out of date and should be run again.
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VHDLLabManual
4.
Look in the Console tab of the Transcript window and read the output and status messages produced by any process that you run.
Caution! You must correct any errors found in your source files. If you continue without valid
syntax, you will not be able to simulate or synthesize your design.
Simulation
1.
Double click Launch ModelSim Simulator in the Process View window.
2.
3.
Right Click a to open a context menu.

Select Force or Clock to add the signal.
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VHDLLabManual
4.
Define the Clock or Force signal to load appropriate signal
5.
Run the simulation by clicking the Run icon in the Main or Wave window toolbar.
6.
Waveform can be observed in the wave window
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VHDLLabManual
7.
Click the Run -All icon on the Main or Wave window toolbar. The simulation continues running until you execute a break command.
8.
9.
Click the Break icon. The simulation stops running.

To restart the simulation, click the Restart icon to reload the design elements and reset the simulation time to zero. The Restart dialog that appears
gives you options on what to retain during the restart.
Click the Restart button in the Restart dialog.
Assigning Pin Location
1.
Double-click the Assign Package Pins process found in the User Constraints process group. ISE runs the Synthesis and Translate steps
and automatically creates a User Constraints File (UCF). You will be prompted with the following message:
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VHDLLabManual
2.
Click Yes to add the UCF file to your project. The counter.ucf file is added to your project and is visible in the Sources in Project
window. The Xilinx Constraints Editor opens automatically.
3.
Now the Xilinx Pinout and Area Constraints Editor (PACE) opens.
4.
You can see your I/O Pins listed in the Design Object List window. Enter a pin location for each pin in the Loc column as specified below:
A: p90
B: p91
C: p53
5.
Click on the Package View tab at the bottom of the window to see the pins you just added. Put your mouse over grid number to verify the
pin assignment.
5.
Select File _ Save. You are prompted to select the bus delimiter type based on the synthesis tool you are using. Select XST Default
<> and click OK.
6.
Close PACE.
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VHDLLabManual
Creating Configuration Data

The final phase in the software flow is to generate a program file and configure the device.
Generating a Program File

The Program File is a encoded file that is the equivalent of the design in a form that can be downloaded into the CPLD device.
1.
Double Click the Generate Programming File process located near the bottom of the Processes for Source window.
The Program File is created. It is written into a file called andgate.jed. This is the actual configuration data.
Configuring the Device

iMPACT is used to configure your FPGA or CPLD device. This is the last step in the design process. This section provides simple instructions for
configuring a Spartan-3 xc3s200 device connected to your PC.
Note: Your board must be connected to your PC before proceeding. If the device on your board does not match
the device assigned to the project, you will get errors. Please refer to the iMPACT Help for more information. To
access the help, select Help > Help Topics.
To configure the device:
1. Click the + sign to expand the Generate Programming File processes.
2.
Double-click the Configure Device (iMPACT) process. iMPACT opens and the Configure Devices dialog box is displayed.
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VHDLLabManual
3.
In the Configure Devices dialog box, verify that Boundary-Scan Mode is selected and click Next.
4.
Verify that Automatically connect to cable and identify Boundary-Scan chain is selected and click
Finish.
5.
If you get a message saying that there was one device found, click OK to continue.
6.
The iMPACT will now show the detected device, right click the device and select New Configuration File.
7.
The Assign New Configuration File dialog box appears. Assign a configuration file to each device in the JTAG chain. Select the
andgate.jed file and click Open.
8.
Right-click on the counter device image, and select Program... to open the Program Options dialog box.
9.
Click OK to program the device. ISE programs the device and displays Programming Succeeded if the operation was successful.
10. Close iMPACT without saving.
Page11
VHDLLabManual
Page12
VHDLLabManual
1. VHDLCODEFORFULLA
ADDERDATA
AFLOW:
A
0
0
0
0
1
1
1
1
FullAdder
B Ci
C S
0 0 0
0 1 1
1 0 1
1 1 0
0 0 1
0 1 0
1 0 0
1 1 1
Co
0
0
0
1
0
1
1
1
XPRESSIONS:
EX
=ABCi
S=
CO
O=(AB)Ci+AB
libraaryIEEE;
useIEEE.STD_LO
OGIC_1164.A
ALL;
useIEEE.STD_LO
OGIC_ARITH.ALL;
useIEEE.STD_LO
OGIC_UNSIGNED.ALL;
entityfaa1is
Port(a,b,ci:inSTTD_LOGIC;s,,co:outSTD
D_LOGIC);
endfa1;;
hitectureBeh
havioraloffaa1is
arch
begiin
s<=axorrbxorci;
co<=(aaandb)or(baandci)or(ciaanda);
endBehavioral;
VHDLCO
ODEFORFULLADDERBEEHAVIORAL::
libraaryIEEE;
useIEEE.STD_LO
OGIC_1164.A
ALL;
useIEEE.STD_LO
OGIC_ARITH.ALL;
useIEEE.STD_LO
OGIC_UNSIGNED.ALL;
entityfaa1is
Port(a,b,ci:inSTTD_LOGIC;s,,co:outSTD
D_LOGIC);
endfa1;;
arch
hitectureBeh
havioraloffaa1is
begiin
process((a,b,ci)
begiin
s<=axorrbxorci;
co<=(aaandb)or(baandci)or(ciaanda);
endprocess;
endBehavioral;
Departm
mentofE&C,SSIT,Tumku
ur.
Page13
VHDLLabManual
2. VHDLCODEFORFULLADDERSTRUCTURAL:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entityfa1is
Port(a,b,cin:inSTD_LOGIC;
s,cout:outSTD_LOGIC);
endfa1;
architecturestructoffa1is
componentand21
port(a,b:instd_logic;
components,entityandarchitecture
c:outstd_logic);
mustbedeclaredseparately
endcomponent;
componentxor21
port(a,b:instd_logic; components,entityandarchitecture
c:outstd_logic);
endcomponent;
componentor31
port(a,b:instd_logic;
d:outstd_logic);
endcomponent;
signals1,s2,s3:std_logic;
begin
u1:xor21portmap(a,b,s1);
u2:xor21portmap(s1,cin,s);
u3:and21portmap(a,b,s2);
u4:and21portmap(s1,cin,s3);
u6:or31portmap(s2,s3,cout);
endstruct;
Page14
VHDLLabManual
3. VHDLCODEFORMULTIPLEXER(8:1):
INPUTS
d(7) d(6)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
1
0
X
1
X
d(5)
X
X
X
X
X
X
X
X
X
X
0
1
X
X
X
X
d(4)
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
d(3)
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
d(2)
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
d(1)
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
d(0)
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SELECTLINES
s(2) s(1) s(0)
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
O/P
f
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
libraryIEEE;
entitymux1is
Port(d:inSTD_LOGIC_VECTOR(7downto0);
s:inSTD_LOGIC_VECTOR(2downto0);
f:outSTD_LOGIC);
endmux1;
architectureBehavioralofmux1is
begin
f<=d(0)whens="000"else
d(1)whens="001"else
d(2)whens="010"else
d(3)whens="011"else
d(4)whens="100"else
d(5)whens="101"else
d(6)whens="110"else
d(7)whens="111";
endBehavioral;
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VHDLLabManual
4. VHDLCODEFORDemultiplexer(1:8):
SELECTLINES
s(2) s(1) s(0)
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
I/P
f
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OUTPUT
d(7) d(6) d(5) d(4) d(3) d(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
1
X
X
X
X
0
X
X
X
X
X
1
X
X
X
X
0
X
X
X
X
X
1
X
X
X
X
0
X
X
X
X
X
1
X
X
X
X
0
X
X
X
X
X
1
X
X
X
X
0
X
X
X
X
X
1
X
X
X
X
X
d(1)
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
d(0)
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
libraryIEEE;
entitydmuxis
port(f:instd_logic;
s:instd_logic_vector(2downto0);
y:outstd_logic_vector(7downto0));
enddemux;
architecturalbehavioralofdmuxis
begin
y(0)<=fwhens="000"else'0';
endbehavioral;
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VHDLLabManual
5. VHDLCODEFORENCODERWITHOUTPRIORITY(8:3):
SELECTLINES
OUTPUT
s(2) s(1) s(0) y(7) y(6) y(5) y(4) y(3)
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
1
0
0
1
0
0
0
1
1
1
X
X
X
X
X
Y(2)
0
0
1
0
0
0
0
X
y(1)
0
1
0
0
0
0
0
X
y(0)
1
0
0
0
0
0
0
X
libraryIEEE;
entityencois
Port(i:inSTD_LOGIC_VECTOR(7downto0);
y:outSTD_LOGIC_VECTOR(2downto0));
endenco;
architectureBehavioralofencois
begin
withiselect
y<="000"when"00000001",
"001"when"00000010",
"010"when"00000100",
"011"when"00001000",
"100"when"00010000",
"101"when"00100000",
"110"when"01000000",
"111"whenothers;
endBehavioral;
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VHDLLabManual
6. VHDLCODEFORENCODERWITHPRIORITY(8:3):
SELECTLINES
s(2) s(1) s(0)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
y(7)
0
0
0
0
0
0
0
X
y(6)
0
0
0
0
0
0
0
X
y(5)
0
0
0
0
0
0
0
X
OUTPUT
y(4) y(3)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
y(2)
1
1
1
0
1
0
1
X
y(1)
1
1
0
0
1
1
0
X
y(0)
1
0
1
1
0
0
0
X
libraryIEEE;
entityenco1is
Port(i:inSTD_LOGIC_VECTOR(7downto0);
endenco1;
architectureBehavioralofenco1is
begin
withiselect
y<="000"when"00000111",
"001"when"00000110",
"010"when"00000101",
"011"when"00000100",
"100"when"00000011",
"101"when"00000010",
"110"when"00000001",
"111"whenothers;
endBehavioral;
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VHDLLabManual
7. VHDLCODEFOR3:8DECODER:
SELECTLINES
s(2) s(1) s(0)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
X
X
X
y(7)
0
0
0
0
0
0
0
1
0
y(6)
0
0
0
0
0
0
1
0
0
y(5)
0
0
0
0
0
1
0
0
0
OUTPUT
y(4) y(3)
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
y(2)
0
0
1
0
0
0
0
0
0
y(1)
0
1
0
0
0
0
0
0
0
y(0)
1
0
0
0
0
0
0
0
0
libraryIEEE;
entitydec1is
Port(s:inSTD_LOGIC_VECTOR(2downto0);
enddec1;
architectureBehavioralofdec1is
begin
withselselect
y<="00000001"when"000",
"00000010"when"001",
"00000100"when"010",
"00001000"when"011",
"00010000"when"100",
"00100000"when"101",
"01000000"when"110",
"10000000"when"111",
"00000000"whenothers;
endBehavioral;
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VHDLLabManual
8. VHDLCODEFOR2bitcomparator:
A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Y1(A>B)
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
Y2(A=B)
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Y3(A<B)
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
libraryIEEE;
entitycompis
Port(a,b:inSTD_LOGIC_VECTOR(1downto0);
endcomp;
architectureBehavioralofcompis
begin
y<="100"whena>belse
"001"whena<belse
"010"whena=b;
endBehavioral;
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VHDLLabManual
9. VHDLCODEFORBinarytogray(USINGEXORGATES):
CIRCUITDIAGRAM:
EXPRESSIONS:
G(0)=B(0)B(1)
G(1)=B(1)B(2)
G(2)=B(2)B(3)
G(3)=B(3)
Inputs
B(3) B(2) B(1) B(0) G(3)
0
0
0
0 0
0
0
0
1 0
0
0
1
0 0
0
0
1
1 0
0
1
0
0 0
0
1
0
1 0
0
1
1
0 0
0
1
1
1 0
1
0
0
0 1
1
0
0
1 1
1
0
1
0 1
1
0
1
1 1
1
1
0
0 1
1
1
0
1 1
1
1
1
0 1
1
1
1
1 1
Outputs
G(2) G(1)
0
0
0
0
0
1
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
0
0
0
0
G(0)
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
libraryIEEE;
entityBinary_Grayis
port(b:instd_logic_vector(3downto0); BinaryInput
g:outstd_logic_vector(3downto0)); GrayOutput
endbinary_gray;
architecturebehavioralofBinary_grayis
begin
b(3)<=g(3);
b(2)<=g(3)xorg(2);
b(1)<=g(2)xorg(1);
b(0)<=g(1)xorg(0);
endbehavioral;
Page21
VHDLLabManual
10. VHDLCODEFORGRAYTOBINARY:
CIRCUITDIAGRAM:
EXPRESSIONS:
B(0)=G(0)G(1)G(2)G(3)
B(1)=G(1)G(2)G(3)
B(2)=G(2)G(3)
B(1)=G(3)
INPUT
G(3) G(2)
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
G(1)
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
OUTPUT
G(0) B(3) B(2) B(1) B(0)
0
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
1
1
0
0
0
1
1
1
0
1
0
0
0
1
1
0
0
1
1
1
0
1
0
0
1
0
1
1
0
1
1
0
0
1
1
1
0
1
1
1
1
1
0
0
1
1
1
1
libraryIEEE;
entitygb1is
Port(g:inSTD_LOGIC_VECTOR(3downto0);
b:outSTD_LOGIC_VECTOR(3downto0));
endgb1;
architectureBehavioralofgb1is
begin
b(3)<=g(3);
b(2)<=g(3)xorg(2);
b(1)<=g(3)xorg(2)xorg(1);
b(0)<=g(3)xorg(2)xorg(1)xorg(0);
endbehavioral;
Page22
VHDLLabManual
11. VHDLCODEFORJKFLIPFLOPWITHASYNCHRONOUSRESET:(MasterSlaveJKFlipFlop)
Reset
1
0
0
0
0
J
X
0
0
1
1
K Clock Qn+1
X
X
0
0
Qn
1
0
0
1
1
Qn
Qn + 1
1
Qn
1
0
Qn
Status
Reset
NoChange
Reset
Set
Toggle
libraryIEEE;
entityjkff1is
Port(j,k,clk,reset:inSTD_LOGIC;
Q:inoutSTD_LOGIC);
endjkff1;
architectureBehavioralofjkff1is
signaldiv:std_logic_vector(22downto0);
signalclkd:std_logic;
begin
process(clk)
begin
ifrising_edge(clk)then
div<=div+1;
endif;
endprocess;
clkd<=div(22);
process(clkd,reset)
begin
if(reset='1')then
Q<='0';
elsif(clkd'eventandclkd='1')then
if(j='0'andk='0')then
Q<=Q;
elsif(j='0'andk='1')then
Q<='0';
Q<='1';
Q<=notQ;
endif;
endif;
endprocess;
endBehavioral;
Page23
VHDLLabManual
12. VHDLCODEFORTFLIPFLOP:
Clear T Clock Qn+1

1
Qn+ 1
Qn
Qn
Qn
libraryIEEE;
entitytffis
Port(t,clk,rst:inSTD_LOGIC;
q:inoutSTD_LOGIC);
endtff;
architectureBehavioraloftffis
begin
process(clk)
begin
div<=div+1;
endif;
endprocess;
clkd<=div(20);
process(clkd,rst)
begin
if(rst='1')then
q<='0';
elsif(clkd'eventandclkd='1'andt='1')then
q<=notq;
elseq<=q;
endif;
endprocess;
endBehavioral;
Page24
VHDLLabManual
13. VHDLCODEFORDFLIPFLOP:
Clear D Clock Qn+1

1
Qn+ 1
libraryIEEE;
entitydffis
Port(d,res,clk:inSTD_LOGIC;
q:outSTD_LOGIC);
enddff;
architectureBehavioralofdffis
begin
process(clk)
begin
if(res='1')thenq<='0';
elsifclk'eventandclk='1'
thenq<=d;
endif;
endprocess;
endBehavioral;
Page25
VHDLLabManual
14. ASYNCHRON
NOUSBINAR
RYUPCOUNTER:
3bittAsynchrono
ousupcountter
Clo
ock
QC
QB
Q
QA
0
0
0
0
0
0
1
1
0
0
1
1
2
2
0
1
0
0
3
3
0
1
1
1
4
4
1
0
0
0
5
5
1
0
1
1
6
6
1
1
0
0
7
7
1
1
1
1
8
8
0
0
0
0
9
9
0
0
1
1
libraaryIEEE;
useIEEE.STD_LO
OGIC_1164.A
ALL;
useIEEE.STD_LO
OGIC_ARITH.ALL;
useIEEE.STD_LO
OGIC_UNSIGNED.ALL;
entityassybin1is
Port(rs,clk:inSTTD_LOGIC;
q::inoutSTD__LOGIC_VECTTOR(3down
nto0));
endasyb
bin1;
arch
hitectureBeh
havioralofassybin1is
signaldiiv:std_logic__vector(22do
ownto0);
signalteemp:STD_LOGIC_VECTOR
R(3downto0);
begiin
proccess(clk)
begiin
ifrising__edge(clk)theen
div<=div+1;
endif;
endprocess;
clkd<=div(22);
proccess(clkd,rs)
begiin
if(rs='1'))thentemp<=(others=>'0
0');fordowncoun
ntertemp=>""1111";
elsif(clkd
d='1'andclkkd'event)the
en
temp<=ttemp+1;
ntertemp<=temp1;
fordowncoun
q<=tem
mp;
endif;
endprocess;
endBehavioral;
Departm
ur.
Page26
VHDLLabManual
15. SYNCHRONO
OUSBINARY
YUPCOUNTER:
3bittAsynchrono
ousupcountter
Clo
ock
QC
QB
QA
A
0
0
0
0
0
0
1
1
0
0
1
1
2
2
0
1
0
0
3
3
0
1
1
1
4
4
1
0
0
0
5
5
1
0
1
1
6
6
1
1
0
0
7
7
1
1
1
1
8
8
0
0
0
0
9
9
0
0
1
1
libraaryIEEE;
useIEEE.STD_LO
OGIC_1164.A
ALL;
useIEEE.STD_LO
OGIC_ARITH.ALL;
useIEEE.STD_LO
OGIC_UNSIGNED.ALL;
entitysyynbicountis
Port(rs,clk:inSTTD_LOGIC;
q::inoutSTD__LOGIC_VECTTOR(3down
nto0));
endsynbicount;
arch
hitectureBeh
havioralofsyynbicountis
signaldiiv:std_logic__vector(22do
ownto0);
signalteemp:STD_LOGIC_VECTOR
R(3downto0);
begiin
proccess(clk)
begiin
ifrising__edge(clk)theen
div<=div+1;
endif;
endprocess;
clkd<=div(22);
proccess(clkd)
begiin
if(clkd='1'andclkd'eevent)then
if(rs='1'))thentemp<=(others=>'0
0');fordowncountertemp<="111
11"
elsetem
mp<=temp+1
1; fordo
owncounterrtemp<=tem
mp1;
endif;
q<=tem
mp;
endif;
endprocess;
endBehavioral;
Departm
ur.
Page27
VHDLLabManual
16. BCDUPCOUNTER:
Clock QD QC QB QA
0
0
0 0 0
1
0
0 0 1
2
0
0 1 0
3
0
0 1 1
4
0
1 0 0
5
0
1 0 1
6
0
1 1 0
7
0
1 1 1
8
1
0 0 0
9
1
0 0 1
10
0
0 0 0
libraryIEEE;
entitybcdupcountis
Port(clk,rst:inSTD_LOGIC;
q:inoutSTD_LOGIC_VECTOR(3downto0));
endbcdupcount;
architectureBehavioralofbcdupcountis
begin
process(clkd)
begin
div<=div+1;
endif;
endprocess;
clkd<=div(22);
process(clkd,rst)
begin
ifrst='0'orq="1010"then
q<="0000";
elsifclkd'eventandclkd='1'then
q<=q+1;
endif;
endprocess;
q<=q;
endBehavioral;
Page28
VHDLLabManual
17. BCDDOWNCOUNTER:
Clock QD QC QB QA
0
1
0 0 1
1
1
0 0 0
2
0
1 1 1
3
0
1 1 0
4
0
1 0 1
5
0
1 0 0
6
0
0 1 1
7
0
0 1 0
8
0
0 0 1
9
0
0 0 0
libraryIEEE;
entitybcddowncounter1is
Port(clk,rst:inSTD_LOGIC;
q:inoutSTD_LOGIC_VECTOR(3downto0));
endbcddowncounter1;
architectureBehavioralofbcddowncounter1is
begin
process(clkd)
begin
div<=div+1;
endif;
endprocess;
clkd<=div(22);
process(clkd,rst)
begin
ifrst='0'orq="1111"then
q<="1001";
elsifclkd'eventandclkd='1'then
q<=q1;
endif;
endprocess;
q<=q;
endBehavioral;
Page29
VHDLLabManual
18. VHDLCODEFORDCMOTORINTERFACE
Libraryieee;
Useieee.std_logic_1164.all;
Useieee.std_logic_unsigned.all;
Useieee.std_logic_arith.all;
Entitydcmotoris
Port(start,dir,clk:instd_logic;
pwm_out:outstd_logic;
out_dc:outstd_logic_vector(1downto0));
enddcmotor;
architecturedcmotor_aofdcmotoris
signalclk1:std_logic;
begin
process(clk,start)
begin
if(start=0)then
div<=0000000000000000000000000;
elsif(clkeventandclk=1)then
div<=div+1;
endif;
clk1<=div(19);
endprocess;
process(clk1)
begin
if(clk1eventandclk=1)then
ifstart=0then
out_dc<=00;
elsifstart=1anddir=1then
out_dc<=10;
pwm_out<=1;
elsifstart=1anddir=0then
out_dc<=01;
pwm_out<=1;
endif;
endif;
endprocess;
enddcmotor_a;
PINASSIGNMENT
XC3128TQ144
Connector Devicepin
128
P18/6
6
P18/13
14
P18/14
15
P18/11
11
P18/5
5
Property
Clk
Dir
Out_dc(0)
Out_dc(1)
Pwm_out
Start
XC2S100TQ1445
Connector Devicepin
18
P18/6
44
P18/13
54
P18/14
56
P18/11
50
P18/5
43
Property
Clk
Dir
Out_dc(0)
Out_dc(1)
Pwm_out
Start
Page30
VHDLLabManual
19. VHDLCODEFORSTEPPERMOTORINTERFACE
lk<=dic(15);
Libraryieee;
process(lk,rst,clkwise)
begin
if(rst=1)then
state<=s0;
entitystm_stis
elsiflkeventandlk=1then
port(clk:instd_logic;rst:instd_logic;
ifclkwise=0then
out_stm:outstd_logic_vector(3downto0));
casestateis
endstm_st;
whens0=>state<=s1;
architecturestm_st_aofstm_stis
whens1=>state<=s2;
typestate_typeis(s0,s1,s2,s3);
whens2=>state<=s3;
signalstate:state_type;
whens3=>state<=s0;
signaldiv:st_logic_vector(20downto0);
whenothers=>null;
signallk,clkwise,start:std_logic;
endcase
begin
endif;
process(clk,rst)
endif;
begin
endprocess;
if(rst=0)then
withstateselect
div<=(others=>0);
out_stm<=0110whens0,
elsif(clkeventandclk=1)then
1010whens1,1001whens2,
div<=div+1;
endif;
0101whens3;
endprocess;
Endstm_st_a;
PINASSIGNMENT
XC3128TQ144
XC2S100TQ1445
Connector
Devicepin
Property
Connector
Devicepin
Property
128
Clk

18
Clk
P14/1
88
Dir
P18/5
43
Dir
P15/1
132
Out_stm(0)
P18/21
62
Out_stm(0)
P15/2
131
Out_stm(1)
P18/22
65
Out_stm(1)
P15/3
121
Out_stm(2)
P18/19
60
Out_stm(2)
P15/4
120
Out_stm(3)
P18/20
64
Out_stm(3)
125
Rst

86
Rst
Page31
VHDLLabManual
20. VHDLCODEFORSEVENSEGMENTDISPLAYINTERFACE
Libraryieee;
Entitymux_dispis
Port(clk:instd_logic
Rst:instd_logic;
seg:outstd_logic_vector(6downto0)
base:outstd_logic_vector(3downto0));
endmux_disp;
architecturemux_disp_archofmux_dispis
signalcount:std_logic_vector(25downto0);
signalbase_cnt:std_logic_vector(1downto0);
signalseg_cnt:std_logic_vector(3downto0);
begin
process(clk,rst)
begin
ifrst=1then
count<=(others=>0);
elsif
clk=1andclkeventthen
count<=+1;
endif;
endprocess;
base_cnt<=count(12downto11);
seg_cnt<=count(25downto22);
Base<=1110whenbase_cnt=00else
1101whenbase_cnt=01else
1111;
Seg<=0111111whenseg_cnt=0000else
0000110whenseg_cnt=0001else
0000000;
Endmux_disp_arch;
4mhz
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Page32
VHDLLabManual
21. VHDLCODEFORRELAYINTERFACE
Libraryieee;
Entityrelayis
Port(sw:instd_logic;
Rl1,led:outstd_logic);
Endrealy;
Architecturebehavioralofrelayis
Begin
Rl1<=ws;
Led<=sw;
Endbehavioral;
PINASSIGNMENT
XC3128TQ144
Connector
Devicepin
P18/3
41
P18/5
43
P18/21
62
Property
Sw
Rl1
Led
XC2S100TQ1445
Connector
Devicepin
P18/3
1
P18/5
5
P18/21
23
Property
Sw
Rl1
Led
Page33
VHDLLabManual
22. VHDLCODEFORMULTIPLEXER(4:1)(STRUCTURAL):
libraryIEEE;
entitymuxis
Port(i0,i1,i2,i3,s0,s1:inSTD_LOGIC;
y:outSTD_LOGIC);
endmux;
architecturestructofmuxis
componentand1
port(l,m,u:instd_logic;n:outstd_logic);
endcomponent;
componentor1
port(o,p,x,y:instd_logic;q:outstd_logic);
endcomponent;
componentnot1
port(r:instd_logic;s:outstd_logic);
endcomponent;
signals2,s3,s4,s5,s6,s7:std_logic;
begin
u1:and1portmap(i0,s2,s3,s4);
u5:not1portmap(s0,s2);
u6:not1portmap(s1,s3);
u7:or1portmap(s4,s5,s6,s7,y);
endstruct;
Page34
VHDLLabManual
23. VHDLCODEFORBINARY
YTOGRAY(Structural):
libraryIEEEE;
useIEEEE.STD_LOGIC
C_1164.ALL;
useIEEEE.STD_LOGIC
C_ARITH.ALL;;
useIEEEE.STD_LOGIC
C_UNSIGNED.ALL;
entitybgis
Port(b:inSTD_LOGIC__VECTOR(3d
downto0);
g:outSTD__LOGIC_VECTTOR(3down
nto0));
endbg;
architeccturestructo
ofbgis
componentxor1port(a,b:instd_logiic;comp
ponents,enttityandarchitecture
c:outstd_loggic);
musttbedeclared
dseparately
endcompon
nent;
componentand1port(d,e:instd_loggic;comp
ponents,enttityandarchitecture
f:outstd_loggic);
musttbedeclared
dseparately
endcompon
nent;
begin
u1:and1porrtmap(b(3),b
b(3),g(3));
u2:xor1porttmap(b(3),b
b(2),g(2));
b(1),g(1));
b(0),g(0));
uct;
endstru
Departm
ur.
Page35
VHDLLabManual
24. VHDLCODEFORGRAYTTOBINARY(Structural):
libraryIEEE;
useIEEE.STD
D_LOGIC_1164.ALL;
useIEEE.STD
D_LOGIC_AR
RITH.ALL;
useIEEE.STD
D_LOGIC_UN
NSIGNED.ALLL;
entitygbis
CTOR(3downto0);
Portt(g:inSTD__LOGIC_VEC
b:o
outSTD_LOG
GIC_VECTOR
R(3downto0
0));
endgb;
architectureestructofgb
bis
com
mponentxor1
1port(a,b:instd_logic; componeents,entityaandarchitectture
c:ou
utstd_logic);
mustbed
declaredsep
parately
endcomponent;
com
mponentand1port(d,e:in
nstd_logic; componeents,entityaandarchitectture
f:outstd_logic);
mustbed
declaredsep
parately
endcomponent;
com
mponentxor1
12port(g,h,i::instd_logic;;components,entityandarchiteccture
mustbed
k:ou
utstd_logic);;
declaredsep
parately
endcomponent;
com
mponentxor1
13port(l,m,n
n,o:instd_loggic;comp
ponents,entityandarchittecture
p:ou
utstd_logic);;
mustbed
declaredsep
parately
endcomponent;
begin
u1:and1porrtmap(g(3),gg(3),b(3));
u2:xor1porttmap(g(3),g(2),b(2));
u3:xor12po
ortmap(g(3),g(2),g(1),b(1
1));
u4:xor13po
ortmap(g(3),g(2),g(1),g(0
0),b(0));
endstruct;
Departm
ur.
Page36
VHDLLabManual
25. VHDLCODEFORDECODER(Structural):
Y (0)
Y (1 )
Y (2 )
Y (3 )
libraryIEEE;
entitydecis
Port(a,b:inSTD_LOGIC;
enddec;
architectureBehavioralofdecis
componentand1is
port(p,q:instd_logic;r:outstd_logic); mustbedeclaredseparately
endcomponent;
componentnot1is
port(d:instd_logic;e:outstd_logic); mustbedeclaredseparately
endcomponent;
signals1,s2:std_logic;
begin
u1:and1portmap(s1,s2,y(0));
u2:and1portmap(s1,b,y(1));
u3:and1portmap(a,s2,y(2));
u4:and1portmap(a,b,y(3));
u5:not1portmap(a,s1);
u6:not1portmap(b,s2);
endBehavioral;
Page37
VHDLLabManual
26. VHDLCODEFORDFLIPFLOP(Structural):
libraryIEEE;
entitydff1is
Port(d,clk,pr,clr:inSTD_LOGIC;
q,qn:inoutSTD_LOGIC);
enddff1;
architecturestructofdff1is
componentclkdivis
port(clk:instd_logic;clk_d:outstd_logic);mustbedeclaredseparately
endcomponent;
componentnand1is
port(a,b,c:instd_logic;
d:outstd_logic);
endcomponent;
componentnand12is
port(x,y:instd_logic;
z:outstd_logic);
endcomponent;
componentnand13is
port(e:instd_logic;
f:outstd_logic);
endcomponent;
signals1,s2,s3,s4,s5,s6,s7,s8,s9:std_logic;
begin
u10:clkdivportmap(clk,s7);
u1:nand1portmap(d,s7,qn,s1);
u2:nand1portmap(s9,s7,q,s2);
u3:nand1portmap(pr,s1,s4,s3);
u4:nand1portmap(s2,clr,s3,s4);
u5:nand12portmap(s3,s8,s5);
u7:nand12portmap(s5,qn,q);
u8:nand12portmap(s6,q,qn);
u9:nand13portmap(s7,s8);
u11:nand13portmap(d,s9);
endstruct;
Page38
VHDLLabManual
27. VHDLCODEFORJKFLIPFLOP(Structural):
libraryIEEE;
entityjkffis
Port(j,k,clk,pr,clr:inSTD_LOGIC;
endjkff;
architecturestructofjkffis
componentclkdivis
endcomponent;
componentnand1is
d:outstd_logic);
endcomponent;
componentnand12is
z:outstd_logic);
endcomponent;
componentnand13is
port(e:instd_logic;
f:outstd_logic);
endcomponent;
signals1,s2,s3,s4,s5,s6,s7,s8:std_logic;
begin
u1:nand1portmap(j,qn,s7,s1);
u2:nand1portmap(k,s7,q,s2);
endstruct;
Page39
VHDLLabManual
28. VHDLCODEFORTFLIPFLOP(Structural):
libraryIEEE;
entitytff1is
Port(t,clk,pr,clr:inSTD_LOGIC;
endtff1;
architecturestructoftff1is
componentclkdivis
endcomponent;
componentnand1is
d:outstd_logic);
endcomponent;
componentnand12is
z:outstd_logic);
endcomponent;
componentnand13is
port(e:instd_logic;
f:outstd_logic);
endcomponent;
signals1,s2,s3,s4,s5,s6,s7,s8:std_logic;
begin
u1:nand1portmap(t,qn,s7,s1);
u2:nand1portmap(t,s7,q,s2);
endstruct;
Page40
VHDLLabManual
29. 1BITCOMPARATOR(structural):
A B
Y1
(A>B)
Y2
(A=B)
Y3
(A<B)
0 0
0 1
1 0
1 1
libraryIEEE;
entitycompis
Port(a,b:inSTD_LOGIC;y:outSTD_LOGIC_VECTOR(2downto0));
endcomp;
architecturestructofcompis
componentand1
port(l,m:instd_logic;
n:outstd_logic);
endcomponent;
componentxnor1is
port(p,q:instd_logic;
r:outstd_logic);
endcomponent;
componentnotgate1is
port(s:instd_logic;
t:outstd_logic);
endcomponent;
signals1,s2:std_logic;
begin
u1:and1portmap(a,s2,y(0));
u2:and1portmap(s1,b,y(1));
u3:xnor1portmap(a,b,y(2));
u4:notgate1portmap(a,s1);
u5:notgate1portmap(b,s2);
endstruct;
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VHDL LAB Manual Vi Semester B.E (E&amp;C) Vishveshwaraiah Technological University (VTU)

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VHDL LAB Manual Vi Semester B.E (E&amp;C) Vishveshwaraiah Technological University (VTU)

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VHDL LAB MANUAL

VI SEMESTER B.E (E&C)

VISHVESHWARAIAH TECHNOLOGICAL UNIVERSITY

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY

Creating an HDL Source

Type in the file name andgate.

Verify that the Add to project checkbox is selected.

Define the ports for your VHDL source.

Click Next in the Define VHDL Source dialog box.

Click Next in the New Project Wizard.

10. Click Next again.

Checking the Syntax of the New Counter Module

Click the + next to the Synthesize-XST process to expand the hierarchy.

Double-click the Check Syntax process.

Double click Launch ModelSim Simulator in the Process View window.

Right Click a to open a context menu.

Define the Clock or Force signal to load appropriate signal

Waveform can be observed in the wave window

Click the Break icon. The simulation stops running.

Click the Restart button in the Restart dialog.

Assigning Pin Location

Creating Configuration Data

Generating a Program File

Configuring the Device

10. Close iMPACT without saving.

Clear T Clock Qn+1

Clear D Clock Qn+1

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VHDL LAB Manual Vi Semester B.E (E&C) Vishveshwaraiah Technological University (VTU)

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