MIT SoC Design Competition

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ARM AMBA3 AHB-Lite*

Karthik Shivashankar
ARM LTD., Cambridge, UK

About Me

Sr. Engineer @ ARM Research

Based in Cambridge, UK
4+ years at ARM

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Before we start

Have you worked on AMBA before ?

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Why we need Architecture Spec ?

Why we need Architecture Spec ?

Agenda
AMBA Family
Introduction to AHB-Lite
AHB-Lite System
AHB-Lite Signals Master & Slave
AHB-Lite Transactions
How to build a simple AHB-Lite Slave
AHB-Lite Multilayer Design

(2)
(6)
(8)

(15)
(9)
(4)
(3)

Agenda
AMBA Family
Introduction to AHB-Lite
AHB-Lite System
AHB-Lite Signals Master & Slave
AHB-Lite Transactions
How to build a simple AHB-Lite Slave
AHB-Lite Multilayer Design

(2)
(6)
(8)

(15)
(9)
(4)
(3)

AMBA Family
AMBA-1
AMBA-2
AHB
AMBA-3
AHB-Lite
AMBA-4

Acronyms
AMBA Advanced Microcontroller Bus Architectures
AHB Advanced High-Performance Bus

Image Source: Google.com

Agenda
AMBA Family
Introduction to AHB-Lite
AHB-Lite System
AHB-Lite Signals Master & Slave
AHB-Lite Transactions
How to build a simple AHB-Lite Slave
AHB-Lite Multilayer Design

(2)
(6)
(8)

(15)
(9)
(4)
(3)

Master-Slave Architecture

10

AHB-Lite
Master 0

Slave
#1

Slave
#2

Slave
#3

Slave
#4

Single Master
Simple slaves
Easier module design/debug
No arbitration issues
Image Source: Walt Disney

11

AHB-Lite transactions
Master
Register Read
Register Write
Burst Read
Burst Write
Slave
Can make Master wait
Can give error response

Image Source: Walt Disney

12

AHB-Lite Features
Single Clock Edge operation
Uni-directional busses
No tri-state signals
Good for synthesis
Pipelined Operation

Image Source:: Walt Disney

13

An Example AMBA AHB-Lite System

ARM
Processor
(CM0-DS)

MEM
CONTROLLER

AHB-Lite

VGA

14

UART

GPIO

PS2-KB

TIMER

7SEG

An Example AMBA AHB-Lite System

DIGILENT NEXYS3

XILINX SPARTAN6

ARM
Processor
(CM0-DS)

PUSH
Buttons

MEM
CONTROLLER

PSRAM
(16MB)

FLASH
(16 MB)

AHB-Lite

15

VGA

UART

GPIO

PS2-KB

VGA

UART

Switches
& LED

PS2

TIMER

7SEG

7-SEG
Display

An Example AMBA AHB-Lite System

16

ARM R&D Testchip using CM0-DS

17

Agenda
AMBA Family
Introduction to AHB-Lite
AHB-Lite System
AHB-Lite Signals Master & Slave
AHB-Lite Transactions
How to build a simple AHB-Lite Slave
AHB-Lite Multilayer Design

18

(2)
(6)
(8)

(15)
(9)
(4)
(3)

Main Components of AHB Lite System

19

Master
Slaves
Address Decoder
Multiplexor

AHB-Lite Master

Transfer
Response

Read Data

Global Signals

20

AHB-Lite
Master

Address and
Control
Write Data

AHB-Lite Slave

Slave Select

Address and
Control
Write Data
Global Signal

21

AHB-Lite
Slave

Transfer
Response

Read Data

AHB-Lite Master & Slave

Slave Select

Address and Control

Write Data
AHB-Lite
Slave

AHB-Lite
Master

Transfer Response

Read Data

Global Signals

22

Memory Map Decoder & MUX

Address, Control & Wdata
AHB-Lite
Slave

Transfer
Response

ADDR
AHB-Lite
Master

SEL1

Read Data

SEL2

Memory Map
Decoder

AHB-Lite
Slave

SEL3

AHB-Lite
Slave

FF
MUX SEL

Transfer Response, Rdata 1

Transfer Response, Rdata 2

MUX
Transfer Response, Rdata 2

23

Pipelined Transactions (Conceptual Level)

Address phase

Data phase
N cycles

HCLK

Address
&
Control

Data
&
Response

Memory Mapped Transactions: READ & WRITE

24

Agenda
AMBA Family
Introduction to AHB-Lite
AHB-Lite System
AHB-Lite Signals Master & Slave
AHB-Lite Transactions
How to build a simple AHB-Lite Slave
AHB-Lite Multilayer Design

25

(2)
(6)
(8)

(15)
(9)
(4)
(3)

AHB-Lite Master Signals

Transfer
Response

Read Data

Global Signals

26

AHB-Lite
Master

Address and
Control
Write Data

AHB-Lite Slave Signals

Slave Select
Address and
Control
Write Data
Global Signal

27

AHB-Lite
Slave

Transfer
Response

Read Data

AHB-Lite Master & Slave

28

AHB-Lite Master & Slave

29

CM0-DS Doesnt speak the entire language !

CM0-DS do not generate BURST transaction

HBURST[2:0] is always 3b000

CM0-DS never generates locked transactions

HMASTLOCK is always 1b0

All transactions issued are non-sequential transfers

30

HTRANS[1:0] is either 2b00 (IDLE) or 2b10 (Non Sequential)

AHB-Lite Master & Slave

31

HSIZE[1:0]

32

HPROT[3:0] Protection Signal Encoding

Master Generates these signals !

Slaves have the freedom to ignore !!
33

HPROT[3:2] For CM0-DS

34

HTRANS[1:0]
HTRANS

Type

Description

00

IDLE

Master does not wish to perform a transfer

01

BUSY

Bus Master is in the middle of a

burst but cannot immediately continue
with the next transfer

10

NON-SEQ

Indicates the first transfer of a burst or a

single transfer

11

SEQ

The remaining transfers in the burst are

sequential address steps from the previous
transfer. Step size is that of data width of
transfer (which is shown by HSIZE)

CM0-DS Always generates NON-SEQ

Transactions
35

Transactions

36

Control Signals Recap

37

HTRANS[1:0]
IDLE
BUSY
NONSEQ
SEQ

HBURST[2:0]
SINGLE
INCR
WRAP[4|8|16]
INCR[4|8|16]

HSIZE[2:0]
Byte
Halfword
Word
Doubleword
...

HPROT[3:0]
Data/Opcode
Privileged/user
Bufferable
Cacheable

HMASTLOCK
UNLOCKED
LOCKED

Transfer Response Signals

38

AHB-Lite Master & Slave

39

Control Signals to Care about

40

Agenda
AMBA Family
Introduction to AHB-Lite
AHB-Lite System
AHB-Lite Signals Master & Slave
AHB-Lite Transactions
How to build a simple AHB-Lite Slave
AHB-Lite Multilayer Design

41

(2)
(6)
(8)

(15)
(9)
(4)
(3)

Basic transfer - Write

Address phase

Data phase

HCLK

HADDR [31:0]

HWRITE

HWDATA [31:0]

HREADY

42

Data (A)

Basic transfer - Read

Address phase

Data phase

HCLK

HADDR [31:0]

HWRITE

HRDATA [31:0]

HREADY

43

Data (A)

AHB Pipelined Transaction

Address Phase A

Data Phase A
Address Phase B

Data Phase B
Address Phase C Data Phase C
Address Phase .

HCLK
HADDR

HWRITE

HWDATA
HRDATA
HRESP

HREADY

44

OKAY A

OKAY B

Pipelined Operation
Address & Control Wdata
AHB-Lite
Slave

Transfer
Response

ADDR
AHB-Lite
Master

SEL1

Read Data

SEL2

Memory Map
Decoder

AHB-Lite
Slave

SEL3
MUX SEL
AHB-Lite
Slave

FF
MUX SEL

Transfer Response, Rdata 1

Transfer Response, Rdata 2

MUX
Transfer Response, Rdata 2

45

AHB basic signal timing Adding wait states

Address Phase
A

Data Phase A
Address Phase B

HCLK
HADDR

HWRITE

HWDATA

HREADY

HRDATA

HRESP

OKAY A

OKAY A

Master will extend Address Phase B

46

HREADY (Inform all)

AHB-Lite
Slave 1
AHB-Lite
Master

HREADY

AHB-Lite
Slave 2

AHB-Lite
Slave 3

FF
MUX SEL
HREADYOUT 1

HREADYOUT 2

MUX
HREADYOUT 3

47

HRESP Slave Response

HRESP

Event

OKAY

Access completed
normally

ERROR

Slave aborts access,

(2 cycle response)

Bus Master operation

Master has option of

continuing or terminating
a burst containing an
ERROR

It is permissible to continuously drive HRESP

Low in a system which does not wish to
generate any errors.
48

ERROR Response

HCLK
HTRANS

NONSEQ

SEQ

HADDR

A+4

undef

ERROR

ERROR

HREADY

HRESP

If HRESP = ERROR, CM0-DS takes an exception and you should implement

appropriate exception handler to catch the error

49

Agenda
AMBA Family
Introduction to AHB-Lite
AHB-Lite System
AHB-Lite Signals Master & Slave
AHB-Lite Transactions
How to build a simple AHB-Lite Slave
AHB-Lite Multilayer Design

50

(2)
(6)
(8)

(15)
(9)
(4)
(3)

AHB2LED TOP LEVEL

Slave Select

Address and
Control

Transfer
Response
AHB2LED
Read Data

Write Data

Global Signal

51

LED

Sampling Address & Control

Data Phase A
Address Phase
Address
Phase B
A

Data Phase B

HCLK
HADDR

HSEL_A
HWRITE
HTRANS
HREADY

52

A NONSEQ

B NONSEQ

C NONSEQ

Sampling Address & Control

Data Phase A
Address Phase
Address
Phase B
A

Data Phase B

HCLK
HADDR

HSEL_A
HWRITE
HTRANS

A NONSEQ

B NONSEQ

C NONSEQ

HREADY
HWDATA

53

AHB2LED Verilog Module

One way of implementing

Address and Control

Sampling Phase

Data Sampling Phase

54

BUS MATRIX - ISE

55

Agenda
AMBA Family
Introduction to AHB-Lite
AHB-Lite System
AHB-Lite Signals Master & Slave
AHB-Lite Transactions
How to build a simple AHB-Lite Slave
AHB-Lite Advanced

56

Shared Slave
Master 0

Slave
#1

Slave
#2

Master 1

Slave Mux

Slave
#4

Slave
#3

Master 0 can access slaves #1, #2 & #3

Master 1 can access slaves #3 & #4
Contention occurs only if Master 0 & Master 1 try to access slave #3 sametime

Arbitration is at the slave level

57

Multi-layer
ARM

DMA

Slave
Mux

Slave
Mux

Slave
Mux

Slave
Mux

Slave
#1

Slave
#2

Slave
#3

Slave
#4

Generalizing on previous slide

Contention occurs only if Master 0 & Master 1 try to access same slave at
same time

Arbitration is at the slave level

58

Typical Multi-layer example

Master 0

On-chip
RAM

UART

Master 1

Slave
Mux

Slave
Mux

AHB2APB

External
Memory
I/F

Timer

DMA
Slave

GPIO

Master 0 can access private RAM, APB and external interface

Master 1 can access DMA slave, APB and external interface

59

Further Information
ARM IHI 0033 - AMBA 3 AHB-Lite Protocol Specification
http://infocenter.arm.com/

60

THE END

61