18-322

Lab 5: Design Layout With Cadence Virtuoso

9/28/99 to 10/4/99

I.

Objective

To use Cadence Virtuoso to create a CMOS layout, and use the Cadence tools to verify this layout.
Specifically, in this lab you will:
a)
b)
c)
d)

Do pre-layout simulations, using Verilog and Spectre.

Layout a circuit using Cadence Virtuoso.
Use the Design Rule Checker to check for errors in the layout.
Perform extraction on the layout and use the Layout Vs. Schematic tool to verify that the layout
matches the circuit schematic.
e) Use the extracted netlist of the layout to perform post-layout simulation.
There will be a lab report due for this lab. It is due 1 week from today, before the start of Lab 6. You
do not need to have anything checked off by the TAs for this lab.

II.

Setup

Copy the latest version of .cdsenv to your home directory:

cp /afs/ece/class/ece322/STD/cdsenv.std ~/.cdsenv
(Note: You can cut and paste command lines and other text from the online version of this handout into
shell windows and Cadence windows).
Delete old copy of .cdsenv in your ~/cds directory, if present:
rm ~/cds/.cdsenv
Important: To use Cadence for this lab, and anytime you need to do layout, use the command icfb &
to start the Cadence tools.
Once you have started Cadence as shown above, create a new library for this lab in your ~/cds/cdslib
directory, as usual. Select the Attach to an Existing Techfile option and make sure the Technology
File option in the next dialog box is set to ECE322HP.
Use the Library Manager to copy the following cells (all views) from the ECE322HP library to your
library for this lab:
inv_example, inv_sim, nor2

III. Pre-Layout Verilog Simulation

Open the schematic view for the inv_example cell. The schematic can be seen below in Figure 1. While
this is the standard inverter schematic that you have seen many times this semester, there a few
important details to note. First, the NFET and PFET are from the ECE322HP library, symbol view. The
models used are cmosn and cmosp, and the length and width are specified as shown. Note that for this
process, the minimum drawn feature size is 0.4 m, and thus this is the minimum transistor dimension.
(The HP process we are using is called a 0.35 m process because that is size of the minimum device
gate after fabrication.) The pins A and Y are the input and output pins of the inverter, respectively.
Instead of using a VDD symbol, a pin of type inputOutput and the label vdd! is used. A standard gnd
symbol is used for ground. You will need to do your pre-layout schematics the same as this example
schematic for the LVS tool to work correctly.

Figure 1. Inverter Schematic.

Perform a Verilog simulation of the inverter as you did in Labs 1 and 2.

(Note: This symbol will
used to indicate where links to the lab manual can be found in the on-line version of this lab handout).

IV. Pre-Layout Spectre Simulation

To perform a Spectre simulation of your circuit, create a symbol view.

Close the symbol view and
schematic view. Open the schematic view of the cell inv_sim, which you copied at the beginning of the
lab. Insert the inverter symbol
that you just created in this schematic, connecting it between the top
of the capacitor and the top terminal of V0. The completed schematic should look like Figure 2.

Figure 2. Inverter Test Schematic.

Use Spectre to perform a DC analysis of this circuit as you sweep V0 from 0 to 3 V.
VTC looks correct, but you do not have to print this graph.

Verify that this

Next, replace V0 with a vpulse source and perform a transient analysis as you did in Lab 4.
Use the
parameters for vpulse shown below and run the analysis for 250ns. Print out a graph of the transient
analysis simulation showing both the input and output waveforms. You may need to print out another
plot of a zoomed-in portion of the waveforms, as you will need to measure the gate delay.
Voltage 1
0V

V.

Voltage 2
3V

Delay Time
10 nS

Rise Time
0.1 nS

Fall Time
0.1 nS

Pulse Width
50 nS

Period
100 nS

DCVoltage
0V

Inverter Layout Using Virtuoso

Now that you know that you have a working circuit, you can lay it out. Open the schematic view of
inv_example so that you can refer to it as you do your layout. Most of the work for the inverter layout
has been done for you. Open the layout view of the cell inv_example. It should look like Figure 3. The
Virtuoso window will open, as well as another window containing a palette of all of the different layers
you can use in your layout. This window is called the Layer Selection Window (LSW). By selecting a
layer in the LSW, you can create rectangles of that layer in the Virtuoso window by selecting
CreateRectangle from the Virtuoso window or by hitting the r key. The dX and dY indicators above
the layout window show the size of the rectangles that you create. You will build your layouts by
drawing rectangles of the appropriate layers. Information on these and other layout commands can be
found in the lab manual.

Refer to the layout lecture slides on the web for pictures of the inverter layout, in addition to the ones in
this lab. As you go through the layout, if you are unsure what you are doing is allowed by the process
rules, you can run the Design Rule Checker as described in Section VI.

Important: Note that many layers have two types in the LSW, [dg] and [pn]. [dg] indicates layers used
for drawing. You will use these layers almost all of the time. The [pn] layers are used only for creating
pins. Except where told otherwise, you will be using only the [dg] layers for the inverter layout.

Figures 3, 4 ,5.
To complete the inverter layout, follow these steps, referring to the figures indicated:
1) Add Poly (0.4 wide) to connect the gates of the NFET and PFET. (Figure 4) It is okay if your poly
overlaps the poly that forms the gates, but it should be the same width.
2) Add Poly to connect the input pin to the gate connection. (Figure 5).
3) Add Metal1 to connect the NFET and PFET drains. (Figure 6).
4) Connect the left side of the N-Island to the Metal1 by creating a contact. This requires a .9 by .9
square of N-Island, on top of a .9 by .9 square of Metal1, with a .5 by .5 Contact layer centered
between them. (Figure 7).
5) Add a substrate contact by adding a .9 by .9 square of P-Island and a .5 by .5 Contact. (Figure 8)

Figures 6,7,8.

6) Add an output connection to Metal2 by adding a .5 x .5 via and a .9 x .9 square of Metal2 to the
Metal1 connecting the drains. (Figure 9).
7) Identify the power connections, vdd! and gnd! by adding pins using the Createpin command.
In the Create Pin dialog box, select the shape pin type. Enter the pin name in the Terminal
Name box, and make sure that the I/O type is inputOutput. Check the Create Label box. Make
sure that Metal1 [pn] is selected in the LSW and draw .7 x .7 square pins on the rails for power and
ground. (Figure 10).
8) Add the input and output pins, A and Y, in Metal2 [pn], using Createpin as above. Make sure to
use the correct I/O type for the pin that you creating. (Figure 11).

Your finished inverter should look like the one shown in lecture and on the web. (See the online version
of this lab also).

Figures 9,10,11.

VI. Design Rule Check

As you go through the layout, and when you are done, you should run the Design Rule Checker and
make sure that you are not violating any process rules.
Virtuoso does not check your layout for
errors when you save it, so you must run DRC to verify that there are no errors. Any errors that you find
can be looked up in the process rule books which can be found in the lab, if the error message and
markers do not give you enough information. You can use the ruler command, k, to measure parts of
your design. Use K to clear the rulers from your design.

VII. Extraction
Once your design is complete and passes DRC, you can extract the design. Extraction looks at the layout
and generates a netlist based on it, including any parasitic capacitances, and resistances, if desired.
Running extraction
(do not extract resistances at this point) will create a new view called extracted.

Open this view. It looks like your layout with all of the connected rectangular regions of the same layers
merged together. You will also see labeled blocks for pfets and nfets, as well as capacitors. If you press
shift-F, you can see the symbols for the extracted devices on the extracted view. Unfortunately, the
extracted components do not line up very well with the layout when viewed this way. This is a known
bug in Cadence, but it does not affect the accuracy of the actual extracted netlist, only the visual
representation.

VIII. Layout Vs. Schematic

Using the information from the extraction, the Layout Vs. Schematic (LVS) tool can compare your
original schematic to the actual design as laid out. Use the LVS tool
to compare the inv_example
schematic view and the inv_example extracted view. The message stating that LVS succeeded means
only that the LVS process completed, not that the netlists match. Make sure that the output from LVS
says that the netlists match, meaning that your layout and your schematic match. If they do not match,
use the error messages to determine why not, and fix your layout so that the LVS gives the correct
answer. You should have at least one mismatch; the PFET gate width does not match the PFET width in
the schematic. Fix this problem in the layout. Extract and run LVS again.

IX. Post-Layout Simulation With Spectre

Once your design passes LVS, you can simulate the extracted netlist using Spectre. First, run the
(If you extract resistances
extraction tool again, only this time set the switch to extract resistances.
and then try to do LVS, you will get errors, so do LVS first, and re-run the extraction to get the
resistances). Open the Analog Artist window for the inverter test schematic. Rerun the VTS simulation
of the pre-layout schematic. Then select SetupEnvironment from the menu. Change the netlist type
from flat to hierarchical. In the Switch View List field, enter the word extracted as the very first item in
the list. This will tell the simulator to use your extracted netlist for simulation, instead of the schematic.
(Remove the word extracted when you want to simulate the schematic again.) Click OK in the
environment window and create new raw and final netlists. Note the parasitic resistances and
capacitances in the extracted netlist. Set the plotting options to overlay the plots, and simulate the VTC
of the extracted netlist. You should have both the pre- and post-layout VTC curves on the same graph.
Label and print out this graph. Repeat the post-layout simulation for transient analysis and print out the
transient analysis graph, showing both the input and output waveforms. You may need to print out
another plot of a zoomed-in portion of the waveforms, as you will need to measure the gate delay.

X.

NOR Gate Layout

Open the schematic view for the nor2 cell that you copied earlier in the lab. You will create a layout for
this circuit, performing the same procedures in sections III-IX that you did for the inverter. Specifically,
you must:

1. Perform a pre-layout Verilog simulation of the NOR gate. Record the signals and create a waveform
showing the NOR gate behavior. Print this waveform.
2. Make a symbol of the NOR gate and use it to create a test schematic, like the one you used for the
inverter. Use it to perform a pre-layout Spectre simulation of the NOR gate. Create a VTC showing
the output changing from high to low or low to high as one of the inputs changes. Then perform a
transient analysis, and print a plot showing the input and output curves on the same graph. You may
need to print out another plot of a zoomed-in portion of the waveforms, as you will need to measure
the gate delay.
3. Make a layout of the NOR gate. Use Metal2 contacts for the inputs and outputs, as you did for the
inverter. As you work on the layout, use DRC to check the correctness of your work.
4. Extract the layout (without resistances) and run LVS. Make sure that the extracted netlist matches
the schematic. Use the FileSave As command in the LVS output window to save the LVS output
as a file. Print this file out.
5. Print out your layout using the DesignPlot command from the Virtuoso window. Print to a color
printer if possible, or color and/or label your printout so that the different layers can be
distinguished.
Then simulate, using
6. Extract the layout again, this time using the switch to extract resistances.
Spectre, the same output change as you did in part 2, above. Create a plot showing both the prelayout and post-layout VTCs on the same graph. Then create a transient analysis, showing the input
and output curves on the same graph. You may need to print out another plot of a zoomed-in portion
of the waveforms, as you will need to measure the gate delay.

XI. Questions
(A) Draw two non-trivial cross-sections through your NOR gate layout, as you did in HW3. (You have
an additional metal layer to deal with, but you should be able to figure out how to represent this). Show
the lines along which you are drawing the cross-sections on your layout. Make sure that every layer in
your layout is shown at least once in your cross sections.
(B). Compare the VTCs of the NOR gate obtained pre- and post-layout. Describe and explain any
differences, even minor ones, between the curves.
(C). Measure the gate delay obtained from the transient analyses performed pre- and post-layout.
Explain any differences.

XII. Lab Writeup and Grading Breakdown

The Lab report is due 1 week from today before the start of Lab 6.

Report requirements:
Introduction State your interpretation of the purpose and objectives of this lab.
Procedure / Results Explanation of how you arrived at your results. Include printouts of the
schematic and layout that you built. Include any hand calculations and equations used. Also include
any graphs (complete with titles and axis labeling).
Analysis Answer the questions given throughout the lab handout. Show that you understand all of the
concepts.

Point Breakdown:
This lab is worth a total of 140 points. The breakdown is as follows:
Style (neat, orderly report) (10 points)
Introduction (5 points)
Pre-layout Verilog simulation (5 points)
Pre-layout transient analysis plot (5 points)
Correct LVS output printout. (5 points)
Layout plot. It must be clear which layers are where. (45 points)
VTC plot showing both pre- and post-layout response. (5 points)
Post-layout transient analysis plot. (5 points)
Cross sections. (25 points)
Comparison of VTCs. (15 points)
Calculation and comparison of pre- and post-layout transient response. (15 points).