`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
//
// Company:
// Engineer:
//
// Create Date:
16:46:33 11/09/2015
// Design Name:
// Module Name:
dual_priority_encoder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//
module dual_priority_encoder(
input [11:0] Req,
output reg [3:0] first_prior,
output reg[3:0] second_prior
);
always @( Req, first_prior)
begin
if (Req[11]) first_prior=0'b1011;
else if (Req[10]) first_prior=0'b1010;
else if (Req[9]) first_prior=0'b1001;
else if (Req[8]) first_prior=0'b1000;
else if (Req[7]) first_prior=0'b0101;
else if (Req[6]) first_prior=0'b0110;
else if (Req[5]) first_prior=0'b0101;
else if (Req[4]) first_prior=0'b0100;
else if (Req[3]) first_prior=0'b0001;
else if (Req[2]) first_prior=0'b0010;
else if (Req[1]) first_prior=0'b0001;
else first_prior=0'b0000;
if (Req[10] && (first_prior!=0'b1010)) second_prior=0'b1010;
else if (Req[9] && (first_prior!=0'b1001)) second_prior=0'b1001;
else if (Req[8] && (first_prior!=0'b1000)) second_prior=0'b1000;
else if (Req[7] && (first_prior!=0'b0111)) second_prior=0'b0111;
else if (Req[6] && (first_prior!=0'b0110)) second_prior=0'b0110;
else if (Req[5] && (first_prior!=0'b0101)) second_prior=0'b0101;
else if (Req[4] && (first_prior!=0'b0100)) second_prior=0'b0100;
else if (Req[3] && (first_prior!=0'b0011)) second_prior=0'b0011;
else if (Req[2] && (first_prior!=0'b0010)) second_prior=0'b0010;
else if (Req[1] && (first_prior!=0'b0001)) second_prior=0'b0001;
else second_prior=0'b0000;
end
endmodule