a PRINCIPLES OF CMOS VLSI li DESIGN A Systems Perspec} Neil H. E. Weste ‘ATRT Bell LaboratoriesPRINCIPLES OF IL | CMOS VLSI DESIGN IL | L lal i ee oe OO TlMG. Vatley, Sponsoring Editor s Hugh Ceawiord, Manufacturing Supervisor Maty Critendan, Project Supervisor FRichatd Hannus, Cover Designer i ‘oureen Langer. Text Designee L lydia P. Siegel, Production Editor “This book is inthe Addison Wesley VEST Systems Seis To Avril, Melissa, and Tamara Typ Conway and Ghats Seitz, Consling Etre and Deidre, Michelle, and Kylie ‘trary of Congress Cataloging in Pblieaton Dat Wat, Nei cli of CMOS VES desis ‘logan: p Include inet Tatra Sects Very ae scale ntation i _—batietind consucion. "2 Meloxdesemionducton, Gompleoenny. L Exhraphle, Kame, HT SP'Tide Panels of CMOS. VIS. doi ‘So o-2o1-ogaat-s Reprned with comets Jae, 1988 Copyrieh © 1085 by ATAT Bell abostaies, ncrporated, Sou Ean Sabrepan| [ligt ese No pat ofthis publication may be coprocessor Ce ee Pnamtd to any form ot By any ens, ere. aaa eascopying ecarding or she, without the par wren ae Pe eblsor Fated in he United States of Ae Filabe smeliancusl in Cams‘The VLSI Systems Series Lynn Conway Consulting Charles Seitz VLSI Signal Processing ‘A Bit-Serial Approach ‘The Design and Analysis of VLSI Circuits ‘The VLSI Designer's Library Structured VLSI Design Principles of CMOS VLSI Design: ‘A Systems Perspective Editors Peter Denver and David Renshaw. 1985 Lance A. Glasser and Daniel W. Dobberpubl 1985 John Newkirk and Robert Mathews, 1983, Ccharles Seitz, 1985 Neil Weste and Kamran Eshroghian, 1985pene perros FOREWORD ‘The subject of VLSI systems spans a broad range of disciplines, Including semiconductor devices and processing, integrated electronic, ‘Crculls, digital logic. design disciplines and tools fr resting complex. Systems, and the architecture, algorithms, and applications of complete VLSI systems. The Addison-Wesley VLSI Systems Series is being organized as a set of textbooks and research references that present the best current work across this exciting and diverse field, with teach book providing for its subject a perspective tht tes it to related disciplines. Principles of CMOS VLSI Design: A Systems Perspective by Neil ‘Weste and Kamran Eshraghian provides both students and practicing System designers with a solid introduction to custom VLSI design in the complementary MOS (CMOS) technologies. The past seve:al years bave seen a rapid shift inthe technology of choice fo high- Complexity digital microelectronics from nMOS to CMOS. This shift fas occurred because CMOS offers high performance at low power, fand scales extremely well to small feature size. In spite of its ad~ vantages, and is extensive use in semi-custom gate-rrays and custom Commodity parts, CMOS has yet to be exploited to is full potential by the VLSI system design community. CMOS design and layout presents soveral intimidating completes that Weste and Eshraghian fave effectively put to ret by the way in which they have adopted hierarchical, stuctured design methods and layout abstrection to ‘CMOS technology. ‘The presentation ofa coherent design style together vith manyx FOREWORD practical design examples allows this book to be used either as @ | text or as a reference. Those readers already skilled in VLSI design re bs median wl fd that tok ed amos tnt PREFACE Int aM med bout CMOS cngn an many stig pnts TEGuGS USF Sem design, The tok cies he sins re Gitrencs unum be HOS poe vata enlace aes ge Te symbol yout spac devoped inthe aoe ee dort sep bck fon he real Souls wh ean We lew tat dostgnos. serchary. and Sn eer al nis oktober tornce Se ny explore th ones Of MOS VES ei, Lynn Conway’ ‘Ann Atbor, Michigan Chuck Seitz Pasadena, California Recently there has been an interest in expanding the set of people engaged in the design and specification of integrated circuits. This hhas occurred in two main thrusts. The text Introduction to VLSI Systems by Mead end Conway advocated what is now commonly called “structured hierarchical design,” accompanied by a reduced fad simplified geometric and electrical rule set. That text was based tipon a nMOS depletion load technology. Design responsibility txtonded down to layout details. An alternative movement. largely Supported by industry (as opposed to academia), has placed custom {)1C. design capability atthe logic level atthe disposal of many HE, system designers. This has largely been in the form of CMOS gate EE arrays and, more recently, CMOS standard cells. ‘This text has been written to assist those who wish to go beyond the standard cell and gate array approaches and realize fully custom ‘Sesigns that Completely utilize the potential ofthe silicon surface, "The material in this book is divided into several parts. The fist past deals with CMOS circuit design and CMOS processing tech- ology. The second part deals with design issues and sub-system design, The last partis devoted toa rich set of examples of custom- designed CMOS circuits from which the reader may draw on the experience of other VLSI system designers, “A centalized theme in the book is the adoption of a symbolic layout approach to CMOS design. Most layout examples are given in this form with some mask level layouts for atypical bulk CMOSig warnce — psec Coed process, However, the symbolic designs are provided where necassary to provide layouts with some lifetime. "This text originated with a course that Weste taught atthe Uni- ‘versity of North Carolina (Chapel Hill) and Duke University im the {pring of 1982. An expanded course was taught by Eshraghian at Duke in the spring of 1983 and at the University of Adelaide in 1983/84. Dr. Kishor Trivedi taught the Duke course in the spring of 1964. A similar course was also taught at ATAT Bell Labs (Holmdel) in 1983, "The authors would like to acknowledge the support and help of many people during the preparation of the text. Bryan Ackland provided outstanding contributions to the outcome of the text, in- Ehuding key rewrites to Chapters 2 and 4. Kishor Trivedi was kind fenough to debug a draft form of the text in his CMOS class. Steven HF. Law, Gershon Kedem, Dave Ditzel, Don MacLennan, Maleolin Haskard, Alan Mariage, Marcus Patridge, Jim Cherry. Richard Lyon, ‘Mike Maul, Randy Katz, Jonathan Allan, and colleagues inthe Com- puter Systems Research Laboratory of AT&T Bell Labs provided much needed comments and criticisms of the fist draft. Jay Borris provided a great resource in the assembly of the fist drat. The Eupport of RL. Andersson, S. C. Knauer, j. H. O'Neill, A. Huang, Joba W. Poulton, Henry Fuchs, Alen Paeth, R. H. Krambeck, and N-S. Vesanthavada is appreciated for their contributions to Chapter 9, Alex Dickinson, Charles Poirier, and Martin Levy provided support inthe later stages of the book. Furthermore the authors would like to acknowledge AT&T Bell Labs menagement, especially Bll Ninke, and staff for providing the ‘experience, the atmosphere, and the resources without which this book would riever have been completed. Additionally, The Mi- crooloctronics Cenze of North Carolina and the associated universities, particularly Duke and UNC (Chapel Hill), provided the ecademic fnvironment where work on this text was started. The University of Adelaide and Symbolics Inc. provided ongoing support for the ‘work on the book. Cambridge, Massachusetts NW. ‘Adelaide, South Australia KE ABOUT THE AUTHORS Neil Weste is the Director of VLSI Systems at Symbolies Inc. in addition to holding a postion as an Adjunct Professor in Computer Seionce at Duke University. Prior to joining Symbolics Inc. Weste Spent six years at AT&T Bell Labs in Holmdel, New Jersey. He Wworked one year at the Microelectronics Center of North Caroline vwith teaching duties at Duke University and the University of North Carolina (Chapel Hill, Weste received his BS. B.E., and Ph.D. from the University of Adelaide, South Australia ‘Kamran Eshroghian isa senior lecturer in Electrical Engineering ot the University of Adelaide, South Australia. In addition to CMOS ‘VLSI Design, his research interests include Signal Processing. Esh- Tghian received his B.S., BE, and Ph.D. from the University of ‘Adelaide, South Australia, Eshraghian spent one year atthe Micro ‘lectzonics Center of North Carolina and Duke University. Prior to teaching, Eshraghian was with Philips Lid. as an IC designe.CONTENTS oar 1 INTRODUCTION TO CMOS TECHNOLOGY INTRODUCTION TO CMOS CIRCUITS 1.4 Introduction 1.2 MOS transistors 1.3 MOS transistor switches 1a CMOS logic La The inverter 14.2 Combinational logic 143. The NAND gate 1a The NOR 143 Compound gates 148 Multiplexers 147 Memory 1.5. Allernate circult representations 1.5.1 Behavioral representation 1152 Structural representation 15. _ Physical represent 1.6 CMOS-nMOS comparison 17 Summary 18 Exercises2 ‘CONTENTS: 2 MOS TRANSISTOR THEORY 22 23 Invoduetion 21.1 nMOS enhancement transistor 21.2 nMOS transistor 2.13 Threshold voltage 2.14 Threshold voltage adjustment 21.3 Body effect MOS device design equations 22:1 Vel characteristics ‘The complementary CMOS invert characteristics 2.3.1 Influence of 4/8, ratio on transfer characteristic 232 Noise margin Alternate CMOS inverters ‘Transmission gate—DC cha Latch-up Exercises Dc ‘CMOS PROCESSING TECHNOLOGY a1 32 33 34 Silicon semiconductor technology: an overview 3.4.1 Wafer processing 34.2 Oxidation 3.1.3 Selective diffusion 3.1.4 The silicon gate process CMOS technologies 3.21 The p-well process 3.22 The n-well process 3.2.3 The twin tub process 3.2 Silicon on insulator 32.5 CMOS process enhancements Layout design rules 331 Layer representations 33.2 Lambda based p-well rules 33.3 Lambda based SOI rules 23.4 Double metal design rules 33.5. Design rules—summary Process parameterization 341 Abstract layers 34.2 Spacing rules 34.3 Construction rules 3 2 n a a 8 38 39 2 2 Summary Exercises CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION 4a 42 43 44 45 46 48 49 4.0 an 412 5 Introduction Resistance estimation 42.1 Resistance of non-rectangular regions Capacitance estimation 43:1 MOS capacitor characteristics 43.2 MOS device capacitances 43.3 Diffusion capacitance 43.4 Routing capacttance 335 Distributed RC effects $36 Capacitance design guide 33.7 Wire length design guide Switching characteristics S41 Fall time determination 442. Rise time 442 Delay time 25 CMOS gate transistor sizing 45.1 Similar stage loads 45.2 Switching performance of the Pseudo ‘AMOS inverter 45.3 Cascaded stage loads Determination of conductor size Power consumption 47.1 Static dissipation 4.7.2 Dynamic dissipation (Charge sharing Scaling of MOS transistor dimensions 4.91 Scaling principles 4.9.2 Interconnect layer scaling Yield Summary Exercises CMOS CIRCUIT AND LOGIC DESIGN 8. 52 Introduction CMOS logic structures 5.2.1 CMOS complementary logic 19 v0 120 2 m2 wa 15 129 at 131 nb 1a? 0 M1 ut rr 15 7 19 150 150 154 136 157 157 159 160 160 160 CONTENTS xviiwill CONTENTS: 33 55 52.2 Peeudo-nMOS logic 5.2.3 Dynamic CMOS logic 5.2.4 Clocked CMOS logic (C*MOS) 523 CMOS domino logic 5.2.6 Cascade voltage switch logic (CVSL) 52.7 Madilied domino logic 5.2.8 Pass transistor logic Electrical and physical design of logic gates 53.1 The invertor 5.3.2 NAND and NOR gates 5.3.3 Series and parallel transistor connection 5.34 Body effect 5.33 Souree-drain capecitance 5.2.6 Charge redistribution (ch: 5.3.7 Logie style comparison 5.3.8 Physical layout of logic gates 5.3.9 CMOS standard coll design 5.3.10 General logic gate layout guidelines 5.2.11, Gate optimization 53.12 Transmission gate layout considerations 5.3.13 2-input multiplexer Clocking strategies Sat Pseudo 2-phase clocking 542 Pseudo 2-phase memory structures 5.4.3 Preudo 2-phase logic structures 544 2phase clocking 548 2phase memory structures 54.6 2-phase logic structures 54.7 4-phase clocking 5.48 4-phase memory structures 54.9 4-phase logic structures 54.10 Pseudo 4-phace clocking 54.11 Recommended approaches Input-output (LO) structures 551 Overall organization 55.2 Vop and Ves pods 55.3 Output pads 55.4 Input pads 55.5 Tristate pads 55.6 Bidirectional pads Summary Exercises re sharing) 162 163, 168, 168 159 1 m 175 vs 179 20 184 185 188, 88 189 193 195 196 201 203 203 203 208, an au 22 ns zat m2 23 2a 24 224 225 225 227 229 230 230 230 PART. SYSTEMS DESIGN AND DESIGN METHODS 6 STRUCTURED DESIGN AND TESTING 6.1 Introduction 6.2 Design styles 62.1 Introduction 6.2.2 Structured design strategies 62.3 Hand-crafted mask layout 6.24 Gate aray design 6.2.5 Standard coll design 6.2.6 Symbolic layout methods 6.3 Automated synthesis 63.1. Procedural module definition 6.3.2 Silicon compilers 6.4 The custom design tool box 64.1 Introduction 64.2 Chreuit level simulation 643 Timing simulation 6.4.4 Logic level simulation 64.5 Switch level simulation 64.8 Timing verifies 64.7 Schematic editors 64.8 Netlist comparison 64.9 Layout editors 64.10 Design rule checkers 8.4.12. Cireult extractors 65 Testing 65.1 Intoduction 65.2 Fault models 65.3 Design for testability 65.4 Ad hoc testing 6.5.5 Structured design for testability 6.5.6 Selftest and builtin test 6.5.7 Layout for improved testability 6.5.8 Summery—testing Summary Exercises 6 6 ‘SYMBOLIC LAYOUT SYSTEMS 7. Introduction 72 Coarse grid symbolic layout 233 25 236 236 236 238 aa aan a7 249 237 287 238 258 259 259 259 260 262 263 268 266 268 268 269 269 an a are CONTENTS aeGate-matrix layout Sticks layout Virtual grid symbolic layout 75.1 Language 752 Devices 733 Contacts 734 Wires 733° Pins 736 Instances 7.57 _ Representations 7.6 Symbolic design tools 7.6.1 Overall organization 762 762 Software organization 7.8.4 Chip design process 763 Cell design process 7.66 Interactive graphics editor 7.67 Circuit interpreter 7.68 Virtual grid compaction 7.69. Graph-based compaction 7.6.10 Mask generation 7.6.11 Call verification 7.6.12 Module assembly 7.7 Future directions 77.1 Flexicells 77.2. Expert systems 7.8 Summary 79 Exercises 8 ‘CMOS SUBSYSTEM DESIGN 8.1 Introduction 82 Adders and related functions 8.2.1 Combinational adder 82.2 Dynamic combinational adder 82.3 Transmission gate adder 824 Cary lookaboad adders 82.5 Manchester carry adder 82.6 Binary lookahead carry adder 82.7 Cary select adder 82.8 Parity generators 82.9 Comparators 83 Binary counters 23.1 Asynchronous counters 83.2 Synchronous counters 309 0 310 an au 317 320 322 225 at a2 33 335 335, 335 84 Multipliers 84.1 Serial multiplier 84.2 Serial'parallel multipliers 442 Parallel multiplier 844 Other multiplier structures 85 Random access memory 85.1. Static RAM calls 85.2 CMOS static RAM cell design 85.3 Dynamic RAM cells, 54 ROM cells 83.5 Row decoders 85.8 Column decodors 85.7 Readiwrite circuitry 8.5.8 Last in, st out stack 8.6 Data paths 86.1 Registers 86.2 Arithmetic logic units 8.6.3 Barrel shifters 8.7 Programmable logic arrays 87.1 Introduction 87.2. Electrical and physical design of CMOS PLAS 87.9 Pseudo-mMOS NOR gate 874 Dynamic CMOS~2-phase clocking 875 Dynamic CMOS—+-phase 876 Detailed PLA layout 8.7.7 PLA else clause implementation 87.8 PLA design points 7.9 Programmable path logic (PPLs) 8.8 Exercises var D (CMOS SYSTEM CASE STUDIES 9 SYSTEM CASE STUDIES 9.1 Introduction 9.2 Dynamic time warp processor 9.2.1 Introduction 92.2 The problem 9.2.3 The algorithm 924 A functional overview 92.5 Detailed functional specification 92.6 Structural floor plan a9 340 340 a8 381 383 am 364 384 305 386 388 303 ‘300 ‘CONTENTS:as 94 28 97 INDEX 9.2.7 Physical design 92.8 Febrication Real time video moment generator chip 9.3.1 Introduction 9.3.2 Review: video formatting 93.3 Chip architecture 934 Floor planning 935 Component cell examples 9.38 Chip assembly 9.3.7 Optimization 9.3.8 Design testing 9.3.9 Physical chip testing 93.10 Conclusions Self routing switching network 94.1 Introduction 9.42 Partitioning the sorting and expander networks 943° Chip layout 8.44 Chip circuit simulation 945 Chip testing to isolate functions 946 Summary Pixel-planes graphic engine 951 Introduction 952. Raster-sean graphic fundamentals 95.3 Pixel-planes system overview 954 Chip electrical design 95.5 Chip organization and layout 9.36 Clock distribution Hierarchical layout and design of a single chip 32-bit CPU 9.6.1 Introduction 962 Design methodology 963 Technology updatability and layout verification 964 Results 965 Conclusion Conclusion APPENDIX COMPUTING NOISE MARGINS FOR CMOS AND NMOS INVERTERS REFERENCES BIBLIOGRAPHY 505 sit set 525 PRINCIPLES OF CMOS VLSI DESIGN| | INTRODUCTION PART 1 TO CMOS | TECHNOLOGY This Part orients the system designer toward CMOS technology. | Chapter 1 gives a brief overview of CMOS circuit design. Chapter 2 deals with basic MOS transistor theory. Chapter 3 summarizes some CMOS processing technologies and also introduces typical ‘geometric design rules, Chapter 4 introduces techniques to estimate petformance of CMOS circuits. Chapter 5 covers at some depth the Yerious alternatives available fo the CMOS circuit designe.Shei INTRODUCTION TO CMOS CIRCUITSGHAPTER 1 INTRODUCTION TO GMOS CIRCUITS ‘Over the past few yeer, Complementary Metal Oxide silicon (CMOS for short) technology hes played an increasingly important role in the world integrated circult industry. Not that CMOS technology is thet new. In fact the basic principle behind the MOS fold effect thanstator was proposed by [Lilienfeld as early a 1925 and a similar ‘tructure closely resembling a modern MOS transistor was proposed. by 0. Hell in 1935, Material problems foiled these early attempts, Experiments with carly feld effect transistors led to the invention Ei the bipolar transistor. The success of the latter device led t0 2 dlecline in interest in the MOS transistor. MOS devices remained se oddity until the invention of the silicon planar process in the arly 1960s. Material end quality control problems dogged the in- duction of the MOS device into commercial uses until around Yoo? [Cobb79}. Even then, single polarity p-ype transistors oF n- transistors wete favored. The use of both polarity devices on the ‘rane substrate was initially weed for very low power applications snch as watches, As the processing technology required inthe fab Fication of CMOS circuits was more complex than that for single ‘olarty transistors, CMOS was sparingly applied to general system Resigns. As nMOS production processes became more complicated, the additional complexity of the basic CMOS process decreased in Importance. Additionally, system designers were being faced with vg large chip sizes and power consumptions. For thls, and other Teosons that will become evident during the course of this book. GaOS technology has increased in its level of importance os a VLST technology. "The purpose ofthis book i to provide the designers of hardware or software systems with an understanding of CMOS technology, Circuit design, layout, and systom design sufficient to feel confident saith the technology. The text deals with the technology down to the layout level of detail, thereby providing a bridge from a circut toa form that may be processed. At the present time, relatively ‘Sutomated design approaches can take a logic schematic end au omatically convert these toa chip layout. However, these approaches Hovnot really capitalize on the fundamental objects available in an JG tansisiors, Hopefully, with texts such 2s this, software sys toms may be constructed that capture an expert's knowledge so that Mbitrarily structured and architected silicon systems of enormous Complexity can be built rapidly and eccurately. ‘Fhe book is divided into three main sections. Chapters 1-5 ossentilly provide @ circuit view of CMOS IC design. In the frst CRapter, a rather idealized view of CMOS technology will be taken Ghat some basic forms of logic and memory willbe introduced. This Is aimed at providing an unencumbered picture of the technology ‘without delving into unnecessary detail. Chapter 2 deals ata greater depth with the operation of the MOS transistor and the DC operation of the CMOS inverter and a fer other basic circuits of interest. The phenomenon commonly known as latch-up is also discussed. Some background to CMOS processing technology is presented in Chapter 3, The besic processes in current use are described along with some {Interesting process enhancements. Some representative design rules are also presented in this chapter, Chapter 4 treats the important Subject of performance estimation and characterization of circuit ‘operation. This cavers speed and power dissipation. A section su ‘marizing some frst order scaling effets is also included. A summary Of basic CMOS circuit forms is provided in Chapter 5. Various locking schemes are discussed with the emphasis being placed on ‘Greuit design and layout, The second section comprises Chapters 5-8. These chapters present a sub-system view of CMOS design. Chapter 6 focusses on a range of current design methods, identifying ‘where appropriate the factors {n common with CMOS. A section tn testing is also included. Symbolic layout techniques are discussed in Chapter 7, with particular emphasis placed on a design system implemented by one of the authors. Tis is included to give an ides ff some of the components required in a custom CMOS design System. Chapter 8 is'a tather hefty chapter on sub-system design, ‘bing the cieuits discussed in Chapter 5. Discussion is commenced ‘with a variety of adder designs. RAMs, ROMs, and PLAS are then covered. The final section is contained in Chapter 9, It consists of five examples of CMOS ICs of varying complexity. The purpose of these chapters isto illustrate the architectural decisions that lead to full custom chip design. Where appropriate the specific rela. tionships to CMOS technology are noted 1,2 MOS transistors ‘An MOS (Meta Oxide Sicon structure is ceted by superimposing Several layers of condvctng. sulting nd vanitor forming m tel, After a series of processing sop, a typialstuctre might Connie of levels called illusion, polyelicon, and metal That a Spero by Insulting layers, CMOS technology provides two types ‘Fount ao called vies in ths txt} an ype Wensitor {eMOS) and & piype transistor (pMOS). These ate foeistd In Seon ty using other negavely doped son th ich in elctrons {negatively charged) ot postive doped lion that sich in hoes {ise dul of elecons and postvely charged), Typical physical 42 MOS TRANSISTORS 5@ CHAPTER T INTRODUCTION TO GMOS CIRCUITS: 1.3 MOS TRANSISTOR SWITCHES 7 1.3 MOS transistor switches ‘The gate controls the passage of current between the drain and Source. Simplifying this to the extzome allows the MOS transisiors {a be viewed as simple on/off switches. Inthe following discussion. wwe will assume that aI" is @ high voltage that is normally set to 5 5 volts and called POWER or Vio. The symbol '0" will be assumed tobe low voltage that is normally set to 0 volts and called GROUND or Vs. The strength ofthe 1" and: signals can vary, The “strength” fof a signal is measured by its ability to sink or souree current. In 5) {general te stronger a signal, the more current it an source or sink. Where the tern output and input are used. the output will be the source of stronger t's and ‘0's than the input. The potser supplios (Woo und Vas} are the source of the stoongost “T's and "0s “The nMOS switch (N-SWITCH) is shown in Fig. 12a. The sche: matic representation is shown along with a switch representation ‘The gate has been labeled with signals, the drain a, and the source b, In an N-SWITGH, the switch is closed or ‘ON’ ifthe drain and S source ate connected. This occurs when there is 2°1' on the GATE, ‘The switch is open or OFF’ Ifthe drain and source are disconnected. ‘AD on the GATE ensures this condition. These conditions are ‘summarized in Fig. 1.25. An N-SWITCH is almost a petfect switch ‘when a0" is to be passed from an output to an input (say a to bl erm crogrsmeo. FIGURE 1.1. MOS transistor physleat structures seuctues forthe wo types of MOS transtorse shown a i 1 Farth rns be stuctur consi of ection of PVE Tee ee cing tr difsed srw of asbpe icon. The wet an eons s copped witha sandwich coasting af cae neds conductog secre called he GATE Simla ran oe ie stele const oa seton of YP tee easing two pope difused ren, The panatr eso econ a clecuode. Frthe purpose of invoduton, wel ase aa eaasserre hav tr adloelconnucons, which ade raat le DRAIN andthe SOURCE thee ing formed by te (hace fe pave) ifsed gions. The pt «contol {Pt oats fom of lara cent bated ho drain SE ce Int ho Gain aaa mayb seed wo ra eer ale They obj egulen and the eame cena donende om ibe dbseton of caren Ho. For ao We ‘ill regard them a5 interchangeable FIGURE 12, MOS trancistors viewed as switchesi L FIGURE 1.2. A comple: 1 tary swt CHAPTER 1 WTRODUGTION TO CNOS CIRCUS toy oT However, the N-SWITCH isan imperfect switch when passing a1! In doing this the voltage level s reduced lie (Ths explained in Section 2-5.) These cases ara shown in Fig. 1.2c. The pMOS Switch (P-SWITGH) is shown in Fig. 12d. [thas different properties thon the N-SWITCH, The P-SWITCH is closed or ‘ON’ when there {s.a"0 on the gate. The switch is open or ‘OFF’ when there is @ ‘on the gate. Fig. 1.2e depicts these conditions. Notice that the PMOS and aMOS switches are ON and OFF for complementary ‘Values ofthe gate signal. We denote this difference for 9 P-SWITCH ty including the inversion bubble in the notation. A P-SWTTGH is llinost pertect for passing “I” signals but is an_imperfect switch ‘ohm pessing ‘” signals. This is illustrated in Fig. 12 ‘By combining an NSWITCH snd a P-SWITCH in parallel (Fig, 1.3), we obtain a switch in which ae passed io an acceptable ‘erm this @ complemeniary switch or C- SwwFRCH ta creat where only a0" or” has to be assed the Sppropriatesub-switch [N or 2) may be deleted, reverting to SWITCH! or N-SWITCH. Note that a double cll logi is implied land its complement are routed to all al is aplied to the 1.4 CMOS logic 1.4.1 The inverter ‘Table 1.1 outlines the necessary stats to implement a logical inverter, If we examine this table we find thet when there 1s ¢‘O' on the eae veer Le ourr 4 FIGURE 1.4. Construction of a CMOS inverter input there isa 1’ a the output. Tis suggests a P-SWITGH connocted from aI" soutce (Voo] to the output as shown in Fig. 14a, When there is 4 t"on the input a0" has to be connected to the output ‘This suggests the addition of an N-SWITCH between the outpot and 270" source (Va). The completed circut is shown in Fig. 1b, Note that as the lower switch anly has to pass 20" [the Vsg source of ‘o's is stronger than the output of the inverter), only an N-SWITCH is needed. By similar reasoning, the upper switch, which only has to pass a1", needs only a P-SWITCH, The transistor schematic and ‘schematic icon forms for this are shown in Fig. 14. In general. 3 fully complementary CMOS gate always bas an N-SWITCH (pull own) array to com i is) and a P'SWITCH {pull-up) artay to connect the output to“ (Voo} a 1.4.2 Combinational logic If two N-SWITCHES are placed in series, as shown in Fig. 1.53 on pege 10, then the composite switch constructed by this action is Elosed (or ON) if both switches are closed (or ON) as illustrated in Fig, 15e This yields an “AND” function. The corresponding structure for P-switches is shown in Fig. 1.5b. The composite switch is closed if both inputs are set 100: ‘When two N-SWITCHES are placed in parallel (Fig. 1.9), the composite switch is closed if either switch is closed (ether input is a1). Thus an ‘OR’ function is creatod. The switch shown in Fig. 15d is composed of two P-SWITCHES placed in parallel. in tontrst to the previous case, if either input is a ‘0° the switch is closed, By using combinations of these constructions, CMOS combi- national gotes may be constructed. 14 (eMOs Losie 90 GHAPTER 1 INTRODUCTION TO CMOS CIRCUITS: Jd Hid gi 4 zg 4 ) adidi 4h $04 ae bag FIGURE 1.5. Series and parallel CMOS switch combinations pe ON bm ol J “ 1.4.3. The NAND gate Fig. 1.6 outlines the construction of a 2-input NAND gate using the constructions introduced in Fig. 15a and Fig, 1.5d. These structures are derived by examining the Karnaugh map in Fig. 1.62. The ‘0! term (pull-down to 0) dictates an AND structure (A.B). Grouping the '1’s together reeults in a structure to perform 4 + B. This is realized by the parellel p OR structure. The complemented signals 14 CMostosic 11 FIGURE 15. A CMOS NAND gateCHAPTER 1 INTRODUCTION TO CMOS CIRCUITS: TABLE 1.2._NAND gate truth table DonpuT BINPUT ANGSWITCH BNSWICH APSWICH BPSWITCN OUTPUT |v 7 ‘OFF ‘OFF ON ON 7 bog 1 OFF oN on OFF 1 1 ° oN. ore oN OFF 1 L 1 Ox. ON. ore OFF ° ae obtained automaticaly by the operation ofthe p-levice, The p- structure is the logical dual ofthe nstructure. This property is used. {in most complementary CMOS logic gates but not aecessarly Ta ‘ynamic gates or static gates that dissipate sialic powet). The roth table and SWITCH Hates ate shown tn Table TZ. BY inspection, ‘one may see that this implements the NAND function Some further points may be noted fom this example. Firstly ote that forall inputs there is always a path from the “1 or “0 (oo oF Vgy supplies) to the output and the full supply volages appear at the output, The lier feature Teads to a “fully restored" ogi family. This simplifies the circuit design considerably. In com parison to nMOS, where the load and driver transistors have to be {atioed, the ransistrs in the CMOS gate do-not have tobe ratioed for ti pte Ts function corey, Secondly, there iz sever «path irom the tte the" supplies fr any combination of iat sah ir contest io aMOS) Ase wil eam in ssequent chaps is iS the bess Toro Taw static power dissipation InCMOS. Tecreuit Sh ogi schomatis fora Tiaput NAND gate as shown in Fig. {oben Fig 16 Note that ager input NAND gates ae constructed By placing one N-SWTTCH in series onthe n side and one PSWITCH, in paralel for cach addtional input tothe gate 1.44 The NOR gate |A Zinput NOR gate is shown in Fig. 1.72. It is composed from Sections introduced in Fig. 1.5b and Fig. 15. according to the Kamaugh map. Note that the N and P switch combinations are the dual or complement of that for the NAND gate. The truth table is shown in Table 1.. This implements 8 logical NOR operation. The Corresponding schematics are shown in Fig. 1.7b and Fig. 1.7c. In Comparison to the NAND gate, extra inputs are accommodated in the NOR structure by adding N-SWITCHES in parallel and P- [SWITCHES in series with the corresponding switch structures, FIGURE 1.7. A CMOS NOR gate va CMOS LoGic 374 CHAPTER 1 INTRODUCTION TO CMOS CIRCUITS 7 14 CMOS LOGIC 18 | yaBLe 13. NOR gate truth table OT AMaMnGr ENGNG AROMAS PSM OORT , : - ee am : ” 5 q o 1 OFF ON ‘ON OFF o : . ° oro 4 Poe ¥ . 1.45 Compound gates . AG aga es erica a oe perallel switch structures. For example the derivation of the switch Eonnection diagram for the function F = ((A.B) + (C.D) is shown in Fig. 1.8, The decomposition of this function and generation of the diagram may be approached as follows. For the n-sde take the ‘ninverted expression ((4.8) + (C.D,)- The AND expressions (A.B) “ land (C.D) may be implemented by sories connections of switches . ae. fs shown in Fig. 1.8a, Now taking these as subentities and ORing ° a the result requies the parallel connection of these two structures. . “Tis is shown in Fig. 1-0. For the pside we invert the expression used for the n-expansion yielding (A + B).(C + D).This suggests two OR structures, which are subsequently connected in series. This prowression ls evident in Fig. 1.8. The final step requires connecting tne end of the p-stucture to“ (Veo) and the otherto the output One side of the nestrctre Is connected to‘0' (Vas and the other — oe to the output in common withthe pstructre, This vields the Anal i Connection diagram (Fig. 18d). The schematic con's shown in Fig. ‘ile, which shows that this gato may be used ina 2-nput mulkiplexer, ° . VODpee Mita cise bei ee ie ao nthe Karnaugh map for @ second function F = ((A + B =] , Dj is shown in Fig. 180 on page 26. The subsunction (A + B + his implemented a three parallel switches. This suucture is then placed Vy sees with a switch with D on the input. The funtion (D+ ABC) This requires three switches in seies connected in tur in parallel witha switch with D on the input. The completed fate is shown in Fig. 1.9 on page 16. In general, CMOS gates ma : felimplemanted by onalyaig the selva rssh ap for both i Togic structures and subsequently generating the requ “4 parallel combinations of Wansisiors. al Romeo 1.4.6 Multiplexers Complementary switches may be used to select between a number of inputs, thus forming a multiplexer function. Fig. 1.10a on poge z $7 shows a connection diagram for a 2-input multiplexer. As the FIGURE 1.8, Construction of function F = (AB) CDH7 CHAPTER 1 INTRODUCTION TO CMOS CIRCUTTS: CURE 19. Construction ¢ unction Barer oD) o switches have to pass ‘0's and ‘1's equally well, complementary Switches with n- end petransstors are used. The truth table fr the ructure in Fig 110 is shown in Table 1.4. The complementary Switch is also called a arsmission gat or pass gate (complementary) ‘A commonly used circuit symbol for the transmission gate is shown in Fig, 1400, The multiplexer connection in tems of this symbol and transistor symbols is shown in Fig. 1.10c + L ® FIGURE 1.10. A CMOS 2nput multiplexer 14.7 Memory Werhave now constructed a sufficient sot of CMOS structures to tenable e memory element tobe constructed. A simple flip‘Nop using ‘one 2-input multiplexer and two inverters is shown in Fig. 1.11 TABLE 1.4. Two input multiplexer truth table s 8 3 5 ourreT A ¥ ° 7 7 om) x 1 o 1 18) ° x 1 ° (4) t x 1 o uA} Ts GMOSLOGiIG 17{a CHAPTER 1 INTRODUCTION TO cmos CIRCUTTS FIGURE 1.11. Connection ‘of components for asim le CMOS tip-top . 3 —T PT When LD = "1", Qis set to B and Qs set to D (Fig. 1.116). When. LD is switched to ‘0’ a feedback path around the inverter pair is tslebished (Fig, 1.12¢). This causes the current state of Q to be Stored. While LD = ‘0" the Input D is ignored. 1.5 Alternate circuit representations: In this section we will examine some alternate representations for the circuits developed so far. Generally, a design can be expressed in terms of behavioral, tructural, and physical properties. 13 ALTERNATE CIRCUIT REPRESENTATIONS 19 1.5.1 Behavioral representation ‘A behavioral representation describos how a particular design should respond to a given set of Inputs. In Section 1.4 the behavior of a gate was defined in terms of its boolean function Tatar OD. This is a technology independent behavioral specification at the Jogi level. No notion of how to implement this function is implied nor Is eny speed performance implied. Higher levels of behavioral escription are possible. For instance, an add operation may be summarized in @ high level language by sun =a +b Here no method of addition is implied and the word length is assumed to be that ofthe machine. further exemple ofthe behavior of the flip‘Nop designed previously is as follows: Ie(LD == 4) THEW a= Note there may be some ambiguity associated with this strle of Dehaviorel representation. It could also represent a multiplexer without implying storage of state. Higher levels of behavioral spec ication can specify the types of tegistrs involved in a design and the transfers that occur between them. Even less information about {implementation is implied. At some stage it i possible to express behavior as an algorithm written in high level language. The alm fof most modern design systems is to convert some such specification {nto a system design in a minimum time and with maximum like lihood that the systom will perform as desired 1.5.2. Structural representation {A structural specification specifies how components are intercon: nected to perform a certain function (or achleve a designated behavior) ‘We will use as an examplé of a complete structural description language. MODEL, a language conceived by Lattice Logic Ld, (Lat®2). ‘The specification for the inverter 's Part dar (in) out Nest out in vss Peet out in vad End —(CHAPTER 1 “SURE 132. Graphical felons of structural de- [Lifptions tor 8 cos NAND gate (schematics) INTRODUCTION TO CMOS CIRCUITS ‘The first line declares a pat called 4 followed by alist of inputs in this case 10. The outputs appear on the other sie of the symbol in this case ot. Following this is alist of transistors with their type and connections in the form eanaistor-type Eee aratn-conn gate-cona out in ‘Thus the first statement describes an transistor with drata = aut, gate = in, source = vss. The second statement describes § prtansistor with zain = out, gate = in, so: vad "The description for @2-iapot NAND gate would be part sand? (a,b) -> ovt Signal i eet Nfet Peet Pret out bal out a vad out b vad End In this description the internal signal 4 is declared by the keyword Signal. A diagram of this appears in Fig. 1.12 It is worthwhile to compare this description with a possible behavioral description out = -(240) out = (aot (and ab )) Te i i “ . 75 ALTERNATE GIRCUIT REPRESENTATIONS [Note that we can infer al ofthe transistor connections from these code fragments. However, the intermediate node 1 is “hidden. Im the MODEL description, we may augment the purely structural ‘description with some parameters such as capacitance and transistor ‘Sizing thal will affect performance. Although notation for this can bbe added to the behavioral representation, rather baroque forms result and the simple elegance of the logial statement is los. An expended MODEL description might be part aand2 (a,b) -> Signal 11 atee out. tha vss oat bb Peet out a vad size Pfet out b vdd size = Capacitance 11 50 Capacitance a 100 Capacitance b 300 Capacitance ov 200 Here the capacitance (in some units} has been specified. n addition, the p-transistor sizes have been modified according to some notional size parameter. This is shown in Fig. 1.12b. As we will lem in Subsequent chapters, this type of information is crucial to the per formance of CMOS cizcults. In other words, the behavioral description fensures that the function may be correctly Implemented but no reference is necessarily made to speed or other operational parameter. ‘The structural description allows the specification of all components that affect performance. The citcuit simulator SPICE [Nage75]| uses ‘a circut description for the specification of transistor connectivity ‘The specification of the NAND gate might look like the following -SUBCKT NANDZ DD VSS A B OUT Na Ty A YSS WSS NPET W HP} OUT A VDD vDD PFET e2 OUT 8 VDD vDD PFET ch A USS SOEF CBB VSS SOfP cour our ¥ss s0ofF ‘ENDS In this description the intemal model in SPICE calculates the parasitic capacitances inherent in the actual device using the device dimensions Specified. The capacitance statements in the above description add extra routing capacitance.22 CHAPTER FIGURE 1.13. Schematic Fepresentation of CMOS. fiptop ;RODUCTION TO GMOS GIRCUTTS Defining o transmission gate in MODEL. we have Part tg (a;cyed) -> weet ac b Peet ach D znd ‘We can now define the flip-flop (also called a D Iatch) as follows {a signal appended with “bar” is a complemented signal) part flipflop (in, 14, ldbar, qe abar) Signal tg (in, 14, Ldbar) -> a ine (a) ~> qbar sae (bac) > 4g tg (4) Ldbac, 1a) > @ End [Now we can use the flip-flop and other similarly constructed parts to hierarchically build larger and larger circuits "A move familiar type of structural description is the schematic diagram shown in Fig. 1.13. Here we have the graphical hierarchy 7 Hf yr op 7 15 ALTERNATE CIRCUIT REPRESENTATIONS. of parts corresponding to the MODEL descriptions that we have eveloped. The specification range from the circuit lave (transistors). to the logic level (gates), tothe functional block level {memory and collections of gates). ‘To all intents, both types of description aro interchangesble, with preference for use dependent on the user. The schematic de- Scription is more immediately descriptive — "a picture is worth a thousand words.” However, the language representation has some particular benefits, especially ifthe high level constructs such as Tooping, conditionals, and paremoter passing are available. For in stance. if we wanted to change the size of transistors inthe inverter wwe might say Part iny (10) (al -> out Wfet out in ss size =a Pfet out in vad size = 240 Bnd Here, nis a parameter passed to the inverter description to specify the size of the transistors. Emerging design systems show promise cof dealing with language and graphical aspects of a design in a consistent fashion, 1.5.3 Physical representation ‘The physical specification for a crcult is used to define how the particular part has to be constructed to yield a specific structure {and hence behavior. In an IC process, the lowest level of physical specification isthe photo-mask information required by the various processing steps required on the fabrication process (see Chapter 5) At this stage, we will not dwell on these details but propose a ‘simple model for the physical nature of a CMOS circuit, assuming that a program can translate our notation directly to the format needed for fabrication ‘typical physical representation fora transistor would consist ‘of two rectangles representing the lithography required to fabricate the transistor, Procise “design rules” specify the size ofeach rectangle. In addition, for each different process these rules change and the corresponding dimensions change —not necessarily linearly. Rather than try and remember these rules, we will use a single symbol to representa transistor In a non-metrc format. We will retain a form that reflects the physical nature of the transistor. The physical symbol for an n-transistor is shown In Fig. 1142 and Plate 1. This mirrors the physical realization in which at least two process levels are overlaid. As we have seen, the gate connection is on one layer of, the process and the source and drain on anather layer. A similar 2 J3 GHAPTER 1 INTRODUCTION TO CMOS CIRCUS: LeGURE 1.14. Physical symbols for transistors snd simple eres Ny ern ia oboe symbol is used for the p-ransistor, as shown in Fig. 1.14b and in olor in Plate 2. Here, a “horizontal” transistor is shown, These Symbols are overlaid on agri, The transistor symbol occupies three rid points, The center grid point is the connection point for the {ale of the transistor. The grid point to the right (or above is the train and the grid point tothe left (or bolow) isthe source. These two terminals are interchangeable. The schematic symbols are also ‘Shown forthe n-and p-transistrs in terms of grid connection points, "A symbolic layout for an inverter may be constructed using these symbols. I is substantially the same as the schematic but we hhave had to be careful about the layers in which connections have been made, We have “wires” on four layers. The interaction ofthese Nae layers is summarized in Table 1.5. OK denotes that 2 connection may be made, while an X designates thet a direct connection may be made between the two layers. Any off-diagonal OK requires “contact” (C) to connect the two layers ‘A completed symbolic layout for the inverter is shown in Fig. 1u1de. The symbolic layout for a transmission gate is shown in TE ALTERNATE CIRCUIT REPRESENTATIONS 25 FIGURE 1.14, (Continues)15 ALTERNATE CIRCUIT REPRESENTATIONS 26 CHAPTER | INTRODUCTION TO GMOS CIRCUITS TABLE 1.5. Physical layer Interactions ‘DIFFUSION DIFFUSION POLYSILICON “ALUMINUM Faison OK x Tranaisor OK (er peiffusion x OK ‘Transistor ok) polysilicon Transistor Transistor OK. OKC) ‘tuminum OKC) OK (Gh OK (CL OK Fig. 114d. Color versions of these are found in Plate 1. This may also be expressed in the form of a language description. The following represents the transmission gate inthe ICDL language (see Chapter 7 begin tg a device n (2/1) 01 t2: device p (2/5) orseast wire alum (0,0) (4,0) wire alam (0,6) (4/6) wire poly (2-4) (2/3) wire poly (217) (2-3) wire aluz (3,3) (1/5) wire alua (3,3) (3/3) wire alum (2,3) (1,3) wire alam (3/3) (4/3), contact ag (1/1) contact a2 (3,4) contact md (1/5) contact nd (3,5) end It consists of transistor, contact, and wire statements with type ‘qualifiers and grid coordinates. Note that although ths is an abridged form of the mask information needed to fabricate the trnsmission. gt, substantially larger than the corresponding MODEL structural Sescription, Using a number of such structures, we can construct ‘a physical sub-assembly that constitutes aflip-Top according to Fig. 1.15. Fig. 1.18a shows a simple physical abutment ofthe two trans- ‘mission gate cells and two inverter cells. The Vig and Vap supplies Ihave beon arranged to feed across the bottom and top ofthe cells. A feedback line in metal connects the Q output to one side of the input multiplexer. In Fig. 1.15b, the internal circuit details of the cells are displayed in the form of schematic circuit symbols. Finally, Fig. 1.15c shows the symbolic layout representation, which is identical in topology to that shown in Fig. 1.15b. Plate 2 illustrates this example in color. “To a large extent, most CMOS IC design involves the steps Illustrated in the preceding sections. Once a behavior is defined, the logie corresponding to that behavior is designed. That leads to a trangistor circuit description. Finally, a layout may be designed for the particular logic function. Quite often, frequently used logic structures may be designed at the layout {evel and placed in @ library. These library elements may then be assembled as illustrated fn Fig 1.16 to build more complex structures. An altermative to this approach is to compose primitive elements such as flip-ops from individual transistors. This yields more efficient layouts. Methods for designing inthis manner will be treated in subsequent chapters. FIGURE 1.15. Physical ‘construction of @ CMOS ‘pop 7 —‘CHAPTER 1 INTRODUGTION TO CMOS CIRCUTTS 1.6 _CMOS-nMOS comparison Many designers may have been introduced to VLSt design through MOS design. In order to illustrate tho salient features of CMOS. a Lape 1. CxO8 CMOS-nMOS quick summary MOS DS Se Togie Levels | ally restored logic. i. output sets at Yao oF Vs (GND) (i) Teansition Times oe an fall times are ofthe same order 1) Transmission Gates ‘Transmission gate passes both loge loves el ‘The output of transmission gate can be used qo dee the input of other teasmisson gates 1) Power Dissipation ‘Almost ceo static powar dissipation, However ‘power is dissipated duving logic transition Procharging Characteristics ‘Both n-type and plype devices ae aallabe for Srecharging 2 bus to Vop and Vax. Nodes can Be charged fully to Von or alternatively t0 Vs ina shor time. (i) Power Supply Toltage required to switch agate Is a ied pes ‘entage of Va. | arable range 1.310 15 volts (vi) Packing Density Require 2N deviers for N inpuls fr comple ‘mentary sale gates. Less for dynamle gates ii Pull to Pull-doven Ratio ‘Lod todrver device eatlo i typieally :t or 2A, Lg tayoun EOS encourages ele layout sls + Output does not sete at Vs {GND} — hence de add nose margin.” + Rise mes ae inherently slower than Fall + Pass transistor transfers loge 0° well but iogic "is degraded. Pass transistor cannot drive the gate of «second pass transistor With output of a ven gute = 0" power is dis sipatad inthe circuit i adition to power Giesipted during fogic vansitons.* + With enhancement mode transistor the best one ‘an do (with normal clocking) i to charge a bus to (Van ~ Yi). Generally use of bootstrap ping or hot cleking is needed to precharge to Vow + Somavehat dependant on supply voltage. Fined, + Reguire (+ 1) devices for N inputs + Load-to-enhancementdcver rll is typically 42 To optimize the loge 0" output level and min. Smize current consumption. ‘Depletion lad and diferent drtver transistor izes ibibo layout regularity quick summary” is ptesented in Table 1.6. However. it should be ‘Shessed that this is a broad overview and individual points may ary widely in importance. The comparisons are true of raioed Toate stvles for nMOS and those items marked with an asterisk are not valid for ratioless nSIOS logic design (dynamic circuits), The main points 10 note are that the output logic levels of CMOS are fully restored. CMOS gate consumes no DC povrer when the output is at"1'or 0'level. and 2N devices are required for an N-input gate for a fully complementory gate 1.7_Summary This chapter introduced a simple model for an MOS transistor and Gveloped logic that uses p-teansistors and n-transistors. This led {oa bosie discussion ofthe various levels of representation of circuits lind methods of composing these representations. The remainder of this book will elaborate on the materal introduced in this chapter. 1.8 Exercises 1.8__Exercises Ih elements 44 Design @ +-input NAND gate using CMOS swi Draw the ful transistor circuit for the function. La F = AB BCFAC implements a complemented cary function Design a complementary CMOS gate to perform this function. 1.3 Design @ input OR gate. Ta what conclusions do you come? 14 A 4-input multiplexer structure is needed to multiplex four ‘busses to a register in a microprocessor. Show two ways in which this may be implemented. Can you think of any reasons why one methed is preferable to the others? 1.5 Using graph paper and colored poncils, complete a symbolic, layout for the gates designed in Exercises 1.1, 1.2, and 1.3, What problems do you encounter? 16 Design and complete a symbolic I jout for a CMOS memory tlement other than that shown in Fig. 1.11, Include waveform Sequencing required for operation Te EXERCISES Ey— * | Mos TRANSISTOR 7 THEORY4a 444 I “ » “ FIGURE 21. MOS transis- tor symbols GHAPTER 2 MOS TRANSISTOR THEORY — 2. Introduction In Chapter 4 the MOS transistor was introduced in terms of its ‘operation as an ideal switch. In this chapter we will examine the characteristics of MOS transistors in more deal olay the foundation for predicting the performance of the switches. which is less than ideal. Fig. 2.1 shows some ofthe symbols that are commonly used for MOS transistors. The symbols In Fig. 21a will be used where itis only nacessary to indicate the switch logic necessary to build {2 function. I the substrate connection needs to be shown the symbols in Fig. 2.1b will be used, Fig, 2.1¢ shows an example of the many symbols that may be encountered in the literature ‘An MOS transistor is termed a majority-carier device. in which the current in a conducting channel between the source and drain is modulated by a voltage applied to the gate. In an n-type MOS transistor (ie. nMOS), the majority carriers are electrons. A positive ‘voltage appliod on the gate with respect to the substrate enhances the number of electrons in the channel (the region immediately ‘under the gate) and henoe increeses the conductivity ofthe channel. For gate voltages less than a threshold value denoted by V,, the channel is cutoff, thus causing a very low drain-to-source current ‘The operation of a p-type transistor (ie. pMOS) is analogous to the MOS transistor, with the exception that the msjority carriers are holes and the voltages are negative with respoct to the substrate. ‘The frst parameter of interest that characterizes the switching behavior of an MOS device is the threshold voltage. V, This is defined as the voltage at which an MOS device begins to conduct mon"), One can graph the relative conduction against the dif- ference in gate-lo-ource voltage in terms of the sourceto-drain ccurent (l.) and the gate-o-source voltage (Vy). These graphs for a fixed drain source voltage Va, ere shown in Fig. 22. Itis possible to make ndevices that conduct when the gate voltage is equal to the source voltage, while others quire a postive diference between gato and souree voltage to bring about conduction (negative for Prdevices). Those doviees that are normally cut-off (ie., noncon- ducting) with 2oro gate bias (gate voltage-source voltage) ae further classed as enhancement mode devices, wheress those devices that ‘conduct with zero gate bias are called depletion mode devices. The channel transistors and p-chennel transistors are the duals of each other; that is, the voltage polarities required for corect operation are the opposite. The threshold voltages for n-channel and p-channel fovices are denoted by V,, and V,, respectively In GMOS technologies both n-chennel and p-channel transistors are fabricated on the same chip. Furthermore, most CMOS integrated Circuits, at present, use transistors of the enancement type. orl ee owe: 7 vourace : a se om 2.1.1. nMOS enhancement transistor ‘The structure for an n-channel enhancement type transistor shown in Fig. 2.3 consists of a moderatoly doped p-type silicon substrate into which two heavily doped n° regions. the source and drain. Jone Set ROLY Oy 21 INTRODUCTION 33 FIQURE 22. Conduction characterises fo hancement and depletion mode transistors (assum Ing feed ¥.) FIGURE 23. Physica! structure of an AMOS, transistor‘a CHAPTER 2 MOS TRANSISTOR THEORY FIGURE 24. Creation of an inversion layer in an ‘transistor are diffused, Between these two ragions there is @ nerrow region of piype substrate called the channel, which is covered by a thin Tasulating layer of silicon dioxide (SIO;) called gate oxide. Over this oxide layer is ¢ polycrystalline silicon (polysilicon) electrode, teferred to a: the gate, Polycrystalline silicon is silicon that is not Composed of a single crystal. Since the oxide layer is an insulator, fhe eurrent through the gate and channel is essentially zero, Because Of the Inherent symmetry of the structure, there is no physical distinction between the drain and source regions. Since SiO; has {elatively low loss and high dielectric strength. the application of high gate field is feasible. in operation, « postive voltage is applied between the source and the drain (Vg). With zero gate bias (Vy, = 0), no current lors from source to drain because they are effectively insulated from rach other by the two reversed biased p-n junctions shown in Fig. 3 {indicated by the diode symbols). However, a voltage applied to the gate which is positive with respect tothe source and substrate, produces an eleczie field E across the substrate, which attracts lactone towards the gate and repels holes. Ifthe gate voltage is Sulficfenty large. the region under the gate changes from p-type to type (due to accumulation of attracted electrons) and provides @ Conduction path between the source and drain. Under such a com- ition, the surface of the underlying p-ype silicon is said to be {nverted. The term n-channel is applied to the structure, This concept {s further illustrated by Fig, 2.4, which shows the intial distribution Of mobile positive holes in the silicon insulating layer before the Spplication ofa positive gate voltage and the final distribution after the application of gate voltage. As these ions dit toward the interface they tend to induce more negative charge at the silicon surface beneath the gate, resulting in the formation of the inversion layer. ‘The difference between a p-n junction that exists in a bipolar transistor oF diode (or between the source or drein and substrate) Peers and the inversion layersubstrate junction i that inthe p-n junction. the n-type conductivity is brought about by a metallurgical process: that is the elecrons are introduced into the semiconductor by the introduction of donot fons. In an inversion laver-substrate junction. the n-type layer is induced by the electric field £ applied to the fate, Thus, this junction, instead of being a metallurgical junction {4 feld-induced junction. Electrcelly, an MOS device therefore ats asa voltage-controlied switch that conducts initially when the gate-to-source voltage, Vax: jg equal to the threshold voltage, V;. When a voltage Ve, is applied betoreen source and drain. with V = V).the horizontal and vertical components of the electrical field due to the source-drain voltage Gnd gate to substrate voltage interact, causing conduction to occur ‘long the channel, The horizontal component of the electric eld fsssocisted with the drainio-source voltage (Le. Vy > 0) i responsible for sveeping the electrons from the channel towards the drain, AS the voltage from drain-o-source is increased, the resistive drop falong the channel begins to change the shape of the channel chat- fcteristic. This behavior is shown in Fig. 2.5. At the source end of the channel. the full gate voltage is effective in inverting the channel However, at the drain end ofthe channel. only the difference between 21 INTRODUCTION o © FIGURE 25. nMOS device behavior under the influence of different terminal vottages 38‘CHAPTER @ MOS TRANSISTOR THEORY the gate and the drain voltages is effective. When the effective gate voltage (Vu — Vj) is greater than the drain voltage, the channel becomes deeper as Vis is increased. This is termed the “timear,” “resistive,” of "unsaturated" rogion, where the channel current I isa function both of gate and drain voltages. If Va, > Vq.~ Ve. then Viz < V; (Vqc is the gate-to-drain voltage), and the channel becomes pinched-off — the channel no longer reaches the drain. This is illustrated in Fig. 2.Sc. Howover, in this case, conduction [s brought about by a dif mechanism of electrons under the inluence ‘of the positive drain voltage. As the electrons leave the channel, they aie injected into the drain depletion rgion and are subsequently accelerated towards the drain. The voltage across the pinched-off Channel tends to remain fixed at (V,, ~ Vi). This condition ts the ‘saturated state in which the chansel curten is controlled by the gate vollage and is almost independent of drain voltage. It should be noted that » depletion region is devoid of mobile carriers and therefore is able to insulate the channel from the rest ofthe substrate. ‘Thus ao significant current passes through the substrate because, in effect. @ reverse biated pot junction js formed with the channel [Fig 23c), For fixed drainsto-source voltage and fixed gate vot the factors that influence the level of drain current ly owing between source and drain (fora given substrate resistivity) are + the distance between source and drain + the chennel width + the threshold voltage V, + the thickness of the gate-inaulating oxide laver + the dielectric constant of the gate insulator + the carrer (electron or hole) mobility 1. ‘The normal conduction characteristics of an MOS transistor can be categorized as follows: + “Gut region: where the current flow is due to what is termed the source-drain leakage current. ‘neae” region: region of weak inversion whece the drain current increases linearly with gate voltge. + “Saturation” region: channel is strongly inverted and drain current is independent of the drain voltage ‘An abnormal conduction condition called avalanche breskdown or punch-through can occur if very high voltages are applied to the train, Under these circumstances, the gate has no control over drain current. CEI ees wus) 24.2 pMOS transistor So far our discussions have been primarily directed towards nbiOS. However, reversal of n-type and pelype regions vield a p-channel MOS transistor. This is illustrated by Fig. 2.8. Application of a negative gate voltage (v.21 sourco} draws holes into the region below the gate. resulting in the channel changing from n-type to p-type. Thus similar to nMOS, a conduction path is created between the source-to-drain. In this instance, however, conduction results from the movement of holes (vs. electrons) inthe channel. A negative drain voltage sweeps holes from the source, through the channel to the drain 2.1.3 Threshold voltage ‘The threshold voltage, V,, for an MOS transistor can be defined as the voltage applied between the gate and source of an MOS device below which the drain-t-soutce curent I, drops to ze. In general the threshold voltage isa function ofa number of prameters including, the following: + gate material + gate insulation material + gate insulator thickness + channel doping + impurities at silicon-insulator interface + voltage between source and substrate Vig In addition, the absolute value of the threshold voltage decreases with an increase in temperature. This variation is approximately 21 INTRODUCTION FIGURE 26. Physical ‘structure of pMOS: transistor 738 CHAPTER 2 MOS TRANSISTOR THEORY FIGURE 2.7. The effect of ‘connected transistors <4 mV/‘C for high substrate doping level. and -2 m\"C for low doping level {VaGr66) 2.1.4 Threshold voltage adjustment This often necessary to adjust the native (original) threshold voltage ‘ofa device. Tivo common techniques used for the adjustment of the threshold voltage ental varying the doping concentration at the Silicon insulator interface through ion implantation. or using different insulating material for the gate. In this later approach, a layer of silicon nitride (SiN,) (selative permitivity of 7.5) is combined with 4 layer of silicon dioxide (relative permittivity of 2.9. resulting in fn effective celative permittivity of about 6. which is substantially larger than the dislectrie constant of SiO... Consequently. for the same thickness a5 an insulating layer consisting only of silicon dioxide, the dual dielectric process will be electrically equivalent tava thinner layer of SiO. In order to prevent the surface of the Silicon from inverting under the regions between transistors, the ‘threshold voltage in these feld regions is increased by heavily doped. diffusions. implants of the silicon surface. or by making the oxide laver very thick. MOS transistors are self-isolating so long as the surface of the silicon may be inverted under the gate, but not in the regions between devices by normal circuit voltages, 2.1.5 Body effect [As we have seen so far, all devices comprising an MOS device are fmade on a common substtate. As a result, the substrate voltage of tll devices is normally equa (In some analog circuits this may not be true] 12 ver in arranging the devices to form gating functions ittmight be necessary to connect several devices in series as shown in Fig. 2.7 (for example the NAND gate shown in Fig. 1.61, This may result in an increase in soutoe-o-subsrate voltage as we proceed ‘vertically along the series chain (Via, = 0, Vx, # 0} ‘Under normal conditions, that is; when Vy > V;, the depletion layer width remains constant and charge caftirs are pulled into the channel from the source. However, as the substrate bies Vay (Vance ~ Var) i8 increased, the width of the chennel-substate eplotion layer also increases, resulting in an increase inthe density of the trapped carriers in the depletion layer. For charge neutrality to hold, the channel charge must decrease, The resultant effect is that the substrate voltage Vz adds tothe channel-substrate junction potential. This increases the gote-channel voltage drop. The overall fect is an increase in the threshold voltage V, (V > V,)- The ttfective threshold voltage can be approximated by the following expression: Vi = Vos = (Vial? ea) ‘where Vyo is the threshold voltage with Vig equal to zero and is ‘constant which depends on substrate doping. The negative sign is used for pMOS. Typical values for y lie in the range of 0.4 to 41.2, As we shall learn in Chapter 3, the type of CMOS process can. have a large impact on this parameter for both n- and p-transistors, ‘The threshold voltage effectively increases, leading to smeller device ‘currents, which in turn leads to slower circuits. 2.2 _MOS device design equations {As stated previously, MOS transistors have three regions of operation: + cutoff region + linear region + saturation region. ‘The ideal (rst order) equations (Cobb70}[Sah64] describing the bo havior of an nMOS device in the three rogions are: V0 cutoff (a) D< Va >" 6p, the expression reduces to the form introduced ing, (2.2). It should be noted that simplified equations that describe the behavior of en MOS dvice assume that cari mobility is constant, do not fake into account the variations in channel length due to the changes in drain-to-source vollage Vi, and furthermore neglect leakage currents, For long channels, the influence of channel variation is of little consequence. However, 5 devices are scaled down, this variation should be teken into sccount. A reduction in channel Tength increases the (W/L) ratio, thereby Increasing 8 as the drain voltage increases. Thus there is a finite output impedance in the saturated region. ‘The effective channel length is approximated by (Va - Mp ~ Vile en tg =t- fen V5 ‘The same MOS device equations also apply to the pMOS device. aeee 32 HAPTER 2 MOS TRANSISTOR THEORY FIGURE 29. V4 charac- teristics for mand pransstors ‘The only difference inthe result isthe change in the sign associated with the voltages and drain current. 2.24 VA characteristics ‘The voltage-current characteristics of the the linear and saturated regions are repres that we use the absolute value of the voltages concerned to plot the chsracteristics on the same axes. The boundary between the linear and seturation regions corresponds to the condition Vad = IV. ~ Vj] and appears as a dashed line in Fig. 29. ‘The output resistance (ie., channel resistance) in the linear repion can be obtained by ditferentiating Eq, (2.2b) with respect to Vay which results in an output conductance of tim 2 = av, ~ Vo. @ ‘Upon rearrangement the channel resistance R, is approximated by es) which indicates that itis controlled by gate-o-source voltage. The {elation defined by Eq, (2.9) is valid for gate-to-source voltages that maintain constant mobility in the channel In contrast, in saturation (Vg. ~ Vill the MOS device behaves like a current source, the current being almost independent of V.,. This may be vetified from Eq. (2.2c) since a, fe) ‘The transconductance gq expresses the relationship between output current [j, and the input voltage V.,. and is defined by al aM esecmtr (220) ean tis used to measure the gain of an MOS device. {nthe linear region {nis given by Senna = BV ey (a2) and in the saturation region by Baas = BtVes ~ Vo (19) For example, the value of transconductance for an n-type transistor fn the linear region is Ce). am Since transconductance must have a positive value, absolute values fare used for voltages applied to p-type devices. 2.3. The complementary CMOS inverter — DC characteristics ‘A complementary CMOS inverter is realized by the series connection of a p- and n-devico, as shown in Fig. 2.10. In order to derive the DDC transfer characteristics for the inverter (output voltage Vo a5 a function of Va). we start with Table 2.1, which outlines various regions of operation for the n- and p-ransistors, In this table. V,, is the threshold voltage of the n-channel device, and V,, is the thresbold voltage of the p-channel device. The objective isto find the variation in output voltage (Vo} for changes inthe input voltage Wale» ‘We commence with the graphical representation ofthe simple algebraic equations described by Eq. (22) forthe two transistors 23. THE COMPLEMENTARY CMOS INVERTER — DC CHARACTERISTICS a(5 ORMPTER 2 MOS TRANSISTOR THEORY 23 THE COMPLEMENTARY GMOS AVERTER — DC CHARACTERISTICS 45 [SURE 210, 8 CMOS inverter (with substrate connections) Sa! shown in Fig, 2.11a (CaMi72), The absolute value of the p-ransistor es train curreot [inverts this characteristic. Ths allows the V-c fcteristcs for the p-device to be reflected about the x-axis (Fig {Zt1b), This step is followed by taking the absolute value of the p- Gaview Vj,, and superimposing the two characteristics yielding the resultent curves, shown in Fig. 2.11c. The input/output transfer ‘curve may now be determined by the points of common V iter Section im Fig, 211¢. Thus, solving for Vig, = Vie, and ly, = lay fives the desized transfer characteristics of a CMOS inverter as t Husteated in Fig, 2.12. The switching point is typically designed to be 30 percent of the magnitude of the supply voltage: =Veo/?, During transition, both transistors in the CMOS inverter are mo- 1 mentaily “ON. resulting ln a short pulse of current drawn from the power supply. This Is shown by the dotted line in Fig, 212. FIGURE 211. Graphical derivation of inverter cha acteristic (lad tne) TABLE 2.1. Relations between voltages for the three re- ons of operation of a CMOS inverter x (CUTOFF LINEAR, SATURATION Vn eve Te Ver Ve? Vyi Vee, + Veo Vee ¥y + Van u peeve Mn? Vee Va Vo> Vy Vn > Vy + Veo Ve? Mh va> Me, FIGURE 212. HOS in- Werte DC transfer eharac- teriatie and operating regions: nedevice i Vans VaWe CHAPTER 2 MOS TRANSISTOR THEORY FIGURE 213. Equivalent Va~ Vu pehanneli Va ~ Vo>V, Vo< Vn = Vw Combining the two inequalities results in Va ~ Va Vo< Va Vi (22) This indicates that with Vi = Voo/2. Vo varies within the range Shown, Of course, we have assumed that an MOS device in saturation behaves like an ideal current source with drain-io-source current being independent of Vn reality, es Va, increases, Ly also increases slightly, thus region C has a finite slope. The significant factor to be noted is that in region C we have two current sources in series, Rihtch is an “unstable” condition. Thus a small imput voltage has ‘Tange effect at the output. This makes the output transition very Stoem, which contrasts with the equivalent nMOS inverter charac: teristic. The relation defined by Eq (2.20)'s particularly useful since it provides tho basis for defining the gate threshold Vae, which cortesponds to the stato where Vo = Vi Region D. This region is described by Voo/2 < Via = Voo ~ Vi ‘The pedevice isin saturation while the n-device is Operating in its Tinear cegion. This condition is epresented by the equivalent cieult shown ln Fig. 2.14. The two currents may be written 3 = Veo - Vult Tay, = — 58Mn and with a) Bete Voo War] Region E. ‘This region is defined by the input condition Vin = Voo cei in which the p-device is cut-off (,, = 0), and the n-device ‘TABLE 2.2. Summary of CMOS inverter operation” Teen CONDON pDEWCE nDEEE Bete Y® amet bentyl te Trees cowed Vg = 03 Wy = LE By ae is in the linear mode. Here. Vy, than V,,. The output inthis egion is Vo (2a) From the transfer curves of Fig. 212, it may be seen thatthe transition between the tivo states is very “steep.” This characteristic is very Gesirable as the noise Immunity ie maximized. This is covered in ‘more detail in Section 2.3.2. For convenience, the characteristics fssociated with the five regions are summarized in Table 2.2 ~ Veo, which is more positive 2.3.1 Influence of 6/8, ratio on transfer characteristic In order to explore tho'variations of the transfer characteristic as a function of fa/B,, iti posible to plot the transfer curve for several Values of f/f shown in Fig. 2.15. Here, we note that the sate threshold voltage Viy defined by the state in which Vin = Yo (2.28) fs dependent on fy/f,- Thus, for @ given process, if we want to change 8/8, we need to change the channel dimensions. ie, channel Tength Land channel width W. From Fig. 2.15 it can be seen that as the ratio Pa/P, is decreased tho transition region shifts from left to right; however, the output voltage transition remains sherp and hhence the switching performafce isnot affected. This behavior should be contrasted with the nMOS inverter, where the transition gsi depends critically on the ratio ofthe load (pull-up) end driver (pull-down) transistors. For the CMOS inverter a ratio of (228) 23. THE COMPLEMENTARY CMOS INVERTER — OC CHARACTERISTICS ourrur Von #10) Vo = Wa +0) = VET50 CHAPTER 2 MOS TRANSISTOR THEORY may be desitable since it allows a capacitive load to charge and {ischarge in equal times by providing equal current source and sink ‘capabilities. This will be expanded upon in Chapter 4. “Another factor thet needs to be. considered isthe influence of temperature on the transfer characteristics [Cobb66]. As the tem- perature of an MOS device is increased, the effective carier mobility Pin the channel decreases. This results in a decrease in A, vehich fs related to temperature T by pxT 27) ‘Therefore (220) Since the voltage transfer characteristics depend onthe rato ./B, nd the mobility of both holes and electrons ae simian afected this rato fs independent of temperature to 2 good approximation. Both Vand ¥, decrease slightly as temperature increases. This implies that af temperature increases, the extent of region A is ‘duced while the extent of eepion E increases. Thus the overall Transfer chesatterstics of Fig. 215 shift to th left as temperature Increases, Based on the Bguresgivon earlier, ifthe temperature rises br °C, the thresholds drop by 200mV each. This would cause a 7 shi in the iat threshold ly pours 218. nce Breiner ans characteristic Zo. THE CONPLENENTARY CMOS INVERTER — DG CHARACTERISTICS 51 rc Bl oho ‘a a ra 2.3.2 Noise margin Noise margin is a parameter closely related to the input-output voltage characteristics, This parameter permits one to determine the Towable noise voltage on the input of a gate so that the output ‘wil not be aifeced. The specication most commonly used to specify noise margin (or noise immunity) isin terms of two parameters — the LOW noise margin, NM,, and the HIGH noise mergin, NM, With reference to Fig. 2.16, NM; is dofined as the difference in ‘magnitude between the maximum LOW output voltage of the driving E gate end the maximum input LOW voltage recognized by the driven gate, Thus NM, (229) “The value NMyis the difference in magnitude between the minismam HIGH output voltage of the driving gate and the minimum input HIGH voltage recognized by the receiving gate. Thus NM = [Vo (230) ~ Varad where Voie = thinimum HIGH input voltage Vay Vorine © minimum HIGH output voltage ‘maximum LOW input voltage Vounn = maximum LOW output voltage.| foune 217. cMos im fF nolee margins Fr — (5 Giapren 2 wos TRANSISTOR THEORY ‘The definitions om page 51 are illustrated in Fig. 2.16. Generally, it is desirable to have Vy = Va and for this to be @ value that is taidway in the “logic swing.” Vo. to Voy- This implies that the transfer characteristic should switch abruptly tot is, there ‘Should be high gain in the transition region. For the purposes of falculating noise margins, the transfor characteristic ofthe inverter nd the definitions of voltage levels Vi. Var» Vis Vow are shown. in Fig, 227, To determine Va, we note that the inverter is in region BB of operation, where the p-device i in its linear region while the device isin saturation. The result of analyzing these quantities (B, = Bp) [see Appendix A) are as follows:* ny = Ben Bl = Be ean sad : Ys ay, = Mina oan tn the ease Va, = IVa] = 02 Vo we have nM, = Ny = (41 ~ 95 = 0425 Note that sv, = Vge then NMy and NH increase a threshold voltages are increased. Note that if either NM, oF NMy for a gate Tre reduced (~-1Voo) then the gate may be susceptible to switching hose that may be present on the inputs. Ths i the eason to keep ihack of noise margins. Quite often, noise margins ae compromised —Darvatca by K Taped, Duke Universi. 24 ALTERNATE GMOS INVERTERS to improve speed. Circuit examples later in the book will illustrate this trade-of. 2.4 Alternate CMOS inverters Fig. 2.188 on page 34 shows an inverter that uses a p-device pul ‘up that has its gate permanently grounded. This is roughly equivalent te the use of a depletion load in nMOS. This circuit is used in a ‘arity of CMOS lope circuits. I has the disadvantage that i dissipates DC power when the n-transistor [pull-down] is turned on. Similar to the complementary Inverter, a graphical solution to the transfer characteristic Is shown in Fig, 2186 on page 54 for various sized pedovices. This shows that the ratio of Ay/B, affects the shape of the transfer characteristic and the Vi. of the laverter, To determine the ratio of the n-transstor size to the paransistor size the circuit in Fig, 2.19 on page 84 will be used. This shows two cascaded pseudo-nMOS inverters. In order to cascade inverters without det Fedation of signal levels, the following condition should be met ve “Vv, where Vigw = the gate threshold voltage For equal noise margins, the gate threshold voltage Viq, should be set to approximately 0.5Vzo. At this operating point, the n-device {pull-down} is in saturation (0 < V,, ~ V,, < Va,). and the p-device (pull-up) is in the linear mode of operation (0 < Va, tering of SiO' {i crartens Guos PROCESSNG TecHnOLOGy 7 te Go Ge om faa i Tz € + There are no intermediate hardware images such as ecticles or masks; that is, the process may be direct. + Different patterns may be accommodated in different sections of the wafer ssithout difficulty. + Changes to patterns can be Implemented quickly ‘The main disadvantage that has precluded the use of this technique in commercial fabrication lines is the cost of equipment and the large amount of time requized to access all points on the wafer. 3.1.4 The silicon gate process 50 far we have touched on the single crystal form of silicon used in the manufacture of wafers and the oxide used in the menufacture land operation of ctcuits. Silicon may also be formed in en amorphous form (oot having a carefully arranged lntice structure) commonly talled polyerysialline silicon or polysilicon. This is used as an {atereonnect in silicon ICs and as the gate electrode on MOS tan- Sistors, The most significant aspect of using polysilicon as the gate Slectrode is its ability to be used as a further mask to allow precise definition of source and drain electrodes. This is achieved with minimum gate‘o-souree/drain overlap, which we will leam improves Circult performance. Polysilicon is formed when silicon is deposited fon SiO, of other surfaces. In the case of an MOS transistor gate tlectrode, undoped polysilicon is deposited on the gate insulator. Polysilicon and source/drein regions are then normally doped at the same time. Undoped polysilicon has high resistivity. This char- fuleristc i used fo provide high value resistors in static memories. ‘The resistivity of polysilicon may be reduced by combining it with, a refractory metal (s0e Section 3.25) "The steps involved in a typical silicon gate process entail pho- tomasking and oxide etching, which are repeated a number of times during the processing sequence. Fig. 3.4 shows the processing steps titer the initial pettering of the SiO, which was shown in Fig 3.3, The wafer is initially covered with a thick layer of SiO, called the field oxide. The feld oxide is etched to the silicon surface in lreos where trensistors are to be placed (Fig. 34a). A thin, highly ‘controlled layer of SiO, is then grown on the exposed silicon surface ‘This is called the gate oxide or thin oxide or thinox (Fig. 3.4) Polysilicon is then deposited over the wafer surface and etched to form interconnections and transistor gates. Fig. 3.4c shows the result fof an etched polysilicon gate. The exposed thinox (not covered by polysilicon is then etched away. The complete wafer is then exposed oa dopant source, resulting in two actions (Fig. 3.4). Diffusion 31 SILIGON SEMICONDUCTOR TECHNOLOGY: AN OVERVIEW 69, sees om om « pnasrare So A "* hos » saat a so serene FTE sm junctions ere formed in the substrate and the polysilicon is doped with the particular type of dopant. This reduces the resistivity of the polysilicon. Note that the diffusion junctions form the drain and source of the MOS transistor. They are formed only in regions where the polysilicon gate does not shadow the underlying substrate This is referred to a8 a s0f-ligned process because the source and drain do not extend under the gate. Finally, the complete structure Is covered with SiO, and contact holes ae etched to make contact with underlying layers (Fig, 34e). Aluminum or other metallic in- Terconnect is evaporated and etched to complete the final connection of elements (Fig. 2.) FIGURE 34. Fabecation ope fora acon gate AMOS transistor70 CHAPTER 3 GMOS PROGESSING TECHNOLOGY FIGURE 25. CMOS pro- ‘cans cross-section and fayout conventions QD rocrenscon —-POLYBLICON ——PORYSLIEON - 7 = ~ Kw rowreucon2 pouy2 pow 3.2__CMOS technologies 10S (Complanentry Metal Oxide con weal negsand se sGinw contender for exiting and ature VL ystems, CMOS a eet low powers ret ochnaogy tht bat Foes sity of povcig «lower power-dley product than cm bie dengue nMOS or POS Technologie, In his section aa et ovrvie of fou dominant CMOS technologie. with {SRO eam th roses stp. Tiss ncladed pany seid for beter appeation ofthe layout ses tat are 9 flow 32 ‘The four dominant CMOS technologies are: + powell process + newoll process + twin-tub process + silleon on insulator, During the discussion of CMOS technologies, process cross-sections fand layouts will be presented. Fig. 3.5 summarizes the drawing conventions. 3.2.1 The p-well process ‘A common approach to p-well CMOS fabrication has been to start ‘with a moderately doped n-type substrate (wafer), create the p-type well for the n-channel devices, and build the p-channel transistor {in the native n-subetrate. Although the processing steps are somewhat ‘complex and depend on the fabrication line, Fig. 3.6 on pages 72- 73 illustrates the major steps involved in a typical p-well CMOS ‘process. The mask that is used in each process step is shown in {Addition to a sample cross-section through an ndevice and a p- device, Although we have shown a polysilicon gate process, itis of historical significance to note that CMOS was otiginally imple- ‘mented with metal (aluminum) gates. This technology formed the basis for the majority of low power CMOS circuits implemented in the 1970s, The technology is robust and still in use in many areas. ‘As can be seen from Fig. 3.5, the mask lovels are not organized by component function, Rather they reflect the processing steps. + The first mask defines the p-well (or p-tub};n-chanoel transistors will be fabricated in this well. Feld oxide (FOX) is etched away to allow a deep diffusion (Fig. 3.6) +The next mask is called the “thin oxide" or “thinox"” mask, as, it defines where areas of thin axide are needed to implement tuansistor gates and allow implantation to form p- or n-type ffusions for transistor source/drain regions. The feld oxide areas are stched to the silicon surf is grown on these areas (Fig, 2.60). ther terms for this mask include active area, island, and mesa, In nMOS this would be the diffusion mask + Polysilicon gate definition is then completed, This involves cov- ering the surface with polysilicon and then etching the required patter {in this case an inverted "U"). As noted previously, the (Mos TECHNOLOGIES n ane| 7 eae ewes EES RIOD eae reseoanoesiare on se oF om nce un vag hearse fe =n . ne eT — are eae wet = Up / som pene VY p Leste : ‘cakes & _THINOXIDE. $ i A E ui avon « “ FIGURE 3.6. (Continued) be ee ce eee ee ip 2.60 Jt wel + A p-plus (p*) mask is then used to indicate those thin-oxide keh | nenumare dros (and pelyalicon) tha are to be implanted p*. Hence 8 o thin-oxide area exposed by the p-plus mask will become a p™ tte aifuson are (hig, 0d) the pps seen the mst, [june tt pt cs pvt sep wa cm jouress. then a p-channel transistor or p-iype wire may be constructed. I the peplus area isin the powell {not shown), then an ohmic contact to the p-well may be constructed. An ohmic contact isa HAPTER 3 GMOS PROCESSING TECHNOLOGY fone which Is only resistive in nature and is not rectifying (as fn the case of a diode) In other words, there is no junction (type and p-type silicon abutting). Current can flow in both Uirections in an ohmic contact. This type of mask is sometimes called the select mask as it selects those transistor regions that are to be p-type. + The next step usually uses the complement of the p-plus mask, although an extra mask is normelly not needed. The “ebsence” of a pplus region over a thin-oxide area indicates that the area will be an n° diffusion or n-thinox. n-thinox in the p-well {fines possible n-tansistors and wires (Fig. 36e). Ann diffusion Inthe n-substrate allows an ohmic contact to be made. Following this step, the surface of the chip is covered witha layer of SiO, Contact cuts are then defined. This involves etching any SiO; Gown to the contacted surlace (Fig. 3.6). These allow metal {next step} to contact diffusion regions or polysilicon regions. Motalization is then applied to the surface and selectively etched ig. 3.68) ‘As a final step (not shown, the wafer i passivated and openings to the bond pds ae etched to allow for wire bonding, Passivation protects the silicon surface against the ingress of contaminants that can modify cireuit behavior in deleterious ways, ‘Additional steps might include threshold adjust steps to sot the threshold voltages of the n- and p-devices, The cross-section of the finished p-well process is shown in Fig. 3.7e. The layout of the ‘porell CMOS transistors corresponding to this cross-section is il- Tostrated in Fig 3.7b. The corresponding schematic (for an invertet) {i shown in Fig. 3.7a, while a more representative cross-section showing realistic topology is depicted in Fig. 3.7d. From Fig, 3.7 itis evident that the n-type substrate accommodates p-channel devices, while the p-well accommodates n-channel devices ‘The p-well diffusion must be carried out with special care since wel doping concentration and penetration depth affect the threshold oltages as well as the breakdown voltages ofthe n-channel devices To achieve low threshold voltages (0.0V-1.0V), either deep well: diffusion or high well resistivity is required. Deep junctions require larger spacings between the n-type and p-type transistors due to Iateral diffusion, resulting in larger chip aress. High resistivity can acoontuate latch-up problems (Section 26). In order to achieve narow threshold voltage tolerances in a typical p-well process, the well Concentration is made about one order of magnitude higher than the substrate doping density, thereby causing the body effoct for n- ‘channel devices tobe higher then for p-channel transistors. In addition, ddve to this higher concentration, n-transistors suffer from excessive source/drain to p-well capacitance. In genera, the m-ransistors are inferior to those that could be built on a native substrate (n0 well) ‘Thus circuits involving n-zansistors will tend to be slower than, say, for atypical nMOS depletion load process: degredaton in circuit periormance may be expected in some logic structures (see Chapter 4) Since the shest resistance fora p-woll is inthe order of 1~10k0. per square, as @ measure against “latch-up.” the woll must be grounded in such a way as to minimize any voltage drop due to injected current in substrate that is collected by the p-well al FIGURE 37. Layout and ‘process cross-sections of ‘wanslators and Inverter In ‘well CMOS technology= — u fom FiguRe ieee | | on Ey 28, powell subsirate contacts In a p-well process, the n-type substrate may be connected to the positive supply (Voo) through shat are termed Vop substrate contact, while the well has to be connected to the negative supply {Wes} through Vs, substrate contacts. The interesting feature of the Veg contact Is that topside connection of substrate is used. This can be compared with nMOS, where backside connection is normally tused. Voo backside contact may be used but topside connection is preferred because it reduces parasitic resistances that could ca latch-up. Substrate connections that are formed by placing p regions in the p-well (Vos contacts) and 1” in the n-type substrate (Voo contacts) ae illustrated by Fig. 3.82. The corresponding layout is Shown in Fig, 3.8b. Other terminology for these contacts include “well contacts” for the Vig substrate connection or “body ties.” We will use the term "substrate contact” for both Ves and Vop contacts, {as this terminology can be commonly used for most bulk CMOS processes. It should be noted that these contacts are formed during the implants used for the p-channel and n-channel transistor {formation In curent fabrication processes the polysilicon is normally doped nt, The p” doping phase reduces the poly doping such that the polysilicon inside the p-plus regions have a higher sheet resistance than the polysilicon outside the p-plus region. The extent of this \ / 08) tone cone MUU Ait reduction may influence the quality of metal-poly contacts within p-plus regions. ‘To meet the growing need for higher pecking density, improve mens in latch-up, and independent threshold adjustment, a number of improved p-well CMOS processes have emerged during recent years. We will examine twa such processes in more detail: the ‘retrograde p-well CMOS” process developed by GE-Intersil, Inc. {[Combs1}, and the “CMOSC" process developed by Hewlett-Packard {HJLV83), These ae illustrated by Fig 3.9 and Fig. 310, respectively. FIGURE 39. GEntersi's “retrograde p-well™ process:7a CHAPTERS CMOS PROCESSING TECHNOLOGY FIGURE 3.10. Hewlet- Packare’s CMOSC process Spence ie SUSSS 44 —— ‘ier TELS LLL S { omemersnonne SYS, In the retrograde p-well process the wll is implanted with a high energy boron implant as opposed to a thermal dilfusion process. ‘As a result of this step and the fact that the implant is made after field oxide, the p-well impurities do not diffuse from their original implanted position, thus reducing the lateral diffusion ofthe wel. This enables reductions in the spacing between p-and n-ransistors Further edvantage of the retrograde process is that junction depth, 32 CMOS TECHNOLOGIES 78 uy seer VLULVLUL EL) boa rage sheet resistance, and threshold voltage are independent, allowing ‘separate adjustments to take place for optimizing the behavior of the CMOS devices. ‘A numberof the process steps for the CMOSC process are shown, F in Fig 2.10, A boron implant is used to define the p-ransistors and ‘phosphorus implant is used to define the n-transstrs.Improvernents In CMOSC processes have resulted in an extremely low standby FIGURE 3.10. (Continued) 3FIGURE 3.11. “Bird's See i i as = co TC 30 GHAPTER 8 GMOS PROCESSING TECHNOLOGY leakage curtent, primarily through cheracterization of the growth of field oxide, improved contol ofthe lateral difusion of the implanted sourez/drein junction, and inereased integrity ofthe gat oxide edge. Thinning of field oxide (Fig. 3.11) during contact etch can result in 41 nondestructive breakdown that increases leakage curens. Inhibiting this thinning effect, referred to as "bird's beak.” also provides sig- nificant improvement in the leakage mechanism. 3.2.2 The n-well process Until recently, p-well processes have been one of the most commonly available forms of CMOS. However, an advantage of the n-well process is that it can be fabricated on the same process line as Conventional nMOS. Therefore this process is ofton “retrofitted to ‘existing nMOS processes {Ohz00). “Typical n-well fabrication steps ar similar to @ pwvell process. ‘except that an n-well is used. The first masking step defines the rnwell regions. This is followed by a low dose phosphorous implant driven in by a high-temperature step for the formation of the n- ‘well ‘The well depth is optimized to ensure against p-substrae to ° diffusion breakdown, without compromising n-well to n~ sep- Eration. The next steps are to define the devices and other diffusions. to grow field oxide, contact cuts, and metallization. An n-well mask is used to define n-well regions, as opposed to a p-well mask in @ pewell process, An n-plus (n°) mask may be used to define the n- Channel transistors and Vyp contacts. Alternatively, we could use fa pplus mésk to define the p-channel transistors, as the masks usually are the complement of each other. “Although there are a numberof n-well CMOS processes becoming available, the novell process developed at the University of Califor at Berkeley is chosen a8 a good illustration of the detels of the fabrication steps. To illustrate this process, the process steps have ‘32 GMOS TECHNOLOGIES 81 ‘been reproduced {GrLN83]. These are couched in a Process Input Description Language. The commands in this language are as follows: + SUBSTRATE (*TYPE=(P, 1} TMPORITY=(1) ‘Specifies the substrate name, type, and impurity level + OXIDE THICKNESS = (1 Specifies oxide layer and thickness. + DEPOSTEZON (+) THICKNESS=(2 Specifies a layer and thickness of a deposited layer. (+) is followed by TYPE=( 1 IMPURTTY=C1 if itis silicon, + BICH DEPTH=C1 ‘Specifies a material and an etch depth. + DOPE TYPE=(P, 1] PEAK=(1 DEPTE BLock=1} Specifies parameters necessary to define a diffusion step, + NASK “POLARITY OF MASK> Specifies a resist layer and associated information 4} DELTA=I1 ‘The complete process input file is as follows (with abbreviations: (© IEEE 1983 ((GrL.82)) a. LEVEL + 2] suas StLicom TyPE=P IHF Initial oxidation 3. OXIDE Ox3 THICK=0.3 well definition 4. DEPO NERD TAIC $1 DEE 887 THICK=0.5 G1 mask R57 DRST nWiT POST 2] BECH DRST DEPTH=0.6 8) ETCH NTRD DEPT 8) ETCH 0 a, a2 OXIDE Ox@ THICI RICH NIRD DEPTE=O.G DOPE TYPE=N PEAK BLOCK=0.2 23. RICH Ox DepTu=0.7 26) OXIDE Ox3 THICK=0.4 'Set5 DEPTH=0.0 DELTA=h.SGHAPTER SONOS PROGESSING TECHNOLOGY ‘32 GMOS TECHNOLOGIES 0.2 All active area definition * Boron dope for p-channel source and drain 45. DEPO NTRD THICK=0.5 42. DEPO RST THICK=1.0 ie. DEPO RST THICK=0.5 43 WASK RST DRST AIIN MEGA 37) MASK RST DRST AA POST G2) eXcm DaSr DEPTH=}.2 5a. RICH DRST DEPTA=0.6 4S. Dope TYPE=P PEAK=ie22 DEPTH=0.0 DELTA 39 EXCH NTRD DEPTH=0.6 BLOCK=0.2 20. ETCH RST DEPTH-D.6 ey. BECH RST DEPTH=L.1 Feld dope for n-channel LPCVD oxide (Liquid Phase Chemical Vapor Deposition Oxide) au. pepo RST THICK=2.0 47. DEPO Of THICK=0.5 EB) MASK RST DEST MHWL POST 23, Contact definition 2a. Doe BLOch=0.2 Gg, DEPO RST THICK=2.0 as. ETCH B57 DEPT G4. MASK RST DRST WCC NEGA 3G. OXIDE Ox¢ THICK=0.7 $30 Hen pase peprans.2 So. etc wrap DEPTH=0.6 FE gi. grew $2. TCH “Threshold adjust dope i Metallization 28. Dope TYPE-P PEAK=1e20 DEPTH=0.0 DELT BLOCK=0.2 53. DEPO HETE THICK=1.0 $4. DEPO RST THICK=1.0 Rogrow gate oxide 35. ASE RST DEST MMe POST Se. ETCH 29. ETCH Ox DEPTH=O.1 57. ETCH $0. OxrDe OxS THICK=0.3 50. ETCH Poly gate definition Some ofthe abbreviations areas follows 34. DEeO POLY THICK=0-30 wien - Nitride 32. DEPO RST THECK=0.5 AST - Resist 35. mask RST DRS? Si POST HETL - Metal (Alumina) 35. Exch DRST DEPTH=0.6 NEGA ~ Negative 3g. ETCH POLY DEPTH=0.6 Post — Positive 3c. etch AST DEPTE=0.t AUWL ~ Novell mask AMA ~ Thin-oxide pack [Arsenic dope for n-channel source and drain ST - Polysilicon aask TIN — Npius aask cc ~ contact mask - EPO RST THICK=2.0 MASK RST DRST HII" POST 7 tm - Hetal wask [ETCH DRST DEPTH=3.2 : 7 Using the abbrevi on 2 pope BLOCK=0.2 Bic .0 DELTA=O.2 TYPE=N PEAR=Le22 DEPT RS? DEPTH}.2 processing may be tr tons and language definitions, the sequence in ‘ed out. For instance, steps 3136 deposit End etch the polysilicon layer, Stop 31 deposits .34 of polysilicon = a Re RLi ee i oll process snap-ahote ‘and layout for newel ine Verter © IEEE 1989, j, counssy 84 CHAPTER 3 CMOS PROCESSING TECHNOLOGY — FIGURE 2.12. Berkeley n- 32 GMOS TECHNOLOGIES 85 r | it cra A | a Fe sm =I : era 1 | 1 | ty Ld - a A —— FE comer , tay =e a = ” es ‘step ss FIGURE 3.12. (Continued) Step 32 deposits 5p of resist called RST. Stop 33 masks this resi with positive polysilicon mask, calling the exposed resist DST. Step 34 etches DEST to a dopth of 64. The exposed polysilicon is then etched to a depth of Sy by step 35. Finally resist RST is etched away, leaving the final polysilicon pattern. Fig. 3.12 shows anap-shots of the cross-section of part of the layout for a number Of steps during processing, The layout corresponding to the cross- section is shown in Fig 3.122. The cross-sections may be generated automatically fom this process file using the SIMPL-1 program [GrLN@3}. Fig. 3.12b shows the n° implant step. Fig. 3.12c shows the step required to define contact windows. Fig. 312d illustratesGHAPTER 3 CMOS PROCESSING TECHNOLOGY the wafer prior to metal definition, while Fig. 3.126 demonstrates the completed inverter in cross-section. Due to diferences in mobility of charge carriers the n-well process creates nonoptimum characteristics, such as high junction fapacitance and high body effect (in the same manner that the p> ‘well influences n-transistors). However, many emerging CMOS designs contain more n-channel than p-channel devices. so the overall effect ‘of poor piransitor performance may be minimized by careful ezeuit design. The n-well technology provides a distinct advantage here, ‘where optimum device characteristics are only required for the n- Channel transistors and not for the p-transistors. Thus a-channel devices may be used to form logic elements to provide speed and ‘density, while prirensistors could primarily serve as pullup devices. Fully nype 1/0 circuits may be also used to advantage 3.2.3. The twin-tub process ‘Twindtub CMOS technology provides the basis for separate optim~ ination of the p-type and n-type transistors. thus making it possible for threshold voltage, body effect, and the gain associated with n- and pedevices to be independently optimized (Parr80). Generally the stating material is either an n° or p~ substrate with a lightly ‘doped epitaxial or epi layer, which is used for protection against fatchup. The aim of epitaxy (which means "arranged upon”) is to row high purity silicon layers of controlled thickness with accurtely Feermined dopant concentrations distributed homogeneously throughout the layer. The electrical properties for this layer are ‘otormined by the dopant and its concentration in the silicon. "The process sequence, which is similat to the p-well process ‘apart from the tub formation where both p-well and n-well are utilized, entails the following steps: + tub formation + thin oxide etching + source and drain implantations + contact cut definition + metallization. Fig, 3.13 illustrates the steps involved in the ATST-Bell Lab- oratories twinub process. Since this process provides separately ‘Optimized wells, beter petformance n-ransistor (lower capecitance, tess body effect) may be constructed when compared with a con- ventional powell process. Similarly, the p-transistors may be optim feed. Note thatthe use of threshold adjust steps is included in this process, These masks are derived from the thinox and n-plus masks (wa terviron we. omarion “32 GMOS TECHNOLOGIES ee _—_ we FORMATION = Sn EP) tT J eoxDATON (= 10 THO FIGURE 3.13. ATAT Bell Laboratories’ twintub CMOS process steps a 2 a 2a es]cc L GURE 3:13. (Continued) {CHAPTER 3 OMOS PROCESSING TECHNOLOGY (POLYSHLCON PATTERNEG POLreucoN ws PATTERNED J I we os I a I Se T oven em L J cmt tn str tt of le pone bcos lee sueseeone ‘nesium aluminate spinel. Various masking and doping techniques arsine pn i ee ng gi “The cross-section of a typical twin-tub structure is shown in Fig. 3.14. The substrate contacts (both of which are required) are also included. 3.2.4 Silicon on insulator icon on insulator (SOI) CMOS processes have several potential rdvantages over the traditional CMOS technologies (MaSi64). These {include higher density, no latch-up problems, and lower parasitic devices. Unlike the mare conventional CMOS approaches, the extra steps in well formation do not exist inthis technology. "The steps used in typical SOL CMOS processes are: +A thin film (7-8 am) of very lightly-doped n-type Si is grown ‘an insulator. Sapphire ia commonly used insulator (Fig + An enisotropic etch is used to etch away the Si except where 2 diffusion area (n or p) will be needed. The etch must be ‘anisotropic since the thickness of the Si is much greater than the spacings desired between the Si “islands” (Fig 9.15b, 9.150) +The prislands are formed next by masking the n-islands with @ photoresist. A peype dopant, boron, for example, is then im- ‘32 CMOS TECHNOLOGIES 69 FIGURE 2.14. Twin process cross-section and fayout of an inverter90 CHAPTER 3 GMOS PROCESSING TECHNOLOGY « — it ono iim i=" FIGURE 8.15. Typlcalsitcon on Insultor (SO) process flow planted. It s masked by the photoresist, but forms p-slands st the unmasked islands. The p-islands will become the n-channel 32. GMOS TECHNOLOGIES a sour prosmronous devices (Fig. 3.18¢), +The prislands are then covered with a photoresist and an ‘type dopant, phosphorus, for example, is implanted to form the n-islands, The nislands will become the p-channel devices (Fig. 2.156), + A thin gate oxide (around 500-600 A) is grown overall of the Si structures, This is normally done by thermal oxidation. + A polysilicon film is deposited over the oxide. Often the po- Iysilicon is doped with phosphorus to raduce it resistivity (Fig, 3.151) + The polysilicon is then patterned by photomasking and is etched. ‘This defines the polysilicon laver inthe structure (Fig. 2.15) + The next step is to form the n-doped source and drain of the rnichannel devices in the p-slends. The n-islands are covered ‘with a photoresist and an n-type dopant, normally phosphorus, is implanted. The dopant will be blocked at the n-slands by the photoresist and it will be blocked from the gate region of eons ~ wea FIGURE 2.15. (Continued) 5 ca}‘HAPTER 8 CMOS PROCESSING TECHNOLOGY 32 CMOS TECHNOLOGIES 93 the prislands by the polysilicon. After this step the n-channel devices are complete (Fig. 3.18h) ‘The p-channel devices are formed next by masking the p-islands and implanting a p-type dopant such as boron. The polysilicon ver the gate of the avislands will block the dopant from the fete, thus forming the pechannel devices (Fig. 2.15 ti |A layer of phosphorus glass or some other insulator such as ver e silicon dioxide is then deposited over the entire structure. The flass is etched at contact eut locations. The metallization laver ee L fs formed next by evaporating aluminum over the entire surlace D fd etching it to leave ony the desired meta eres. The sluminurm fell ow through the contact cuts to make contact with the | diffusion or polysilicon regions (Fig. 3.15. LIZ REET ls ‘che rina Because the diffusion regions extend down to the insulating ven . substrate, only “sidewall” areas associated with source and drain diffusions contribute to the parasitic junction capacitance. Since To Fa InSGTRORE TON F= tapphite is anvextremely good insulator, leakage currents between transistors and substrate and adjacent devices are almost eliminated, In order to improve the yield, some processes use “preferential fetch" in which the island edges are tapered. Thus aluminum or poly runners can enter and leave the islands with a minimum step bight. This is contrasted to “Tully anisotropic etch” in which the ‘undercut is brought to zero as shown in Fig. 3.16. An “isotropic fetch” is also shown in the same diagram for comparison. The ad- iu vantages of SO! technology are: i ta FIGURE 3.16. Classifica Ta are oe tion of etching process + Due to the absence of wells, denser structures than bulk silicon fan be obtained. Also direct nto p connections may be made. bean eo ne cee aaa silicon techniques. Thus although SOI has the potential to be the & Low capacitances provide the basis of very fast circuits. ser Mase ee ansloeevit is he tha eames + No field-inversion problems exist (insulating substrate) i + Nelachup detain of and panier by nulating 3.25 CMOS process enhancements c ‘A number of enhancements may be added to the CMOS processes, primarily to increase routability of circuits, provide high quality AAs there is no conducting substrate, there are no body effect problems. Expuctors for anlog circuit and memories, of provide resistors 0 iu «Enhance relation tolerance capacitors for analog celts and » a However, on the negative side, due to absence of substrate diodes, ie entree ae the inputs ate somewhat more difcltt protect. As device gains oer e ee { are lower, I/O structures have to be larger. Single crystal sapphire double or tiple level matal iy or spinel substrates are considerably more expensive than silicon + double or triple level poly nd’ processing techniques tend to be less developed than bulk + combinations ofthe shoveFIGURE 2.17. Retractory ‘gates and interconnect © IEEE 1988 ({Chowea}) 94 CHAPTER 3 GMOS PROCESSING TECHNOLOGY Cy Uo PoLysucoNsIICIE nes oe a iio wowrorscy) Soa Hut ro = cpap roerenconsunce For example, a second level of good quality interconnect is almost ‘mandatory in modern processes. One mothod that requires no extra ‘mask levels isto reduce the polysilicon resistance by combining it with a refrctory metal. Four such approaches are illustrated in Fig. 3.17 {Chow83}. In Fig. 3.172, a silicide (eg. silicon and tantalum) is used as the gate material. Shoot resistances of the order of 1-2 0/0] may be obtained. This is celled the silicide gate approach. Silizides are mechanically strong and may be dry etched in plasma reactors. Tantalum silicide is stable throughout standard processing and hes the advantage that it may be retrofitted into existing process lines. Fig. 3.17b uses a sandwich of silicide upon polysilicon, which fs commonly called the polycide approach. A molybdenum gate, capped with silicide yields a metal/silicide sandwich or heart of ‘oly structure (Fig, 9.17c). Finally. the slicide/polysilicon approach may be extended to include the formation of source and drain regions T using the silicide. This is called the salicide process (Fig. 9.174 ‘The effect of all ofthese processes isto reduce the "second laver Interconnect resistance. allowing the gate material to be used as a reasonable long distance interconnect. This is achieved by minimum perturbation of an existing process ‘A second approach is to just use a second layer of motal as discussed above. Asa rule, second level metal layers have a coarser pitch as the topology of the silicon surface is more varied. Usually, Contacting the second layer metal to fist layer metal Is achieved by a via, as shown in Fig. 3.18 If further contact to diffusion or polysilicon is required. « separation between the via and contact ‘cut is usually requited (although not in advanced processes). This requires a fist level metal tab to bridge betwoon metal 2 and the lower level conductor. Itis important to realize that in contemporary processes frst level metal must be involved in any contact to un- ‘derlying ares. Probebly as processes mature, this rule wil be relaxed, ‘A number of contact geometries are shown in Fig. 3.19 on page 86. Processes may require metal borders around the via on both levels ‘of motal, on second level metal only, or no borders on either level, {in which case the via normally overlaps the intersectior. ofthe two, layer. Fig. 3.19b shows an example ofthe second instance. Aggressive processes allow one to stack vias on top of contacts, as shown in Fig. 3.19. Consistent with the relative large thickness ofthe intr. ‘mediate isolation layer, the vias may be larger than contact cuts fand second layer metal needs to be thicker and requires larger via ‘overlap, The process steps for a two metal process are briefly as, follows: + The oxide below the first meal layer is deposited by atmospheric, ‘chemical vapor deposition (CVD). + The second oxide layer between the two metal layers is applied. ine similar manner 32 CMOS TECHNOLOGIES 95 FIGURE 3.18. Cross-see- tion of a second metal via = A 3 =a pect) 22)i | JOURE 219. Second total via geometries i & GHAPTER® CMOS PROCESSING TECHNOLOGY + Depending on the process, removal of the oxide is accomplished tusing a plasina etcher designed to have a high rate of vertical {on bombardment. This allows fat and uniform etch rates. The structure ofa via etched using such a method is shown in Fig 3.18. Similarly, the bulk of the process steps for «double poly process are common to the processes described 30 far. With polysilicon, the oxide may be grown on top ofthe polysilicon to serve as isolation between polysilicon layers. Recent innovations in research processes have included 3D (CMOS structures to reduce area and increase performance of circuits by using the vertical dimension in a silicon wafer (Cibbso] {ADYY89} [SIMS] Fig. 3.20a illustrates a cross-section of one particular 3- 1D SOI CMOS process [KSIM3). with an accompanying layout for an inverter shown in Fig. 2.20b. Trench isolation (Fig. 3.21a) improves Tatch-up and n to p spacing of transistors by including deep oxide 32 GMOS TECHNOLOGIES 97 filled trenches between n- and p-transistors (IEDMa3). Fig. 3.21b shows a cross-section from an advanced twin-tub process developed by Tektronix that has silicide gates, trench isolation, and second Tevel metal [YMKP83) FIGURE 3.20. 30 cwos process cross-section and Inout of invertor © IEEE 1965 (KSIM 83)36 CHAPTER 3 CMOS PROCESSING TECHNOLOGY =— | FIGURE 3.21. Trench Isolation 2) ideal cross-section 6) representative process (Fektronix) © IEEE 1963 (YMKPE3]) 3.3 Layout design rules Layout rules, also referred to as design rules, can be considered os {prescription for preparing the photomasks that are used in the fabricetion of integrated circuits. The rules provide a necessary com ‘munication link between circuit designer and process engineer during the manufacturing phase, The main objective associated with the layout rules isto obtain the circuit with optimum yield in as small ‘sgeomelry as possible without compromising reliability of the circuit “a3 LAYOUT DESIGN RULES 99 In general. design rules represent the best possible compromise between performance and yield. The more consercatve the rules are, the more likely i is thatthe circuit will function. However, the more aggressive the rules are. the greater the probability of Improvements in circuit performance. This improvement may be at the expense of yield Design rules specify tothe designer certain geometric constraints on the levout artvork so thatthe pattems on the processed wafer till preserve the topology and geometry ofthe designs. I is important to note that design rules do. not represent some hard boundary between correct and incorrect fabrication. Rather. they represent @ tolerance that ensures verv high probebiity of caret fabrication and subsequent operation. For example. one may find that a layout that violates design rules may stil function correctly and vice versa Nevertheless, any significant or fequent departure fom design rules will seriously prejudice the success ofa design. ‘Two sets of design rule constraints in a process relate to line ‘widths and interlaver registration. Ifthe line widths are made too Seall tis possible forthe line to become discontinuous. On the ther hand, ifthe wires are placed too close to one another itis possible for them fo merge together: thai, shorts can occur between {wo independent circuit nets. Furthermore. the spacing between two independent layers may be affected bythe vertical topology of a process. “The design rules primarily adéress two issues: 1 the geometrical reproduction of fetures that can be reproduced by the mask masking and lithographical process. and 2) the interactions between different layers. ‘There are several approaches that can be taken in describing the design rules. These include ‘micron’ rules stated at some micron resolution, alphe (a) and beta (3) rules, and lambda (\)-based rules.” Micron design rules are usvally given as alist of minimum feature sizes and spacings for all the masks required in a given process. For example, the minimum thinox width might be specified as 4 jum. This is the normal style for industry. tn @ and rules the basic feature size is defined in terms of 8. while the minimum grid size that is needed is deseribed by a «and 8 may be related bya constant factor, The lambda-basod design rules popularized by Mead and Conway (MeCo80] ate baséd on a single parameter A, which char- s the linea festure — the Fesofution of the completo waler Implementation process — and permite Bist order scaling (which rarely applies). AS @ rile they can be expressed on a single page. The vader Toul cone thine of and wth dn Chapt 2 forthe air gin an channel lengihedlton parses. especialy A a3a LAYOUT DESIGN ULES 104 TABLE 32._JPL/Mead Conway layer representation for p-well CMOS process PL ee — (30 GHAPTER SENOS PROCESSING TECHNOLOGY TABLE 3.1, Derivation of lambda-based rules from micron res ‘Minimum Al width 45 am a” Orerplaee = = © Aluninem ‘Minimum Al spacing AS wm en L The layers for typical CMOS processes are represented in various figures in terms of: ‘The derivation of some A rules based on « representative set of 4 mnicroa rules is illustated in Table 3.1 ron Tul be noted that the degradation in circuit performance se wall othe expected increase in silicon area could rake the + a color scheme proposed by JPL" 4 modified color scheme to differentiate between nMOS and OS structures (as used on the cover of this tex) 2 ede unutate for commercial circuits and even experiment) ap eroeet Wabi text, we will use the A rules to illustrate principles sees symbolic techniques as described in Chapter 7 heres By ene vy the actual inion rales cannot be used and it is Ne 0 tessa text to encourage tis practice. The objective in this txt aim ot trate approaches that completely hide the design rules from the designer 3.3.1. _Layer representations ‘The advances in the CMOS processes ae generally complex end sa gvat inhibit the visualization of all the mask levels thet ae sar dhe actual fabrication process. Novertheless the design process tae i Uetacted to a manageable number of conceptual layout cate at represent the physical features one observes in the fxs ere natfer At a sufficiently high conceptual evel all CMOS processes use the following features: + two diffrent substrates 1 oped regions of both p- and aArensistor forming material + transistor gate electrodes + interconnection paths + interlayer contacts, + stipple patterns + line styles + or a mixture of these ‘Some of these representations are shown in Table 3.2 and Table Somber diagrams art presented, a legend will be used to indicate TABLE 3.3. Alternate layor representations for p-well CMOS process TAYER ‘ALTERNATE COLOR ‘ar Cone, See Thin oxide" Red ro tPoly Green oe ser Purple cs Metal Ten ow SMetalz Dark blue w 2 Contct Black c Oveslas hte stipptes c See amr acer aon. ano pO Ta onaines borin, Calflora Inte a Technology, Paden702 CHAPTER 8 CMOS PROCESSING TECHNOLOGY 3 LAYOUT DESIGN RULES 103 TABLE 34, First character representation of CIF for pro- TABLE 35. Lambde-based layout rules cess description E No__MASK FEATURE DENSON ‘PROCESS (CIF CHARACTER ‘A Minimum thinox width 2k Q 4 ae mv Th aa TABLE 3.7. Double metal rules — micron based (suggested lambda rules) AYER WIDTH SPACING Tait Tam amon Metalz Sam (9) Sum (9) Via 2 mn 3 ym (2 x 2A) 3H en) cut 3 yum x 9 pam (2 x 20) ane) Gutvia space = Sum (2, TABLE 3.8. Metal, metal2, via constructs LAYER ‘SUE, ee Tear Tua e Samia ea Via Byam x 3m [2A * 2) Matz 7am x7 nm [Sk <5) 3.3.4 Double metal design rules ‘Tables 3.7 and 3.8 show some typical rules relating second layer ‘metal to first layer metal fr atypical two laver metal process. The increase in width end separation of second level metal ensure against ‘broken conductors oF shoris between adjoining wires due to the vertical topology. 3.3.5 Design rules — summary {In commercial designs. lambda rules are rarely suficent to desccibe high performance circuits, Some additional rule that might be present fn some processes are as follows: + Extension of polysilicon in the direction that metal wires exit a contact + Differing p- and nvtransistor gate lengths. + Differing gate poly extensions depending on the device length cof the device construction While all of these rules can be worstcased, very inefficient designs result. A better approach is to implement systems that synthesize the correct geometry from an intermediate form. Therefore, symbolic. styles of design appear to provide a solution for creating generic, GMOS circus that can be implemented with a wide range of fab- Heation processes, This is the underlving theme in this text and ‘will be expanded upon in Chapter 7. For the time being we will txamine some ways of capturing the key rules of a process. 3.4 Process parameterization AAs automated tools became more available, the necessity for an individual designer to know detailed design rules becomes less important. However, the tool designer must have a form in which the design rules for a process can be unambiguously represented. 34 PROCESS PARAMETERIZATION 13Tid CHAPTER'S CMOS PROCESSING TECHNOLOGY If rules are to be communicated between tools then a data format has to be designed to provide the appropriate interface. We will examine some of these ideas in this section. The main idea is to {entify structures of interest and demonstrate algorithms that might be used to construct these. Spacing of these structures from other structures is achieved by applying the normal spacing rules 3.4.1 Abstract layers ‘An important concept in the synthesis (and analysis) process is the Gefinition of abstract layers. For instance, n-difusion in a p-well process consists of the thin oxide mask “anded” with the p-well mask without p-plus present, while transistor p-diffusion consists ‘of thin oxide “anded” with the p-plus mask in the absence of the powell. We might state this for a p-well process in some pseudo Tenguage represented by the following: NDIEF = W_DIFFOSION = PLWELL AND THIWOK AND NOT PoPLOS pDIFF =; 2LFPOSTON = PLPLUS AND THINOX AND NOT POMEL ACTIVE = ACTIVE_TRANSISTORAREA = TEINOX AND POLYSILICON ‘aook = TDD. DIFFUSION ‘AND NOT P_PLUS ysse = VSS-P-DIPPUSION = THINOX AND P_PLUS AND PELL THINOX AND NOT P_WELL 3.4.2 Spacing rules Using the abstract layers and regularly defined layers the spacing of layers may be specified. For instance, the following rules are according to Table 3.4 np_p_sP = NDIFF 70 PDIFF SPACING = O+LAMBDA NDLNDSP = NDIPE 70 NDIFF SPACING = 2+LAMBDA PDLPD_SP = PDIPF 70 PDIFP SPACING = 2+LAMBDA COuco_SP = CONTACT TO CONTACT SPACING = 2+LANBDR COLGP_SP = CONTACT TO GATE POLT SPACING B4LRMBDA However, the following rules are also needed: ND_vP_SP = NDIPF 10 VSSP SPACING = 2+LANBDA PDLYNSP = PDIPF TO VDDN SPACING = 2LANBDA NDUVNSP = NDIPP 10 VDDN SPACING = S*LANBDR PDL¥PLSP = PDIPP 10 VSSP SPACING = S*LANBDA eee ‘34 PROCESS PARAMETERIZATION 115 9.4.3 Construction rules Construction rules are used to build structures. The first level of these are the minimum width rules. For exampl THwID cO_wID PO_RID MININON TAINOX WIDTH ~ 2°LaNBDA RINIHON CONTACT WIDTH = 2+LAMBDA MINIMUM POLYSILICON WIDTH = 2*LANBDA In addition, extension rules may also be specified GP-LEXT = EXTENSION GATE_POLT OVER ACTIVE = BeLAMBDA PO_COLEXT = EXTENSION POLYSILICON OER CONTACT = LAMBDA ‘THLGP_EXT = EXTENSION THINOT OVER GATE_POLY = ‘2*CAMBDE WB_TH_EXT = EXTENSION PTUB OVER THTHOX S*LEMBDA pp_TH2XT = EXTENSION PPLUS OVER THTNOX 2eCAMBDA ‘THCOLEXT = EXTENSION TATNOX OVER CONTACT = TEARBDA Using these parameters, the following is an example of the pseudo code that may be used to build a minimum length transistor of variable width: type is transistor type x7 48 transistor position w Is transistor wigeh build transistor(typesx+y/¥) t 1 = PowiD + 2eTH_cP_exT build _cectangle(THINOX, x-1/2: y-¥/2, ee1/2, yow/2), Le(type = N_TRANSTSTOR) w+ esT0Bta_ex? 1+ geron t_ext beild_rectangle(PTUB, x-1/2, y-¥p/2, xel/e, yexp/2) } else ( wp =v + 2PP_TH_ExT Lis. + 2=pP TH EXT = 9 i ]Line 4 emuasse sme rset HAPTER @ CMOS PROGESSING TECHNOLOGY boitg_rectangle(PPLUS, t-1/2, J-4P/2r Lz, pep7e) ) ep = - 2*GPALEXT 1s eo_wroTs paildcrectangle(POLt, -1/2, yup/2, X-1/2) yewp/2) 1 ent | cee | “The resulting unconnected transistor is shown in Fig. 3.28a. The addition of some parameterized contacts completes the transistor. ‘A larger transistor is shown with multiple souzco/drain contacts. ‘The poly pitch and the source/drain contact pitch are illustrated. {An alternative transistor structure is shown along with the associated dimensions in Fig. 3.28. This has a reduced poly pitch et the expense of ¢ reduced number of source/drain contacts. 3.5 _Summary ‘This chapter has covered some of the more common CMOS tech- nologies that are in current se. We have presented a set of lambda files for a pewell process and an SOI process. Chapter 7 outlines Symbolic layout techniques that allow the CMOS circuit designer to construc circuits without direct reference to such rules, Ofcourse the design automation programmer still has to be cognizant of geo- metric design rules. The last section inthis chapter dealt with some more obvious ways of parameterizing layout software. 35 SUMMARY 117 FIGURE 3.28 (Continued)ie GHAPTER 3 GMOS PROCESSING TECHNOLOGY 3.6 Exercises 4.2 An newell process has thin oxide, r-well and n-plus mask layers, in addition to the other regular layers. Draw the mask combi tations to obtain an transistor contact, a p-ransistor contact 2 Voo contact, and a Vss contact. 3.2 Repeat Exercise 3.1 for a twin-tub process with thin oxide. p= well, and n-plus mask layers. 133 Design the layout for an SOL inverter and transmission gate 2- input multiplexer using the design rules included in Fig. 3.27, ‘4 CMOS inverter in p-vell technology 134 Writea program to generate the n- and peransistors to alter the thot can individually size threshold of the gate. eel CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION bes) 3ai 20 t GHAPTER 4 GIRGUIT CHARACTERIZATION ANO PERFORMANCE ESTIMATION 4.1 _ Introduction {In previous chapters we established that an MOS structure is created by superimposing a numberof layers of conducting, insulting, and transistor forming materials. It was further demonstrated that in 2 Conventional silicon gate process an MOS device requires a gate forming fegion and a source/drain forming region, which consists of difusion, polysilicon, and metal layers separated by insulating fayers. Each layer has both a resistance and capacitance that are fandamental components in estimating the performance ofa circuit cr system, They also have inductance characteristics that we will ‘assume to bo neplisible ‘In this section we ae primarily concerned with the development of simple models that wail asist us in the understending of system behavior and will provide the basis whreby systems performance, in terms of signal delays and power dissipation, can be estimated. “The issues to be considered in this section are + resistance and capacitance calculations + delay estimations + determination of conductor size for power and clock distribution + power consumption + charge storage mechanism + effects of scaling 4,2 Resistance estimation Spade 2 ()(t) ame ws tty eer 1 = conductor length w = conductor width. ‘Tis expression may be rewritten 2s na(!) een ws “2 RESISTANCE ESTIMATION snl Sen + 8 At Zt neni) on (f ‘where R, isthe sheet resistance having units of obm/square. Thus to obtain the resistance of a layer one would simply multiply the sheet resistance R, by the ratio ofthe length to width of the conductor. For example, the resistances of the two shapes shown in Fig. 4.1 are equivalent, Table 4.1 shows typical sheet resistances that can be expected in 3 um to § um MOS processes. Note that for metal having a given thickness ¢, the resistivity is known. while for poly ‘and diffusion the resistivities are significantly influenced by the Concentration density of the impurities that have been introduced Into the conducting regions during implantation. This means that ‘the process parameters have to be known to accurately estimate these quantities “although the voltage-current characteristic of an MOS transistor 4s generally nonlinear, itis sometimes usoful to approximate its behavior in terms ofa “channel” resistance to estimate performance. From Chapter 2, Eq (2.0), one may express the channel resistance the linear region) R. by R 43) TABLE 4.1._ Typical sheet resistances for conductors SHEET RESISTANCE OHM/SQ, Material Min Typical Nx Toa SSC«C Siliides 2 3 5 Ditfusion (a+ and p+) wo Pn 0 Potyilcon 5 50 100 FIGURE 4.1. Determin tion af layer resistance: 12TABLE 42. Resis- tance of test shapes RESIS. SHAPE RATIO TANCE an x A 88 eee erate) Bois 288 B, 2 (26 Boo 827s c oi 2 e225 rn) G4 28s Dot BR Dos 28 D2 8 Dee ae eet Bis 14s e238 Boo3 (23 BO 426s Jaa HAPTER 4 CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION ke [oe). = val aay For both the n-channel and p-channel devices, k may take @ value ethan the Tange 5.000 to 30,000 1/sq.. Eq (24) demonstrates the epondence of channel resistance on the surface mobility 4 ofthe serenity caters (i.e. electrons in n-device and holes in p-device) Since the mobility is elzo a function of temperature the channel Feotstance and therefore switching time parameters, as well as power ‘esipation, change with temperature variations. The increase in the creel eesistance may be approximated by +0.25 percent per °C for an increase in temperature above 25°C. 4.2.1 Resistance of nonrectangular regions Many times during the course of « layout nonrectangular shapes Mie used (for instance, the corners of wires). The resistance of these ‘Shapes requires more elaborate calculation than that for simple {angular regions. One method of calculating the resistance sto break the Shape in question into simple regions, for which th resistance {ay be calculated (HoDu83). Fig. 4.2a summarizes the resistance ‘Bre number of commonly encountered shapes. Fig. 4.2b shows some ‘Shapes that ae commonly encountered in practice, Table 4.2 presents the results ofa study (HoDua3] to calculate the resistancos of these Shapes for diferent dimension ratios. This shape information may ‘iso be used to estimate the effective w/1 of odd shaped transistors {GiB082], A fow precautions need to be taken, however, especially Concerning which side of «shape is the source or drain. The values Shown in Table 4.2 best approximate the linear region of operation Stan MOS transistor. Note that contacts and vas also havea resistance Ghsociated with them. As contacts are reduced in size the associated, ‘sistance Increases. Typical values for processes currently in use range from .250 to 1000 4.3 Capacitance estimation 4.3 Capacitance estimation ___ “The dynamic response (eg. switching speed) of MOS systems are very much dependent on the parasitic capacitances associated with The MOS deviee and interconnection capacitances that ere formed by metal, poly, and diffusion wire (often called “runners” in concert Pith tanaistor and conductor resistances. The total load capacitance fon the output of an MOS gate is the sum of 43 cH) » + gate capacitance (of other inputs connected tothe output of the sate) «+ diffusion capacitance (of the drain regions connected to the output) {+ routing capacitance (of connections between the output and ‘other inputs) . ‘Understanding the source of parasitic loads and their variations is ‘esontal in the design process, where system performance in terms of the speed of the system form part of the design specification. ‘We will frst exemine the charecteristics of an MOS capacitor Following this, the MOS transistor gate capacitance, source/drein, capacitance, end routing capacitance will be estimated, TANCE ESTIMATION 123 FIGURE 42. Resistance fof nonrectangular shapes: {IEEE 1989 ((HoDueS)) 3 oe| 724 CHAPTER 4 CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION L 4.3.1 MOS capacitor characteristics “The capacitance voltage characteristics of an MOS structure depend fon the state of the semiconductor surface. Depending on the gate woltage the surface may be in: Referring to the pesubstrate structure shown in Fig, 43, an accu malation layer is formed when Vi, < 0 (Vg > Ofor nsubsteatel. The negative charge oa the gate atracts holes foward the silicon surtace. When an accumulation layer is present the MOS structure behaves like a parallel plate capacitor. The gate conductor forms one plate of the capacitor. The high concentration of holes in a p-subsirate Inedevice) forms the second plate of a capacitor. Since the accu ‘mulation layer is directly connected to the substrate. the gate ca pecitance may be approximated by A 6) where A = area of gate uo, * dielecteie constant (or relative permitivity of SiO, taken 25 3.) ‘When a small positive voltage is applied to an n-device gate with respect to the substrate, a depletion layer is formed in the Se | @ esueernare LC cuRE 4.3. MOS capacitance (a) physical structure and (b) variation a8 function of Ye “43. CAPACITANCE ESTIMATION | p-substrate directly under the gate. The positive gate voltage repels Roles leaving e negatively charged region depleted of carters. A corresponding effect occurs in an n-substrate device for a small negative gate voltage ‘Since the magnitude of the charge density per unit area in the surface depletion region is dependent on the doping concentration {N), electronic charge (ql. and the depth of the surface depletion region {dl}, increasing the gate to substrate voltage also increases Carp. the depletion capacitance. is given by A rr) where 4 ‘ey = dielecteic constant of silicon taken as 12 lepletion layer depth ‘Thus as the depth of the depletion region increases, the capacitance from gate to substrate will dcrease. The total capacitance from gate to substrate under depletion conditions can be regarded as that being due tothe gate oxide capacitance. C, in series with Cai specifically an As the gate voltage is further increased, minority carriers (electrons {or the p-substrate) are attracted toward the surface. Ths effectively inverts the silicon at the surface and creates en n-type channel, Surface inversion yields a celaively high conductivity layer under the gst, which restorer the low Froquency capacitance to C,. Because of the limited supply of cazters (electrons) to the inversion layer. the surface charge is not able to track fast moving gate voltages Hence the dynamic capacitance remains the same as for the maximum depletion situation Co low frequency (<1ooHt2) = os dynamic C+ Ca Fig. 4.9b summarizes dynamic gate capecitance asa function of gate voltage. 4.3.2 MOS device capacitances So fer we have considered the MOS gate in isolation. Fig, 4.4 on ‘ge 126 i a diagrammatic representation ofthe parasitic capacitances ‘fan MOS transistor. In this model and in the subsequent analysis the overlap of the gate over the drain and source is assumed to beJRE CHAPTER 4 GIROUTT CHARACTERIZATION AND PERFORMANCE ESTIMATION FIGURE 44. Represen {ation of parasitic capect: tance for an MOS transistor FIGURE 45. Circuit sym- bole for parasitic capacitance ‘zero, a simplification that is valid to a fist order in self-ligned silicon gate processes cin fig. Jct the following capacttive components have been identified: yu Cys = gate to channel capacitances, which ae lumped SP source end drain regions of channel. respectively. ‘source and drain diffusion capacitances to bulk {or substrate) sate to bulk capacitance. CoCo itis now possible to view the model in terms of circuit symbol ‘Tus is ilustrated in Fig. 45. The total gate capacitance C, of an MOS transistor Is given by C= Got Co + Ow aa) ‘the behavior of the gate capacitance of an MOS device can be Gaplained in terms of the following simple models in the the regions of op 2 CAPACITANCE ESTIMATION ‘TABLE 4.3. Approximation of intrinsic MOS gate capacitance CAPACITANCE PARAMETER of near Saraon I ao oo oe = ° o G a oa ° 0 C= Gat Get Cu 12) 1 Off region, where V,, < Vj. When the MOS device is “OFF” there isno channel, and hence Cy = Cys = 0. Cjcan be modeled fs the series combination of the two capacitors (C, end Ci), shown in Fig. 43. {2 Linear region, where Vp ~ V; >» Va-In this region, the depletion layer depth remains relatively constant. Cy, therefore, remains constant. As a result of the formation of the channel, gate to Channel capacitances C, and Cy now become significant. These Cepecitances are dependent an gate voltage. Their values can be conservatively estimated 23 ee) Cd Sent th ye sit Sasa Se eS mae ite) near Se te eter Pe ‘on page 126, is approximately equal to the intrinsic “gateoxide” Capacitance for all values of gate voltage. The only region where Cu = Co 1 ‘|u | AGURE 46. Total gate ‘Capacttanes as a funetion ot Ve oes ‘ut of an MOS transistor JF contin maton this does not hold is around the threshold voltage of the transistor {Since trensistors in digtal circuits switch through this region rapidly, we can conservatively approximate C, = C,. "Another way of stating this approximation Is C= Cu (40) where Gy: is inthe “thin oxide” capacitance per unt area given by Cog = S88 (4.1 is (an) With a thin-oxide thickness in the order of 500-1000 A. and the relative permittivity for SiO, approximated as 4, the value of 443.054. 10 {G00 ~ 1000) 10 = (@ ~ 4) 210 pF Yum [Approximation of the gate capacitance may now be undertaken by ‘Sumply taking the above value and multiplying it by the gate are. For exemple, the input (or gate) capacitance for e typical MOS transistor shown in Fig. 4.7, with A= 2 am and t= 1000 A, is C= 35+ 10" # 6x pF nape We will refer to this transistor as “unit transistor" — a transistor that can be conveniently connected to metal at source and drain Tis the same width as a metal-diffusion contact. Shallow n° and p” diffusions form the source and drain terminals fof n-and p-channel devices. Diffusion region ae also used as wites. ‘AIl diffusion regions have a capacitance to substrate that depends on the voltage between the diffusion regions and substrate (or well) {5 well a5 on the effective area of the depletion region separating diffusion and substrate (or well). The diffusion capacitance C, is proportional to the total diffusion to substrate junction area. As Shown in Fig. 48, this is a function of “base” area end also of the he Pos T od + | ote osm | ot He sé A oT * th capnrance REPRESEITAON (9 ownerace woos. “463 CAPACITANCE ESTIMATION 129 FIGURE 48, Area and pe- ‘ipheral components of at- fusion eapactance490 CHAPTER 4 CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION area of the “sidewall” periphery. The latter occurs because the iffusion region has a finite depth. Sidewall capacitance can be characterized (assuming constant depth diffusion) by a periphery Capacitance per unit length. The model generally used is shown in Fig. 4.8c, Total C, can be represented by Gy = Ga* (ab) + Gy # (20 + 2b). (42) where Gq = junction capacitance per sq.m Gy = periphery capacitance per um (0 = width of difusion region bb = extent of diffusion region Note that the capacitance contributed by the sidewall facing the chennel will be reduced somewhat by the presence of the channel ‘depletion region ‘An obvious factor that emerges from Eq. (4.12) is that as the diffusion area is reduced (through scaling, to be discussed later) the tolative contribution of the peripheral capacitance becomes more important. Typical values for diffusion capacitances are shown in Table 44 for both a- and p-channel devices. For example, the drain diffusion capacitance of an n-channel device with the dimensions shawn in Fig. 4.7 may be approximated in the following manner: 5 Ca = Ca¥ ab) + Gy (2a + 20) 1+ 10°* (10 8) + 96 10"* (20 + 16) = 40 fF. These simple capacitance calculations assume zero DC bias across the junction. Sixce the thickness of depletion layer depends on the voltage across the junction, both Cy and C, are functions of junction voltage VA general expression that describes the junction capacitance ea(-2)7 (ass we Vein vag xsi TABLE 4.4. Typical uitfusion capacitance values. ‘DEVICE (OR WIRE) ‘pDEVICE (OR WIRE) 5 Te pea Tam & 9.2 10-*pF/m 4210" prim “3 CAPACITANCE ESTIMATION rmoncconcrnee zac 4, L t ; o 4, = built-in junction potential ~ 0.8 volts zero bias capacitance: V ‘and m is a constant. which depends onthe distribution of impurities near the junction. and has a value of the order of 0.3 t0 03. 43.4 Routing capacitance Routing capacitances between metal and poly layers and the substrate 4 canbe approximated using parallel pte model (C= $A). here ‘Ais area of the parallel plate capacitor, tis the insulator thickness ‘and ¢ is the dielectric constant ofthe insulating material between the plates. The paralle-plate approximation, however, ignores fringing fields. The effect of fringing fields Is to increase the effective area ofthe plates. Consequentv, poly and metal ines will actualy have f higher capacitance (up to twice as large) than that predicted by the model, Interlaver capacitance such as metal-poly capacitance is also enhanced by fringing. Fig, 49 illustrates this effec. As line widths are scaled. the width () and heights of wires tend to reduce less than their separations (I). Accordingly, this fringing effect in creases in importance. For current processes, a factor of 1-5-3 should be used. Methods for more accurately computing the finging factor can be found in [RuBr73}. ‘Another factor. which should be taken into account for small ‘geometries when using the parallel plate model is that @ drasen Shape (om mask) will act be the same as the actual physical shape produced on silicon. This effect, shown in Fig. 4.10 on page 132, fs most pronounced for diffusion regions and the extent may be determined analytically or empirically through experimentation, 4.3.5 Distributed RC effects ‘The propagation of a signal along a wire depends on many factors, including the distributed resistance and capacitance of the wire. the impedance of the driving source, and the load impedance, For FIGURE 49. Effect of fringing feiss on capacta atiqURE 410. eect of | Toceesing on crown Lsomey by | JGURE 4.11. Represen- [Lion of tng wie tn terms ‘of elstrbuted RC sections very long wires propagation delays caused by distributed resistance Capacitance (RC) ia the wiring layer tend to dominate. This trans- mmission line effect is particularly severe in poly wires because of the relatively high resistance ofthis layer. A long sre can be rep= resented in terms of several RC sections, as shown in Fig. 4.11. “The response at node V, with respect to time is then given by wy - oFie dan w aaa Wir Mi) wR [As the numberof sections in the network becomes large (end the Sections become small) the above expression reduces to the di- ferential form: way at” oe we (as) here x= distance from input = resistance per unit length spacitance per unit length. “42 CAPACITANCE ESTIMATION “The form of this relation is that ofthe well known diffusion equation ‘The solution for the propagation of a voltage step along the wire shows that the propagation time t, over a wie of length x is eke, (ans) where kis a constant. Altematively, a discrete analysis of the circult shown in Fig. 411 yields an approximate signal delay of RC t (aan) where n= number af sections. ‘As n becomes very large (Le, the individual sections become very small) this reduces to (a where f= resistance por unit length capacitance per unit length 1 = length ofthe wire ‘The I term in Eq. (4.18) shows that signal delay will be totally dominated by this RC effect for very long signal paths. In order to ‘optimize speed ina long poly line, one possible stategy isto segment the line into several sections and insert buffers within these sections. Fig. 4.12 shows a poly bus of length 2 mm that has been divided into two 1 mm sections. Forr = 12 0/amand.¢ = 4 x 10~* pf/um. Bq. (4.18) yields t= 24x10, ‘Assuming thatthe delay associated withthe buffer is ry, the total olay for this bus is 2.4 20°" x (1000}° + rp 2a ne + My a “TL wee T) tT og fy FIGURE 4.12. Segmen- {ation of polysiican tine{G4 CHAPTER 4 CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION FIGURE 4.13. Simple ‘model for AC delay ‘aleulation ‘This may be contrasted tothe situation in which the buer is missing, which yields t= 9825. “Thus by keeping 7yy small, significant gain can be obtained through appropriately segmenting the bus. yyy does. in fect depend on the feslstance of the first section of the bus and on the capscitance of the second section of the bus. The relative importance ofthese two terms depends on other circuit parameters such as final load ca- pacitance, (some situations, it may be preferable to use a wide poly wire to reduce overall series resistance at the expense of capacitance ‘When the RC product of a long line is high, it might not be possible to compensate by simply adding drivers. This is where Technologies such as double metal layer prove useful. Here, the econd real layer may be arranged torun in place of the polysilicon line Po. + sill used for local gate connections. Another approach that is also effective in reducing the influence of AC effects is to lie silicides (tantalum, molybdenum) with sheet resistances in the ‘order of 2-4 ohm/sq. This approach provides considerable im- provement in the AC delay associated witha line and is argued to bes elicctive as a second meal layer while maintaining compatibility with a single metal process. ‘A imodel forthe distributed RC delay. which takes driver and receiver loading into account, is shown in Fig, 4.19. Ry is the output resistance of the driver. Cis the receiver imput capacitance. R, and . are the tolal lumped resistance and capacitance of the line. is the RC delay calculated using Eq. (4.18). Such e model yields results that are very economical in terms of computation and, more im- pportantly, are accurate enough for most puxposes. The concept of sing RC time constants for delay estimations is based upon the tssumption thet the time taken for a signal to reach 63 percent of its final value approximates the switching point of an inverter 43.6 Capacitance design guide ‘As a guide to the design process and, in particalar, tothe choice 2 layers, Table 4.5 fs provided. I shows a range of capacitance falues {no fringing) for 8 typeal 4 gm (\ = 2 um) silicon gate 49. CAPACITANCE ESTMATION TABLE 4.5. Typical 4 ym silicon gate CMOS process capacitances PARAMETER MIN. MAX. ‘COMMENTS Gere) ao sot Gate Gera) 06+ 10" Palyiicon over fil CuipFum) ote 30" 08+ 10" Metal over poly ColpF/nm!) 038+ 10" 03+ 10°" Metal over field ColpP/um) 08+ 10" 1.0810 Metal over difuson . (p" AND 0") CalpFium?) 0810" 10 1074 nfusion GulpF/um') — ogeto" 1.9410" peiftusion GelpF/um) 7010" 90410" channel device ColpF/um) 6010" _ 80610" __ppchannel device (CMOS process. Table 4.6 shows typical capacitance values for the second level metal in a two metal process. These are included for Comparison purposes. Since the second lovel metal capacitance is {governed by the planarization layer thicknes, itis strongly dependent ‘upon the process. Furthermore, friiging felds are quite small and generally can be neglected for current technologies. An example Showing the manner in which detailed parasitic capacitances may be calculated is shown in Fig. 4.14 on page 138. Substituting in some typical values (A = 2 am) yields: Cay = (3 # 100903 + 10°* = 0.0360 poly: C, = [a » 44) + (A + 22) + 2a]0.6 «107 0.0053pF ante: = [24+ 24].0 + 10°* = 0.008pF. ‘Therefore the total capacitance Is r= Gy + C+ Cy ~ 0.0890. Its important to be able to estimate capacitances before any detailed layout is completed. For each process, it is useful to have ‘an approximate figure forthe gate capacitance ofa unt size n- and. rttensistor, the capacitance of 100 jm of poly wize, etc. In this TABLE 46. Typical 4 yum second level metal CMOS pro- [SEER pass copacharcee Wane ssENUUENEDEES PARAMETER MIN. MAK, COMMENTS Gapfiam) 02-107 ois si0% Meal to subst Calpe!) 02610" 3610" Metal 2 to poly yo" ase10 GolpF/am?) 03. al 2 to meta 1 135li ki )PGURE 414, Example of [A paraatle capactance cal = Gulation for = 24m — — = TABLE 47. Guide- lines for ignoring RC wire delays | MAXIMUM “LAYER LENGTH. Nour O00» Sililde 2,000 & Ls poly "200 8 © pitusion 20 y [Tae Garren CRCUT CRATEREATON Ne FERFORUNCE EATON fee td L 4 PAT a ws way, bus loadings and other critical parasiies can be estimated £0 1 rst order without resorting to any detailed analysis. 4.3.7 Wire length design guide FFor the purposes of timing analysis, an electrical node may be tefined as that region of connected path in which the delay associated ‘oath signal propagation is small in comparison with gate de or sufficiently small wire lengths. RC delays can be ignored. Wires ren thon be tested a3 one electical node and modeled as simple Capecitive loads. It is therefore useful to define simple electrical alos that can be used a¢ 2 guide in determining the maximum Tength of communication paths for the various interconnect levels ‘Tonio this we sequre that wire delay 1, and gate delay 7, satisfy the following condition: oe en oo biting (1) a 49), ta ee fe isn ‘This establishes an upper bound on the allowable length of the interconnects where the above approximations are valid, The eletrcal rules governing interconnect pats for atypical process are illustrated Ta'teble 27 in terms of A (es used in specification of design rules) ‘This table assumes gate delays of the order of 1.5 nS to 2.0 nS and ares the values in Table 4.3 and Table 4.5 in conjunction with Eq. (420). For example, for aluminum, 1. pez D3{e) +3 * 10 = 600000, “a SWITCHING CHARACTERISTICS So, conservatively 1 < 200000. ‘The significant factor that omerges from the table isthe difference in tolerable communication distance betwoen metal and polysilicon. ‘Although the rules shown in Table 47 are very conservative they Gre simple to remember and satisfy most of the CMOS processes that ave currently available. They may be simply rederived, for future processes, using Eq. (4.20). 4.4 _ Switching characteristics ‘The switching speed of a CMOS gate is limited by the time taken to charge and discharge the load capacitance C,. An input transition results in an output transition that either charges C, towards Voo ‘or discharges C, towards Vss. In this section, we develop simple models that describe the ‘witching characteristics of a CMOS inverter. Before proceeding, however, we need to define some terms. Referring to Fig. 4.15, on page 138, «+ Rise time; f, = time for a waveform to rise from 10 percent to 90 percent ofits steady-state value. «Fall time: ty = time for a waveform to fall from 90 percent to 10 percent ofits sjeady-state value + Delay time; ty = time difference between Input transition (50 percent level) and the 50 percent output level. (This isthe time {aken for a logic transition to pass from input to output, Fig. 4.15e shows the familiar CMOS inverter with a capacitive load (Gr thet represents the load eapaciance (input of next gates, output of this gle and routing). Of interest is the voltage waveform V.(}) when the input is driven by a step waveform V(t), a shown in Fig. 4.186, 4.4.1 Fall time determination Fig. 4.16, on page 138, shows the trajectory ofthe n-trnsistor operating plat af the input voltage, Vj(0), changes from zero volts to Vi Initially, the n-device is cutoff and the load capacitor, Cis charged to Voo. This is illustrated by X, on the characteristic curve. Application ofa step voltage (ie., Vy = Voo) at the input of the inverter changes the operating point to X.. From there onwards, the trajectory moves 197