The state of pentium bus cycle is depend upon the type bus cyicle is being processed. There are six possible states for pentium bus cycle. These are : Ty (ldle state) : After hardware reset pentium bus is in idle state. In this state, no bus cyde is currently running. Ty (First state) : This is the first state of the bus cycle. During Th, a valid address is output on the address lines and ADS is activated. Tz (Second state) : This is the second state of the bus cycle. During 7, data is read or written and the BRDY input is examined. Tr !It indicates the overlapping period of first and second states. This state exists when a second bus cycle starts before the first one completes. The data for the first bus cycle is transferred, and a new address is output on the address lines. To : State inserts a dead state between two consecutive cycles, Fig. 2.4 State transition diagram for pentlum processor