ATPG Flow

Read Netlist - reading netlist (.V format)

Read library - Defining Library for design

Build Model - Define the top module, Black box, Delete

unused gates

Perform DRC -Read the STIL file or SPF File,

-Set fault model (stuck or @speed)

-Add faults (all, some modules)

- remove fault (DT, PDT, UT, ATPG_UT, and UD)

Run ATPG- Setting pattern count or auto, compressed

Review Coverage- Report test coverage, report all fault, Non-scan

cells

Return ATPG -

Save Test pattern - Writing test pattern (serial, parallel, scan, chain)

2. Build model: (similar to read library, defining top_module)

1. build_model -workdir mydir -designsource design file1 -techlib tech_-file1 -cell top_module_name
2. build_model -designsource a.v:b.v:c.v -techlibtsmc13.v:techlib1.v -definemacro text_macro
3. build_model -workdir /local/sub_unit -designsource /local/dlx/tbdata/hierModel -techlib /local/techlib/tech90.v -cell
sub_unit
4. build_model -workdir /local/dlx -designsource /local/source/dlx.v -techlib /local/techlib/tech90.v -allowincomplete yes -
blacboxoutputs x

1. Build_testmode: (Similar to define TESTMODE, reading NETLIST)

It is used to build test modes which define the scan structure and active logic for testing.

Defining “mode definition and Sequence definition file.

1. Build_testmode -workdir ./my/workdir -testmode testmode2 -modedef FULLSCAN -assignfile ./my/Assignfile

2. Build_testmode -workdir ./my/work/dir -testmode COMPRESSION_INTEST -seqdef
./my/sequences/seqdef.COMPRESSION_INTEST -assignfile ./my/assignfile.COMPRESSION_INTEST.

3. Build_faultmodel (Similar to perform DRC( calling SPF file, setting stuck or @speed fault, setting all fault in all module
or particular module)

1. build_faultmodel -workdir mydirectory -includedynamic no

2. build_faultmodel -ignoredfaultstatistics yes

3. Verify_test_structure ( Clearing DRCs)

1. verify_test_structures -workdir mywd -testmode FULLSCAN -testdefaults no - testclockusage yes
2. verify_test_structures -testmode FULLSCAN_INTEST -xclockanalysis yes
 Create_logictest :

create_logic_tests -log no -testscan no -workdir ./myworkdir -experiment carmen_logic - testmode FULLSCAN -

maxscanswitching 25 -maxcaptureswitching 25 -compactioneffort high - effort high -activecompaction yes -scantest no -
messagecounteach 25

create_logic_tests -testmode FULLSCAN -experiment tg1

create_logic_tests -testmode FULLSCAN -experiment tg1 -effort high (effort high means – increase test coverage)

create_logic_tests -testmode COMPRESSION -onepattern yes (generate only one pattern)

Commit_test – (it store the pattern or test vector in database, then we can use command write_vector to store patterns in
separate file).

Append_test – (if we want to run a script multiple times with different ATPG controls)

“create_logic_delay_tests -testmode FULLSCAN -experiment tg2 -append yes”

Delete_test – if we want to delete previous test pattern due to many reasons (like low coverage, high pattern count), we can
delete previous run for that we can use “build_model” command, this command automatically delete all previous runs).

Example of deleting an experiment:

delete_tests -testmode FULLSCAN -experiment tg1

■ Example of deleting multiple experiments (deletes experiments tg1, tg2, and tg3):

delete_tests -testmode FULLSCAN -experiment tg1,tg2,tg

3. Prepare_fault_subset : (
It allows you to specify a subset of faults to be included in an experiment. It also allows you to adjust the fault status.
The resulting experiment is used as input to create tests that target the specified faults; or ignore the faults with adjusted
status.

1. Prepare_fault_subset -testmode MY_FUNC_TESTMODE -experiment func_ptrns_subset - faultlist

My_EVCD_Fault_List
2. Prepare_fault_subset -workdir. -testmode FULLSCAN_DELAY -experiment ramseq1

Debug to increase test coverage:

Clock off or multi-clock messages -- may want to determine if there is a way to reconfigure the testmode to avoid these issues.
Critical clock message from TSV are: TSV-017, TSV-018, TSV-020, TSV-021, TSV-059.

X-source messages -- may want to determine if there are ways you could reconfigure the testmode to eliminate sources of X.
Critical X-source messages from verify_test_structures are: TSV-101.

If running a SDC/SDF timed methodology, are there a large number of constraints that shutdown major portions of the logic?

❑ TCE-425 message reports the # of constraints

❑ Make SDC constraints as concise as possible

❑ Faults along constrained paths are untestable and lead to lower test coverage

Compact_vectors:

compact_vectors -workdir -testmode -inexperiment –experiment

Where: ■ workdir = name of the working directory

■ Testmode= name of the testmode for dynamic ATPG

■ Inexperiment= name of the experiment to run re-order

■ Experiment= output experiment name

The most commonly used options for the compact_vectors command are:

■ -resimulate yes|no - Set to no to not resimulate the result patterns. Default is yes to resimulate the results.

■ -reordercoverage both|static|dynamic - Specify the fault types to drive sorting. The default is based on the type of ATPG
patterns that are being simulated.

■ -maxcoveragestatic # - Stop patterns at a specific static coverage number (for example 99.00)

■ -maxcoveragedynamic # - Stop patterns at a specific dynamic coverage number (for example 85.00)

simulate_vectors -workdir -testmode -experiment - language -vectorfile

where: ■ workdir = name of the working directory

■ testmode= name of the testmode for dynamic ATPG

■ experiment= name of the output experiment from simulation

■ language= Type of patterns to import

■ vectorfile= Location of input vectors

The most commonly used options for the simulate_vectors command are:

■ -language stil|tbdpatt|evcd - Type of language in which the patterns are being read.

■ -gmonly no|yes - Perform good machine simulation (no fault mark off). Default is no
The following is an example of fault simulation using FULLSCAN testmode:

build_model \ -designsource ./verilog_source/DLX_TOP.v,./verilog_source/DLX_CORE.v \

-techlib ./verilog_lib,./verilog_lib/rf32x8.v,./verilog_lib/rf64x29.v,./ verilog_lib/tsmc13.v

build_testmode -modedef FULLSCAN -testmode FULLSCAN \

-assignfile ./verilog_source/FULLSCAN.pinassign

verify_test_structures -testmode FULLSCAN

build_faultmodel -includedynamic no

create_scanchain_tests -testmode FULLSCAN -experiment atpg

create_logic_tests -testmode FULLSCAN -experiment atpg -append yes

commit_tests -testmode FULLSCAN -inexperiment atpg

read_vectors -testmode FULLSCAN -experiment func_ptrns \ -language evcd -importfile My_Functional_Patterns.EVCD

simulate_vectors -testmode FULLSCAN \ -inexperiment func_ptrns -experiment func_ptrns_out -measurelatch sequential

## If you do not want to add the functional patterns to the committed

## ATPG patterns then omit

commit_tests -testmode FULLSCAN -inexperiment func_ptrns_out force=yes

## If you omit the commit step you can reference the functional patterns

## With "inexperiment=func_ptrns_out" parameter. write_vectors -testmode FULLSCAN –language.

The following is an example of fault simulation using non-scan test mode and reduced fault count:

build_model \ -designsource ./verilog_source/DLX_TOP.v,./verilog_source/DLX_CORE.v \

-techlib ./verilog_lib,./verilog_lib/rf32x8.v,./verilog_lib/rf64x29.v,./ verilog_lib/tsmc13.v

build_testmode -modedef FULLSCAN -testmode MY_FUNC_TESTMODE \ -assignfile

./verilog_source/MY_FUNC_TESTMODE.pinassign

verify_test_structures -testmode MY_FUNC_TESTMODE

build_faultmodel -includedynamic no

read_vectors -testmode MY_FUNC_TESTMODE -experiment func_ptrns_subset \ -language evcd -importfile

My_Functional_Patterns.EVCD

## If you report_faults you can then edit the output to create a reduced list.

prepare_fault_subset -a -testmode MY_FUNC_TESTMODE \ -experiment func_ptrns_subset -faultlist My_EVCD_Fault_List

simulate_vectors -testmode MY_FUNC_TESTMODE \ -inexperiment func_ptrns_subset -experiment func_ptrns_subset_out \ -
contentionremove hard

Options to Control Pattern Count and Coverage

The following options are used to limit the test coverage ATPG tries to attain during the run.

If you found that your pattern count was acceptable at your target test coverage, use one or both of these options to limit the
coverage to your target.
■ create_logic_tests -maxcoverage - maximum static coverage

■ create_logic_delay_tests -maxcoverage - maximum dynamic coverage

For example, the following command will stop static ATPG when the test coverage is at least 90%.

create_logic_tests -maxcoverage 90%

The following option is used to limit the pattern count ATPG tries to attain during the run.

■ -maxpatterns maximum number of patterns

For example:

❑ The following command will stop static ATPG when the number of patterns is at least 9500.

create_logic_tests -maxpatterns 9500

❑ The following command will stop delay ATPG when the number of dynamic patterns is at least 7500.

create_logic_delay_tests -maxpatterns 7500

Report Untested Faults:

report_faults -testmode your_testmode -experiment resim \

-faultstatus untested -includecollapsed no \

-logfile ./log_report_untested_faults \

-faulttype static