66

Chapter-3
MODELING AND ANALYSIS OF LINE
COMMUTATED CONVERTER HVDC SYSTEM
3.1

INTRODUCTION
The strength of the AC system at the location of the converter

station determined by the AC system short circuit capacity has

significant impact on design and performance of the HVDC system. The
transient performance of an HVDC system is greatly affected by the
strength of the connected AC networks. The control and operation of
conventional Line Commutated Converter (LCC) HVDC link connected to
weak AC system [56] is too complex to visualize from the system point of
view. Thus for economic design and optimal operation, HVDC system
requires a detailed investigation of dynamic performance of the system
both under steady state and transient conditions. In this chapter,
modeling and simulation of the first CIGRE benchmark system using
PSCAD/EMTDC is implemented. To the model, the steady state and
transient analysis of the system has been carried out in detailed, and the
results have been presented and analyzed.

3.2 COMPONENTS OF HVDC CONVENTIONAL SYSTEM

Based on the technology, used in the conversion station HVDC
systems are classified as conventional or classic system and HVDC light.

67
In former a thyristor and in later an IGBT is used. In this work,
conventional systems are considered. The HVDC transmission consists of
two converter stations, which are connected to each other by a
transmission link consisting of an overhead line/or a cable. The main
components of an HVDC station comprising of :
Two series connected six pulse converters consisting of valves
shown

in

Fig

3.2a

and

converter

transformers

shown

in

Fig3.2b.The valves provide the conversion from AC to DC and the

transformer provide a suitable voltage ratio to achieve the desired
direct voltage and galvanic separation of the AC system and DC
system.
Filters as shown in Fig 3.2c on AC and DC side are connected to
eliminate the current and voltage harmonics generated during
conversion.
A smoothing reactor shown in Fig 3.2d in the DC circuit reduces
the harmonic currents in the DC line and possible transient over
currents.
To complement the reactive power generation shunt capacitors are
included.
A control system will give the desired operation performance of the
transmission.
The ability of an HVDC converter to convert a three phase
alternating voltage to direct voltage that can be controlled to any value

68
between a positive and negative value depends on the following
properties of the valve. The valve conducts current in only one direction
i.e., the forward direction, from the anode to cathode. Valve blocks the
current in the opposite direction, i.e., if a voltage is applied across the
valve with cathode positive relative to the anode the valve will take up the
voltage and will block the current. This voltage is called reverse blocking
voltage. The valve starts to conduct current in forward direction provided
the following two conditions are satisfied.
The voltage in the forward direction across a valve is positive.
Control pulse is sent to the valve.
Once the valve started to conduct current the magnitude of the current is
determined solely by the main circuits outside the valve. The flow of
current through the valve continues until it decreases by external
influence and tries to pass zero, a negative voltage appears across the
valve and the current through the valve is extinguished. In forward
direction the valve with forward voltage comes into conduction state until
a control pulse is applied to the gate. This voltage is forward blocking
voltage. During each cycle of the alternating voltage the valve under go
the following states of operation.
Forward blocking interval
Conduction interval
Reverse blocking interval.

69
The following assumptions are made during the analysis
An infinite three-phase AC source connected to the converter
transformer with finite leakage inductance (L).

Fig 3.2a: Valve Hall

Fig3.2c: AC Filters

Fig.3.2b: Converter Transformer

Fig.3.2d: Smoothing Reactor

70
Valves are ideal
Infinite smoothing reactor
Ripple free current at the output of the bridge
Equal firing interval.

3.2.1 Six-Pulse Bridge Converter

Basic unit of a converter station in a conventional HVDC system is
the six-pulse bridge converter or called Graetz Bridge[25],[57] .The
structure of the bridge is shown in the Figure 3.2.1a. The equations
(3.2.1) to (3.2.5) under steady state operation of the converter is
developed in literature [25][57].

Fig 3.2.1a: Graetz Bridge Circuit

With the assumption of instantaneous current conduction the output
voltage waveforms with no delay angle and with delay angle are shown
inFig3.2.1b & 3.2.1c.

71

Fig. 3.2.1b: Voltage Waveforms with no Delay Angle

Average of the ideal no load DC Voltage Vdio is given as[58]
Vdio =32/ (eLL)

(3.2.1)

eLL =RMS AC phase to phase voltage applied to the bridge ckt.

Fig 3.2.1c: Voltage Waveforms with Delay Angle

Due to finite leakage inductance in converter transformer,
commutation from one valve to another valve is not instantaneous.

72
During commutation, three valves are in conducting state. Such a period
is called overlapping period.
Variation of output dc voltage shown in Fig.3.2.1d in relation to firing
angle
Vd = Vdocos 3XcId/

(3.2.2)

Consumption of reactive Power in terms of active power as[25]

Q = Ptan

(3.2.3)

Cos = cos 3Xc Id/Vdo

(3.2.4)

Fig3.2.1d: Rectifier DC Voltage

The reactive power depends on load conditions as well as on the
firing angle. To keep the power factor within the acceptable values firing
angle is maintained in the range of 15 to 20. The remarkable feature of
the six pulse bridge is that it can be operated not only as a rectifier as

73
described above, but it also can be operated as an inverter with firing
angle increased between 90 to 180.
Expression for the inverter in terms of extinction angle
=
represents overlap angle
Vd = Vdo cos - 3XcId/

(3.2.5)

3.3 RECTIFIER AND INVERTER CONTROLS

To transport large amount of power HVDC transmission systems
needs a tight controlling system.D.C current and voltage is precisely
controlled to affect the desired power transfer. It is necessary therefore to
continuously and precisely measure system quantities, which include at
each converter bridge i.e., the DC current, DC voltage, delay angle and
for an inverter its extinction angle . Under steady state conditions, the
inverter is assigned the task of controlling DC voltage. Thus, it may do by
maintaining a constant extinction angle , which causes the DC voltage
to droop with increasing DC current in the minimum constant extinction
angle characteristics. This means that the extinction angle must
increase beyond its minimum setting 18(60Hz).

If the inverter is

operating in a minimum constant or constant voltage characteristics,

then the rectifier must control the DC current. It can do so long as the
delay angle is not at its minimum limit (usually 5 degree).

74
The control models for both the rectifier and inverter are based
essentially on proportional and integral function blocks. While the
rectifier controls consist only of a current control loop, and the inverter
controls contains both current control and gamma control loop. Voltage
dependent current limits are included in the controls, otherwise during
disturbances, the AC voltage at the rectifier or inverter is depressed and
it will not be helpful to a weak AC system. The voltage dependent current
order limiter (VDCOL) is implemented shown in Fig.3.3 by monitoring the
inverter side DC voltage, and compounding it using the measured
current to that at the mid-point of the cable.

Fig.3.3: Static Vd-Id Characteristic of two Terminals HVDC Link

The computed midpoint voltage is then used as input to a non-linear
gain in order to modify the basic control characteristics. The combination
of the weak inverter system, the DC side resonance near fundamental,

75
and the AC side resonance near second harmonic makes the benchmark
system particularly onerous for DC and control operation.

3.4 INTERACTIONS BETWEEN THE AC AND DC SYSTEMS

The

basic

AC/DC

interaction

phenomenon

is

related

to

electromechanical and quasi steady state dynamic equations [59].

Converters consume reactive power in the process of transforming power
from AC to DC and vice versa. Hence, the converter transient response
has an impact on generator angles, through active power, and on system
voltages, through reactive power. Thus, HVDC systems can influence not
only the electromechanical oscillation dynamics but also voltage
dynamics of the AC power systems in which they are embedded. AC/DC
system interaction studies are mainly about the recovery of the system
after the disturbance, voltage stability and over voltages, especially
HVDC system connected to weak AC network. HVDC system stability is
measured by how fast the dc system recovered from the AC or DC faults.
In general, recovery time depends on the characteristics of the dc
and ac system and DC control strategy [60]. The characteristics of
AC/DC system are nothing but strength of the network, dc line
parameters i.e. line inductance, capacitance (especially if its cable),
smoothing reactor and transformer reactance. The rate of power recovery
affects system stability, since after a long period of AC system

76
disturbance, fast recovery of power may cause voltage instability if the
inverter ac system is weaker; effects subsequent commutation failures.
In particularly, low SCR system requires slow recovery of power to ensure
the AC system voltage maintained at satisfactory level.
Recovery time: It is defined as the time from fault clearing to the instant
90% of the pre-fault power is restored.
The design and performance of an HVDC system has significant
impact on the relative strength of AC system to which it is connected.
The behavior of the DC system is a function of the thevenin impedance of
the connected AC system [56]. If the impedance is small, there is very
little variation in the AC bus bar voltage and consequently the converter
operates with less risk of commutation failure and is subject to less
overvoltage stress as the DC load changes. Also, the larger the
impedance the more the likelihood of harmonic resonances which can
have disastrous effects on the converters operation.
The Short Circuit Ratio and Effective Short Circuit Ratio, are the
important indices for characterizing the degree of expected operational
problems in a dc transmission scheme[3]. The relative strength of the ac
system is often parameterized by an index called the Short Circuit Ratio

3.5 SHORT CIRCUIT RATIO (SCR)

It is defined as the ratio between the ac system short circuit MVA
to the dc power.Stronger the system lower the ac system impedance and

77
weaker the system higher the impedance. Theshunt capacitors including
ac filters connected at ac terminal of dc link can increase the effective ac
system impedance
For the circuit shown in Fig.3.4 the Short Circuit Ratio is given as
SCR

= /Pdc .

Zs = Thevenin impedance
Pdc = DC Power
V1 = Rated line Voltage

Fig:3.4: AC System at Inverter

3.6 EFFECTIVE SHORT CIRCUIT RATIO(ESCR)

More, often the index of Effective short circuit ratio (ESCR) is used.The
ESCR takes into account the reactive power generation Qf due to ac
filters,which increases the susceptability to overvoltage.The ESCR is thus
small in magnitude compare to SCR.
ESCR is defined as the difference between the short-circuit ratio
and the ratio of the reactive power supplied by capacitor banks and
filters and the rated DC power of the converter.

78
The SCR is a complex number which is inversly proportional to
Zs.However,as Zs is highly inductive the SCR is almost imaginary.Hence
the phase of the SCR is ignored and only its magnitude is refered.As a
thumb rule, a system is classified weak or strong according to ESCR
value as shown in Fig.3.5
Short Circuit(SC) MVA =
SCR

(3.1)

ESCR =
1.5
Very
Weak
System

(3.2)
2.5

Weak
system

5.0
Strong
system

Fig.3.5: System Strength Vs. ESCR

ESCR
Very
strong
System

ESCR is a simple index in the analysis of dc systems. It considers

the fundamental behavior of the system. Very often at low order
harmonic frequencies, the systems impedance can be regarded as a pure
inductance. In such a circumstance, the ESCR can provide useful
information on low order harmonic resonances.

3.7 CIGRE HVDC BENCHMARK MODEL

A First CIGRE HVDC benchmark model is chosen as the HVDC
system under study. Ainsworth [61] proposed a benchmark model

79
in1985, which was later adopted by CIGRE SC-14 to carry out analysis
and studies on the DC control aspects, aiming at the improvement of
information exchange on system simulation. This benchmark model
developed by CIGRE study group 14.02[62] (The Conseil International
des Grands Reseaux Electriques) is an international association based
in France. Both manufacturers and users from all over the world have
been using this benchmark model for testing and evaluating the
performance of the system under study. The main circuit values
proposed are arbitrary and do not represent any particular HVDC
scheme. The test system is particularly selected to have an operationally
difficult configuration. The original CIGRE benchmark model [61] is a 12
pulse bipolar system. Benchmark model of a mono polar two terminal
HVDC transmission system as shown in Fig 3.7 which has been
developed by CIGRE [62], considered for the study.

Fig: 3.7: CIGRE Benchmark Model

80
The model has been elaborated for comparative studies of different
HVDC control schemes. All the parameters of the system are in detailed
including component values, ratings, operation conditions for converters,
and steady state conditions.
The CIGRE benchmark system consists of a 500 kV,1000 MW DC
link, which connects two 345 kV and 230 kV AC systems as shown in
Fig.3.7. Each AC system has a preset Short Circuit Ratio (SCR), which
represents the degree of strength of the system. Their values in the
rectifier side (345 kV) and in the inverter side (230 kV) are respectively:
2.5pu/84 and 2.5pu/75. The model also considers AC filters of the
dampedarm type and capacitor banks for reactive power compensation.
The DC transmission line is considered as a long cable system and hence
is represented by a Tsection model with high shunt capacitance and low
series

inductance.

Modeling

of

CIGRE

Bench

mark

model

in

PSCAD/EMTDC presented and its data is given in Appendix B

3.8 PSCAD/EMTDC MODELING

Benchmark

model

of

mono

polar

two

terminal

HVDC

transmission system, which has been developed by CIGRE described in

the foregoing section has been implemented using PSCAD/EMTDC.
PSCAD is a powerful and flexible graphical user interface to the world
renowned

EMTDC

solution

engine

[63].

Typical

PSCAD/EMTDC

81
applications include control system design and coordination of FACTS
and HVDC and optimal design of controller parameters among many
others. This platform supports linear and nonlinear systems modeled in
continuous time, sampled time, or a hybrid of the two.
Several basic components of electrical networks can be found
already modeled in the extensive library supported by PSCAD/EMTDC. A
brief description of those components used in this work are presented
below.

3.8.1 Twelve Pulse Converter Model

Each converter of the HVDC link of the two area system has been
modeled in PSCAD/EMTDC using mainly two basic components
available in its library. Firstly, a sixpulse bridge [63]. This component is
a compact representation of a DC converter, which includes a built in
6pulse Graetz converter bridge (can be inverter or rectifier), an internal
Phase Locked Oscillator (PLO), firing and valve blocking controls and
firing angle ()/extinction angle () measurements. It also includes built
in RC snubber circuits for each thyristor. For each converter two of these
bridges connected in series are used. The other component is a three
phases, two windings transformer. This device represents a typical
transformer based on the classical modeling approach.The leakage
reactance of the transformer is chosen as 18% which is sufficient to limit

82
the fault current through the valves. In this simulation no tap changer is
considered because only transient phenomena is concerned. Fig3.8.1
depicts the complete configuration of the rectifier converter. Design
procedure of the converter transformer are provided in the Appendix-B.

Fig.3.8.1: Complete Converter Model in PSCAD/EMTDC

3.8.2 DC System
DC system consists of DC cables, DC filters and smoothing
reactors. In this simulation DC line is modeled using an equivalent T
network shown in Fig.3.8.2.

83

Fig.3.8.2: DC Line
This model is based on Bergons travelling wave method used by
EMTP.DC Filters are used to eliminate the higher order harmonics which
may cause interference with nearby voice frequency communication
circuits. For an HVDC system using a cable as a transmission link, this
interference problem will not arise. Hence DC filters are not used in the
simulation with a cable.

3.8.3 AC System Representation

The HVDC system is connected to 50Hz AC network on each
side.AC networks at both the rectifier and inverter ends are modeled and
represented by a Thevenin equivalent circuit as shown in Fig.3.8.3.

84
Fig3.8.3: AC System Representation
This component models a 3-phase AC voltage source, with
specified

source

or

zero-sequence

impedance. A

zero-sequence

impedance branch may be added directly within the component. In

addition, this component allows to regulate the bus voltage on a remote
location on the network, or the internal phase angle can be regulated to
control source output power. In this benchmark a weak AC network is
considered at each end. The impedance angles at rectifier are 84 and
75 at the inverter are chosen to provide the necessary damping to the
systems. Source parameters are selected such that both sending and
receiving end AC systems have an impedance peak near 100Hz.Purpose
of such selection is to create stringent operational conditions for the
controllers.

3.8.4 SCR Representation

Short Circuit Ratio is one of the important parameter for
representing the strength of AC/DC system. The impedance network at
rectifier side is represented by R-R-L and at the inverter side is
represented by R-L-L and shown in Fig.3.8.4

85

Fig3.8.4: SCR Representation at Inverter End

3.8.5 AC Filters Representation:

Tuned filters and reactive power support are provided at both
rectifier and inverter are shown in Fig.3.8.5.Filters are installed in order
to limit the harmonics to the level required by the network. In the
conversion process, the converter consumes reactive power, which is
compensated in part by the filter banks and rest by the capacitor banks
0f 600Mvar on both sides

Fig.3.8.5: AC Filter

86
The 12 pulse converter system generates characteristics of the
order 11th, 13th, 23rd, 25th, 35th, 37th and so on. In this simulation
passive tuned shunt R-L-C are used for removing lower order harmonics
(11th and 13th).A high pass filter is used for higher order harmonics.
Shunt capacitors: These filters generate fixed amount of reactive power
at the fundamental frequency. The reactive power requirement of the
converters varies with the load. Passive shunt filters are used to supply
reactive power of 50-60% of the total active power. In this simulation,
capacitor banks are represented by fixed capacitors.

3.8.6 Control System

The control structure of the HVDC CIGRE Benchmark is modeled
in PSCAD/EMTDC. Modeling is based upon the fundamental blocks
found in the Control System Modeling Functions (CSMF) folder of the
master library of this platform. For each converter control four main
blocks are used, namely: generic current control block, generic gamma
control block, voltage dependent current limits block, and minimum
gamma detector block. The complete configuration for the control of both
converters (Rectifier/inverter in this case) is depicted in Fig.3.8.6 &
Fig3.8.7. Regulators in each control block have been adjusted by trial
and error using the multi run characteristic available at PSCAD/EMTDC,
while voltage dependent current order limits have been adjusted
according to the static characteristic.

87

Fig3.8.6: Rectifier Control Configuration in PSCAD/EMTDC

Fig3.8.7: Inverter Control Configuration in PSCAD/EMTDC

88

3.9 STEADY STATE BEHAVIOR OF HVDC SYSTEM

For steady state analysis, the system has been simulated for the
duration of 5sec.Initial transients are present during start of the link,
takes 0.5 seconds to subside, and then system reaches to steady state.
For both rectifier and inverter the DC Voltages and DC Currents
waveforms are presented in Fig.3.9.1, 3.9.2, 3.9.3 & 3.9.4.

Fig.3.9.1: Steady State DC Voltage Waveform at the Rectifier

Fig.3.9.2: Steady State DC Current Waveform at the Rectifier

89

Fig 3.9.3 : Steady State DC Voltage Waveform at the Inverter

Fig 3.9.4: Steady State DC Current Waveform at the Inverter

From the dc voltage waveforms of both rectifier and inverter shown
in Fig 3.9.1and Fig 3.9.3 small oscillations occur around the reference
value 1p.u and their mean of the output dc voltage produced are
respectively 0.99pu for rectifier and 0.97pu for inverter. In case of DC
currents of rectifier and inverter the mean of the output for the
waveforms shown in Fig 3.9.2 and Fig 3.9.4 are1.0pu and 0.99pu.The

90
maximum rectifier firing angle is 17.15,inverter firing angle 141.6and
gamma angle 15 are observed.

3.10 TRANSIENT BEHAVIOR OF HVDC

VARIOUS OPERATING CONDITIONS

SYSTEM

FOR

In the following section AC and DC faults are applied at the AC

side of the inverter LCC HVDC system connected to weak ac network
having SCR of 2.5 at inverter and rectifier side are presented and
discussed.AC faults with duration of five cycles is applied at the inverter
to observe the dynamic response of the control scheme. Fault is started
at 1 second and cleared at 1.1 second.
Following are the AC faults applied at the AC side of the inverter.
Single Line to Ground fault (L-G) at inverter and rectifier
Remote Single phase to ground Fault at inverter
Three phase to Ground fault (LLLG) at inverter.
Remote Three phase to ground fault at inverter
DC fault at inverter dc transmission line

3.10.1 Single Phase to Ground Fault Applied at Inverter

A single phase to ground fault was applied to the A-phase of the
inverter bus at t=1s for duration of 5 cycles. The behavior of certain
parameters such as Vdc, Idc, angle order, thyristor valve currents and bus
phase voltages measured at both inverter and rectifier are shown from

91
Fig.3.10.1a to 3.10.1j. Due to the fault ,the AC voltage of the inverter bus
reduces as shown in Fig 3.10.1a and

the dc voltage shown in Fig

3.10.1b goes to zero (neglecting oscillations due to capacitor energy

storage).The DC current in Fig 3.10.1c therefore shoots up to a value
about 2.5pu and goes to minimum limit with some oscillation present.
This peak current is limited primarily by the impedance of the dc
smoothing reactor and converter transformer and causes dynamic
portion of the VDCL to operate and limit the current to its Imin value.
Recovery processes is initiated immediately after the fault is
released resulting in the DC current to be ramped up according to VDCL.
The alpha order at the rectifier as shown in Fig.3.10.1i is forced into
inverter region to limit the peak short circuit DC current. At the same
time, the alpha order at the inverter end as shown in Fig.3.10.1e is
forced to its alpha-min-limit. Thus rectifier and inverter reach to
maximum value thereby blocking the system for fault duration. After the
fault is cleared at about 1.1 sec, although the inverter DC voltage in Fig
3.10.1b shows that it has recovered, the rectifier DC voltage in Fig
3.10.1g shows a dip due to commutation failure in the inverter. Thus
with ac fault for duration of 5 cycle, commutation failure of multiple
occur resulting in a momentary drop of dc voltage. Commutation failure
[64] is nothing but a short-circuited dc grid and open circuited ac grid.
This failure is observed in Fig.3.10.1d, which represents the valve

92
currents. To prevent the transient instability in synchronous machines
and energy loss these faults should be recovered as fast as possible.

Fig 3.10.1a: AC Bus Voltage of Phase A at the Inverter During Single

Phase to Ground Fault (LG) on the AC Side of the Inverter.

Fig 3.10.1b: DC Voltage at the Inverter During Single Phase to

Ground Fault(LG) on the AC Side of the Inverter

93

Fig3.10.1c: DC Current at the Inverter During Single Phase to

Ground Fault (LG) on the AC Side of the Inverter

Fig 3.10.1d:12-pulse converter valve currents of the inverter during

single phase to ground fault(LG) on the AC side of the inverter.

Fig 3.10.1e: Angle Order of the Inverter During Single Phase to

Ground Fault (LG) on the AC Side of the Inverter.

94

Fig3.10.1f: AC Bus Voltage of Phase A at the Rectifier During

Single Phase to Ground Fault(LG) on the AC Side of the Inverter

Fig3.10.1g: DC voltage at the Rectifier During Single Phase to

Ground Fault(LG) on the AC Side of the Inverter.

Fig3.10.1h: DC Current at the Rectifier During Single Phase to

Ground Fault (LG) on the AC Side of the Inverter

95

Fig3.10.1i: Angle Order at the Rectifier During Single Phase to

Rectifier
: Graphs
Ground Fault(LG) on the
AC
Side of the Inverter.
Valve CurrentYD

2.00

Valve Currentyy

Valve CurrentYY&YDR

1.50
1.00
0.50
0.00
-0.50
-1.00
-1.50
-2.00
Time(s)

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

Fig 3.10.1j:12-Pulse Converter Valve Currents at the Rectifier

During Single Phase to Ground Fault (LG) on the AC Side of the
Inverter.

3.10.2:

Single Phase to Ground Fault Applied at

Rectifier AC Network

Single phase to ground fault was applied to phase-A of the

converter bus at the rectifier for the duration of 5cycles at the instant
t=1sec. When this fault is applied, the AC voltage of rectifier bus (A-

...
...
...

96
phase) reduces to zero shown in Fig 3.10.2f. Since,thyristor is a
unidirectional device DC current shown in Fig 3.10.2h goes to zero
immediately. Rectifier DC voltage in Fig.3.10.2g and DC current in
Fig3.10.2h also reduces. No power is transferred until the fault is
cleared. Rectifier current controller attempts to increase the DC voltage
by reducing the firing angle of the rectifier shown in Fig 3.10.2i. Inverter
takes control of current and therefore inverter gamma increases. With
the fault at one phase of the rectifier bus results unbalance in the other
phase voltages shown in Fig 3.10.2j cause to generate second harmonic
oscillations in DC voltages and DC currents shown in Fig3.10.2g & Fig
3.10.2h. Due to this, oscillations appear in rectifier firing angle shown in
Fig 3.10.2i and inverter angle shown in Fig3.10.2d. When the fault is
cleared after 5 cycles, due to sudden increase in the rectifier AC bus
voltage shown in Fig3.10.2f, the DC voltage and DC current represented
in Fig3.10.2g & Fig3.10.2h increases. Current controller at rectifier
attempts to reduce the current by increasing its firing angle. During the
post fault period distortion appears in AC voltages of rectifier shown in
Fig 3.10.2f and inverter in Fig 3.10.2a. The recovery slows down due to
occurrence of single commutation failure at the inverter.

97

Fig3.10.2a: AC Bus Voltage of Phase-A at the Inverter During Single

Phase to Ground Fault (LG) on the AC Side of the Rectifier.

Fig3.10.2b: DC Voltage at the Inverter During Single Phase to

Ground Fault (LG) on the AC Side of the Rectifier.

Fig3.10.2c: DC current at the inverter during single phase to ground

fault (LG) on the AC side of the rectifier

98

Fig3.10.2d: Angle Order at the Inverter During Single Phase to

Ground Fault(LG) on the AC Side of the Rectifier

Fig3.10.2e: 12-Pulse Converter Valve Currents at the Inverter

During Single Phase to Ground Fault(LG) on the AC Side of the
Rectifier

Fig 3.10.2f: AC Bus Voltage of Phase A at the Rectifier During Single

Phase to Ground Fault (LG) on the AC Side of the Rectifier.

99

Fig3.10.2g: DC Voltage at the Rectifier During Single Phase to

Ground FAULT(LG) on the AC side of the Rectifier.

Fig3.10.2h: DC Current at the Rectifier During Single Phase to

Ground Fault(LG) on the AC Side of the Rectifier

Fig3.10.2i: Angle Order at the Rectifier During Single Phase to

Ground Fault(LG) on the AC Side of the Rectifier

100

Fig3.10.2j: Valve Currents at the Rectifier During Single Phase to

Ground Fault (LG) on the AC Side of the Rectifier.

3.10.3 Remote Single Phase to Ground Fault Applied at

Inverter AC Network.
A remote single phase to ground fault is simulated by grounding
the phase A of the inverter bus through (100ohm) resistance. In practice,
this type of fault occurs more frequently in overhead lines than any other
fault. The fault is applied at t=1s for a duration of 5cycles.Simulation
results of the transient study both at inverter and rectifier are presented
and shown in Fig.3.10.3a -3.10.3j. When the fault is applied to Phase A
shown in Fig 3.10.3a. Due to reduction in dc Voltage shown in Fig
3.10.3b dc current shoots up. The peak value of the fault current shown
in Fig 3.10.3c & Fig.3.10.3h are 2pu for inverter and 1.6pu for rectifier.
The increase in current for the remote Single-phase fault, indicate a
commutation failures of the corresponding valve groups, which are
indicated in Fig3.10.3e and in Fig 3.10.3j.

101

Fig 3.10.3a: AC Voltage of Phase A at the Inverter During Remote

Single Line to Ground Fault(LG) on the AC Side of the Inverter.

Fig.3.10.3b: DC Voltage at the Inverter During Remote Single Line

to Ground Fault (LG) on the AC Side of the Inverter.

Fig3.10.3c: DC Current at the Inverter During Remote Single Line

to Ground Fault(LG) on the AC Side of the Inverter.

102

Fig3.10.3d: Angle Order at the Inverter During Remote Single Line

to Ground Fault(LG) on the AC Side of the Inverter

Fig3.10.3e: 12-Pulse Valve Currents at the Inverter During Remote

Single Line to Ground Fault(LG) on the AC Side of the Inverter

Fig3.10.3f: AC Voltage at Phase A at the Rectifier During Remote

Single Line to Ground Fault(LG) on the AC Side of the Inverter.

103

Fig3.10.3g: DC Voltage of Phase A at the Rectifier During Remote

Single Line to Ground Fault(LG) on the AC Side of the Inverter.

: Graphs
Fig3.10.3h: DC Current at the Rectifier
Rectifier
During Remote Single Line
Alpha OrderFault(LG) on the AC Side of the Inverter.
to
Ground
100
90
80
70

AO R

60
50
40
30
20
10
0
Time(s)

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

4.50

5.00

Fig3.10.3i: Angle Order at the Rectifier During Remote Single Line

to Ground Fault(LG) on the AC Side of the Inverter.

...
...
...

104

Fig3.10.3j: 12-Pulse Valve Currents at the Rectifier During Remote

Single Line to Ground Fault (LG) on the AC Side of the Inverter.

3.10.4

Three phase to Ground Fault Applied at Inverter

AC Network

The fault at inverter shown in Fig3.10.4a causes the DC voltage to

collapse and DC current to shoot up to 2.5pu and was shown in Fig.
3.10.4b &3.10.4c.Here,the decrease in DC voltage at the line is not as
fast as pole voltage at the inverter end due to the line capacitance.
Rectifier current controller attempts to reduce DC current by increasing
the firing angle of the rectifier shown in Fig3.10.4i. The rectifier therefore
goes into inverter region. At the inverter end the DC voltage depicted in
Fig3.10.4b shows the oscillations which are present due to the reflections
on the dc transmission line. The action by the VDCOL unit is able to
bring the system back to steady state quickly in a controlled manner.
Since the system is a weak system the decrease in DC Voltage and
increase in DC current shown in Fig 3.10.4b & Fig 3.10.4c results a
commutation failure shown in Fig 3.10.4e and Fig 3.10.4j. The rectifier

105
AC voltage shown in Fig 3.10.4f is distorted and over voltages up to
1.35pu appear on them. During the faulted period, the DC voltage in Fig
3.10.4g oscillates about zero value. After the fault is cleared the rectifier
DC voltage transiently reverses due to commutation failure at inverter.
The rectifier DC voltage and DC current in Fig 3.10.4g & Fig 3.10.4h
oscillate and reaches to pre-fault value in about 12 cycles after the fault
is cleared.

Fig3.10.4a: AC Bus Voltage of Three Phases at the Inverter During

Three Phase to Ground Fault(LLLG) on the AC Side of the Inverter.

Fig3.10.4b: DC Voltage at the Inverter During Three Phase to

Ground Fault(LLLG) on the AC Side of the Inverter.

106

Fig3.10.4c: DC Current at the Inverter During Three Phase to

Ground Fault(LLLG) on the AC Side of the Inverter.

Fig3.10.4d: Angle Order at the Inverter During Three Phase to

Ground Fault(LLLG) on the AC Side of the Inverter.

Fig3.10.4e: 12-Pulse Valve Currents at the Inverter During Three

Phase to Ground Fault(LLLG) on the AC Side of the Inverter.

107

Fig3.10.4f: AC Bus Voltage at the rectifier during Three Phase to

Ground Fault(LLLG) on the AC Side of the Inverter.

Fig3.10.4g: DC Voltage at the Rectifier During Three Phase to

Ground Fault(LLLG) on the AC Side of the Inverter.

Fig3.10.4h: DC Current at the Rectifier During Three Phase to

Ground Fault(LLLG) on the AC Side of the Inverter.

108

Fig3.10.4i: Angle Order at the Rectifier During Three Phase to

Ground Fault(LLLG) on the AC Side of the Inverter.

Fig3.10.4j: 12-Pulse Valve Currents at the Rectifier During Three

Phase to Ground Fault(LLLG) on the AC Side of the Inverter.
It is observed that in Fig3.10.4i the angle order of the rectifier is
advanced to 110 (minimum limit) by the commutation prevention
function, increasing the extinction angle and their by eliminating the
consecutive failure during the recovery. The rectifier current controller
attempts to reduce the DC Current shown in Fig 3.10.4h by increasing
the firing angle. Thus rectifier goes into inverter region.
It is also observed that after the fault clearance at 1.1s,there are
current spikes at both the rectifier and inverter DC bus shown in Fig

109
3.10.4c & Fig3.10.4h which are almost equal in magnitude to the initial
fault current levels. Normal operation is resumed at around 1.4s which is
almost 240ms after the clearance of the fault. As the damping is not
provided for rise in current order for rectifier it reduces the firing angle
shown in Fig.3.10.4i without allowing the voltage to rise. This cause
commutation failures and delay in the restoration process. Due to
commutation failure, the DC link voltage reduces causing

an abrupt

decrease in current order, triggering an abrupt firing angle advance in

Fig 3.10.4i which cause a dip in inverter and rectifier currents in
Fig3.10.4c & Fig3.10.4h. Due to the problem in current control scheme
mechanism post faults are observed.

3.10.5 Remote Three Phase to Ground Fault at the

Inverter
A remote three phase to ground fault was simulated by grounding
all the three phases of the converter through AC bus through 100-ohm
resistances. When the fault is applied, due to reduction in rectifier AC
bus voltage shown in Fig. 3.10.5a, DC voltage and DC current reduces
shown in Fig. 3.10.5b, & Fig. 3.10.5c. Rectifier Current controller
attempts to increase the current by reducing the firing angle hitting the
minimum limit 100shown in Fig3.10.5i. Due to reduction in DC current
shown in Fig3.10.5c, inverter current controller takes over the task of
controlling current. During fault period, DC current settles down to value

110
determined by the VDCL. When the fault is cleared, rectifier controls DC
current and inverter resumes extinction angle control. During

the

faulted period over voltages are observed on the AC voltage of the rectifier
bus shown in Fig.3.10.5f is approximately 1.24pu and at the inverter
shown in Fig 3.10.5a is 1.1pu. When the fault is cleared at t=1.1s the
increase in AC voltage shown in Fig 3.10.5a momentarily increases the
DC voltage shown in Fig.3.10.5b, and decreases the DC current
presented in Fig.3.10.5c.

Fig3.10.5a: AC Bus Voltage at the Inverter During Remote Three

Phase to Ground Fault (LLLG) on the AC Side of the Inverter.

111

Fig3.10.5b: DC Voltage at the Inverter During Remote Three Phase

to Ground Fault(LLLG) on the AC Side of the Inverter.

Fig3.10.5c: DC Current at the Inverter During Remote Three Phase

to Ground Fault(LLLG) on the AC Side of the Inverter.

Fig3.10.5d: Angle Order at the Inverter During Remote Three Phase

to Ground Fault(LLLG) on the AC Side of the Inverter.

112

Fig3.10.5e: 12 Pulse Valve Currents at the Inverter During Remote

Three Phase to Ground Fault (LLLG) on the AC Side of the Inverter.

Fig3.10.5f: AC Bus Voltage Three at the Rectifier During Remote

Three Phase to Ground Fault (LLLG) on the AC Side of the Inverter.

Fig3.10.5g: DC Voltage at the Rectifier During Remote Three Phase

to Ground Fault (LLLG) on the AC Side of the Inverter.

113

Fig3.10.5h: DC Current at the Rectifier During Remote Three Phase

to Ground Fault (LLLG) on the AC Side of the Inverter.

Fig3.10.5i: Angle Order at the Rectifier During Remote Three Phase

to Ground Fault(LLLG) on the AC Side of the Inverter.

Fig3.10.5j: 12-Pulse Valve Current s at the Rectifier During Remote

Three Phase to Ground Fault(LLLG) on the AC Side of the Inverter.

114

3.10.6

DC Fault Applied at Inverter

The

results of the study are shown in Fig. 3.10.6a to Fig3.10.6f.

The fault is applied for 5 cycles. When the fault is applied at DC line side
of inverter, it causes the DC voltage to collapse to Zero and DC current to
rises to 1.6 pu at rectifier shown in Fig 3.10.6g & Fig 3.10.6h. HVDC
control systems plays an important role in clearing the fault. A force
retard function sense the DC fault and operates the rectifier as inverter.
The order of the rectifier forces to high value shown in Fig 3.10.6f and
operates in inverter mode. At the same time the alpha angle order at the
inverter as shown in Fig3.10.6d is 88,i.e., inverter acts as rectifier. DC
line voltage becomes negative as shown in Fig 3.10.6b and energy stored
in line is returned to AC network causing rapid extinction of fault current
at next zero crossing. When is released DC voltage and DC current
recover approximately in 500 ms when fault is cleared. The smoothing
reactor and DC line impedance limits these peak values. The alpha order
at the rectifier reacts to short circuit and increases from its pre-fault
value to maximum value to reduce the fault current. It is also observed
that since the rectifier is connected to a weak system a commutation
failure occurred at the rectifier indicated with rise in DC Current shown
in Fig 3.10.6h and fall in DC Voltage shown in Fig3.10.6g. The dc power
transfer is Zero at the inverter as DC Voltage and DC Current shown in
Fig3.10.6b and Fig3.10.6c is zero at the instant of fault period.

115

Fig 3.10.6a: AC Bus Voltage at the Inverter During DC Fault Applied

at the Inverter.

Fig 3.10.6b: DC Voltage at the Inverter During DC Fault Applied at

the Inverter

Fig 3.10.6c: DC Current at the Inverter During DC Fault Applied at

the Inverter

116
Inverter : Graphs
180

Alpha Order

160
140

AO I

120
100
80
60
40
Time(s)

0.50

1.00

1.50

2.00

2.50

3.00

3.50

4.00

4.50

5.00

Fig 3.10.6d Angle Order at the Inverter During DC Fault Applied at

the Inverter.

Fig 3.10.6e : 12-Pulse Valve Currents at the Inverter During DC

Fault Applied at the Inverter.

Fig 3.10.6f: Angle Order at the Rectifier During DC Fault Applied at

the Inverter

...
...
...

117

Fig 3.10.6g: DC Voltage at the Rectifier During DC Fault Applied at

the Inverter

Fig 3.10.6h: DC Current at the Rectifier During DC Fault Applied at

the Inverter.

3.11 RESULTS AND DISCUSSION

From the results it can be seen that in case of remote three phase
to ground faults and single phase to ground faults at inverter end leads
to a reduction in the receiving voltage. This causes an initial overshoot in
DC Current depending on severity of the fault. The inverter undergoes

118
one or more commutation failures. The system however recovers after the
fault is cleared.
During normal operation rectifier is under Constant current mode
and inverter is at Constant extinction angle mode. During faults, when
the AC current decreases below the current reference of the inverter, the
inverter takes control of current .After fault is cleared constant current is
transferred back to rectifier.

3.12 SUMMARY
In this chapter an HVDC system based on the CIGRE Benchmark
model is presented. Description of various subsystems such as AC
system, AC/DC filters, Converters, Converter transformers, DC cables
and control strategies representing both rectifier and inverter are
presented.

Modeling

of

each

subsystem

is

performed

using

PSCAD/EMTDC simulation The Steady state and dynamic analysis are

performed on the benchmark model when inverter is connected to weak
AC network. The modeled system has been simulated for the following
operating conditions.

Both symmetrical and unsymmetrical faults on the AC side of the

inverter.

Both symmetrical and unsymmetrical remote faults on the AC side

of the inverter.

DC fault on the HVDC Transmission line near to the inverter.

119
The AC bus voltage ,DC Voltage ,DC current, Angle order and Valve
currents have been recorded at both the inverter and rectifier side. The
results for the performance analysis of HVDC line commutated converter
with low short circuit ratio(SCR=2.5) for both at inverter side and rectifier
side) have been presented.
From the analysis of the simulation results it is observed that
HVDC systems when connected to weak AC systems it is subjected to
high magnitude of AC voltage oscillations, recovery from disturbances,
AC voltage fluctuations are highly undesirable causing harm to AC
equipment, and thus maintain poor quality of power, whereas on DC side
the probability of commutation failure increases. High magnitude of AC
voltage oscillations is a consequence for high magnitude of AC
impedance, causing small current perturbations leading large voltage
deviations. Results presented demonstrate the controller performance in
recovery of HVDC links from various disturbances.