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Lecture19annotat PDF
Lecture19annotat PDF
Lecture 19-1
Common-Source Amplifier
Contents:
1. Amplier fundamentals
2. Common-source amplier
3. Common-source amplier with current-source supply
Reading assignment:
Howe and Sodini, Ch. 8, 8.1-8.6
Announcements:
Quiz 2: 11/16, 7:30-9:30 PM,
Lecture 19-2
Key questions
Lecture 19-3
1. Amplier fundamentals
Goal of ampliers: signal amplication.
vOUT
+V
output
signal
vIN
RL
vOUT
-
vIN
-V
input signal
Features of amplier:
Output signal is faithful replica of input signal but
amplied in magnitude.
Active device is at the heart of amplier.
Lecture 19-4
vs
voltage
amplifier
is
transconductance
amplifier
RS
transresistance
amplifier
RL
RL
iout
is
+
vout
iout
RS
vs
RL
RS
current
amplifier
RL
+
vout
Lecture 19-5
vOUT
output
signal
vIN
input signal
Lecture 19-6
2. Common-Source Amplier
RD
iR
signal source
RS
iD
+
vOUT
vs
VGG
signal
load
RL
V-=VSS
Lecture 19-7
load line
IR=ID
VDD-VSS
VGG-VSS=VDD-VSS
RD
VGG-VSS
VGG-VSS=VT
0
VSS
VDD
VOUT
VOUT
VDD
VSS
VT
VDD-VSS VGG-VSS
Want:
Bias point calculation;
small-signal gain;
limits to signal swing
frequency response [in a few days]
Lecture 19-8
W
nCox (VGG VSS VT )2
2L
VDD VOU T
IR =
RD
If we select VOU T = 0:
VDD
W
2
ID = IR =
nCox (VGG VSS VT ) =
2L
RD
Then:
VGG =
2VDD
+ VSS + VT
W
RD L nCox
Lecture 19-9
RD
+
vin
vgs
gmvgs
ro
vout
-
- S
vin
gmvin
ro//RD
vout
-
vout = gm vin(ro//RD )
unloaded
Then unlo
aded voltage gain:
Avo =
vout
= gm (ro//RD )
vin
Lecture 19-10
2 Signal swing:
VDD
RD
signal source
+
RS
vOUT
vs
VGG
VSS
Lecture 19-11
RD
iR
iL
signal source
iD
RS
+
vOUT
vs
VGG
RL
VSS
Lecture 19-12
RS
Rout
+
vs
vin
Rin
input
loading
Avovin
RL
vout
-
unloaded circuit
output
loading
s
vin = Rin Rinv+R
S
vin
vout = RL RAoutvo+R
L
Lecture 19-13
it
+
+
vt
-
vgs
gmvgs
ro//RD
vt
it = 0 Rin = =
it
No eect of loading at input.
RL
Lecture 19-14
it
+
RS
vgs
gmvgs
ro//RD
vt
= = ro//RD
it
vt
Lecture 19-15
RS
Rout
+
vs
vin
input
loading
Rin
Avovin
unloaded circuit
RL
vout
-
output
loading
vout
vs
Rin
RL
RL
=
Avo
= gm(ro //RD )
Rin + RS
RL + Rout
RL + ro //RD
Av =
Or:
Av = gm (ro //RD //RL )
Lecture 19-16
W
VDD
VDD
VDD
ID
Consequences of high RD :
large RD consumes a lot of Si real state
large RD eventually compromises frequency response
Also, it would be nice not to use any resistors at all!
Need better circuit.
Lecture 19-17
iSUP
signal source
iD
RS
signal
load
RL
vOUT
vs
VGG
VSS
Loadline view:
load line
iSUP=ID
VGG-VSS=VDD-VSS
ISUP
VGG-VSS
VGG-VSS=VT
0
VSS
VDD
VOUT
Lecture 19-18
VB
iSUP
signal source
iD
RS
+
vOUT
vs
VGG
VSS
Lecture 19-19
gm = 2
W
nCox ID
L
1
L
ro
nID ID
Then:
Circuit Parameters
Device
|Avo |
Rin Rout
Parameters gm (ro//roc ) ro//roc
ISU P
W
-
nCox
-
Lecture 19-20
Key conclusions