Digital system design using PLDs _and_¥PaAs Prograrmabl. Logic Devius SPLO = Simple PLO - Crorely used, academic intevests) CPLD - Cornplee PLO —s Tha: Memory as Programmable Logic PRoM The truth Fable is programmed ints the rremond « Adore bus act as the inpuk of He logic and data line is You cubpub: >Do (% xor Y) SRAM tannet be ured in tHe above seemario os ib is Volabile PROM anchibechie by dh oie i %! %] Loo, 1D, UY Heed AND 4 A— THuses can be blown by - Dioden prevent inkurnel n-input AND gakis one nok - a” - Bi mintexms — Thus Rod ANO bad de — Making the Inpus Se the Ay fo passing a lage curren short cht bly tu AND galt oubpubs. wore reapirel Thin ih a disadvartoge aloayp veqpired Bx a beoluan finchon be replaced by programmable Input AND galir~ AND gas programmable, tor ge tu PLA 1 YY Programmable =a — Lope Array 9, fp, — Poogramrrable AND, Zo Programmable OR A Ao vlyY Progrowersble Prag Logie ¥ — Programmable AND, Fad on. PALIbLe - Gasliey day PAL Prom Texas Instnummts Clo dedicatid inpuls + ¢ T]o pine, 1 32-bit AND gat» output connsckid co OR gal)- PAL and PLAs ave simpl PLDs — PAL 2avI0 Is one Simpl. PLO which is stil availble Prom ATMEL = PALB2VI0 has outpubs connedtid tbo Flip-Flops to get repishuntad Version of outputs: 4-91 hecodin allows bypating of Cie bypassing the Fp Plops) Comples PLD - Hievarchial SPLD - Malbigh SPLDs inter connedid — Any output oF any SPLD tan go bo any C Programmable ‘Interconnest) MAX7000 CPLD output oF Lomplumunk oubput« inpuf of omy othut SPLD INPUTIGLCK? INPUTIGCLR > INPUTIOE Hh sy HY = [canto 2 | Goce 81016 pins = Each LAS a has 1b Macrocells re rs Hs ela) 7 aby mmacrocells fal =] v0 3 [econo = |'Bloce Macrocels to 48 FOP |g 81018 Contel! 3 iopins cs Hs Source: Altera DatasheetsMAx 1000 CPLD —> Logic Array Blocks (LAB) contain number of macro cells —> All inputs come to a cross bay cohus any Inpubi can be connuchid che any of tu outpubr oe te LaBs. (Programmable Trhewonruct Array) > Global cleks can be used te eck the Plip-Plope — > Inkerconnechon behown blocks use just ont sikh: This makes fening analysis foster. MAX7000 Macrocell at doused prot — oval ta Loge Aray sess [ a on Gooel Gal | re | paatciageo™ Tso! Exandere foan Posanmatke—» allows 4 | incl) Ase Gon igure as fegser pyq Fle pass Dy 4 tov0 fh Corea CH 6 Ls are Beck oa Select © ‘Shared Logic. [a to PIA Expancors © 236 Signale fromPIA Product Terms Prog samecable Lnturconnut Prray (PIA) (Crosebor) NXN crossbar ruyuires No numky of Ni malbiplouns. \ 2x2 PIA =Xilinx XC9500 Product Term Allocator Produ ein) (oer! ee ae ee) rer ot s py} py oe Dy wo Detern Maerocells contain a product term allocator whch decidir whutlun the AND gatin output ave conrudid ky XOR oy OR oF inverters- —>» 5 product terms per macro cell held Programmabl pte Avvoys CFP6A) FPGA Ns CPLD cPLD - Logic mainly based on AND-oR - Registin to logic Yolio is small ~ Timing analysis 1s Siinple- Only Small variation in onchiteehere Ouro devices. ~ Programming Feehnolegy is Flash: — Capacity 1s upto tol Chypically) FPGA - Legte based on Mux/ Lut] Sets - Large vegistin fo loge ratio: x Anti-Puse com make — Timing analysis is complex & conmeshon Loy applising — Lange Prebitechrral variahon among devias a Voltage - Prog arming technology is SRAM, HashiAnb: Rue. 2% OLL- Delay - Contain a Pao rvilion loge call + Fao MB RAM Locked Loop ~ Crrossbaw connustion is dlishibulid so Hu chip scala uxt on Silo — Has special vesourees : PLL/ DLL , RAM, FiFos, Memery tooholers, Nehowrk Interfours, Procsors Xilinx - Sportan, Virkes, Artin, Kinker , Zyng Cowmercal FPiAS , ONS pttera - CySont, Arvta, Strate Zgrq—s has a hard dual core ARM procenoy bulk m- fo $0 40 to Strchwe oP an FPOA ~ Gre typically operalis Configurable. Logic 'g at lower voltaye (x1 V) en Ces). Tere ~ To s operate at higher 1s propranmabily ein Hoe Logie blales Volkage (-% 3-3V)— Tnterconrechon dlelays are Somewhat larger in FPGA: - Anottwr disadvantage of FPGA is the larger power dissipahon (due to the longer Ore) — To blocks Contaim tristal. bjs and synchronising creiits. Tlo Leeks may alro Support ArFPurent Voltage weds Prrogrrareable _tormuchon - SRamM (Pass transistor ) = The got of each pass SRAM Lvansistor Jn tonnedid ute memory locations on the SRam s ea evant - Paw 9 xamring He Sram than makes or breaks connechons Hip Flop Amving _veguivernts Setup cme: The time aluration Rov which an input signal must be Stable before dre Ligger edge of the cock. Hold ime: “Tn time uration fey whih am input Signal mut be stable alten the bvigger edge 4 tu dock DP setup] hold Lime vequireminls au. nat rmeh, Hu output cam be unpredictable- Clocle skeo: Ans difPerence in time ib taku dor a chk Ue ease a Plp-Plop Compaud tp amothen ts callid te clock skuo- Usually te TSE tries really hard us avoid held tine probe, enon if 1b muons Some sehip time violations ovcun. This U because Sekup time Violahont tam be Usually“vechhed by asing lower clock Pregnancy While, with held Hire violahons, tu chressk Would never otk regardlen of the Preguumuy Fao irony A bednmique ov avoiding Fiming Viclahors vorthouk reducing the ed Prequumug Hip-Plops are Inserked in the middle 4 large combinational blocks bs ment trming ‘reqplvomunls. This rathod dla» rot reduce thorouhpuk, bub Inbreduccs latory,Cyclone TW FPGA - Device: EP4cE30FasI7 ~ A general punpore PLLs - Logie. elements : 28,849 > 20 global clock nehoorks - Embedded memory: 544 Kbits — @% user Tlo banks (532 user Tlo fncluding ~ Embedded rnultipliers: 18x18 Girr0, dedicatid clock pins and dual pxpor. conf pins) Core _fabric — Logie Elementi —> 4-Inpub Lurs , memory blcles , multipliers: — Each MAK rmemony block provides 4 Kliti oP SRAM configurable ax Single port ual pork or FIFO RAM — SRAM cells used do stove configuration dati EP 4 ce| 30\F a3|1]4 |_> Speed grode (6 - fastest’) Cychone w L_—» Industrial grade. Cenhancee} 29848 > 484 pins Log! /rnemory’) Les L__s Finelne BoA Package Logie Elements —s 4 ip Lut —> Programmable veyister > Corry Chaim —lonnechon- —> Register chain Connestion —> Ability de drive the Allowing Inter cormus= Row | Coleman: = Local ; Register chon & Dived link as The prng rammable register of each LE Cam be conkgund 4 0,7, Tk ov SB Plip-Flop — 5 Fer combinahonal Kinchons , the Lut outpuk bypasses the -veyistin ond dives Avrety Jo the LE cutpubi- —s Two LE outpuls vive the Column or vow and dived link ‘vouhg conneshors, hile one LE oubput driver the local inbereonnedk verowrens . This allows Ha. Lut df diive one oulpub cabile tha -vegiia diver tha. than: Thin fealvre: called vegistin packing , lmproves devia utilisahon bucome the ‘vegtstey and Lut com be ued fe undatid —Rnchons — PA -vagistin chain oubpub allows vegistins in the Same LAB uf cascade togetian — > LEs cam operate in the Following mods = Normal rods —> “oy general logic. and combinahonall Rorchons — Prnthmetc moe —> “for adders, countiu , acuumulalors ete Logie Ary Blocks (Las) — Each LAB contaum ao group of Les =lb Logic ements — LE carry chains = LAB vontwl signals - Registin Chains - Local Tnberronnecs~ Each LAS contains dledbcatid logic Ror abvivivg the Pellowing contnad sigrals ~ 2 docks and chock enables = 2 asynch clears and one synch. cleo =) Sgndh- dood: Embedded munory - Colurons of Mak blocks — 8192 bib per block ~ Trdependint RDEN and Ween ‘Tlo loanks - Each To bank has a Separate, power bus Power—vp — APtey power-up device. gow through POR. POR delay depends on MsEL Settings Corresponding uf the conPigunahon Schur