Thc hnh: Thit k Lun l S (CE118)

LAB 3: THIT K ALU

1.1 Mc tiu
Trong bi lab ny sinh vin s tham kho thit k mt ALU 8-bit trn phn mm m phng
LogiSim.
Sinh vin s thit k mt ALU 4-bit trn phn mm LogiSim. Sau , thit k v kim
chng hot ng ca ALU ny trn KIT DE2.

1.2 Ni dung thc hnh

Thit k b ALU 4-bit c s khi v cc chc nng nh bn di
A

(SW[3:0])

(SW[8:5])

M (SW[17])
S1 (SW[16])
S0 (SW[15])

ALU

Cin (SW[14])
4

add_sub _overflow
(LEDG[5])

Zero_flat

(LEDG[7])

(LEDG[3:0])

Ch : Lnh Add (cng) v Subtract (tr) c thc hin trn 2 s c du 4-bit A v B. Kt qu

s c biu din trong s c du 4-bit (R). C bo add_sub_overflow s c bt ln 1 khi
mch pht hin c overflow xy ra.
Hi: tm biu din ca 2 ton hng A, B v kt qu Add v Subtract trn?

1.3 Sinh vin chun b

1. Download phn mm LogiSim: http://sourceforge.net/projects/circuit/
2. Xem trc clip chun b cc thao tc:
https://www.youtube.com/watch?v=dYZ-Hwbcnq4

ThS. Nguyn Thanh Sang-H L Hoi Trung

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Thc hnh: Thit k Lun l S (CE118)

3. Ti liu tham kho, hng dn s dng LogiSim:
http://www.cburch.com/logisim/docs/2.7/en/html/guide/index.html
4. V mch thit k ALU 4-bit trong phn 1.2 v m phng trn phn mm LogiSim
5. V mch thc hin ALU 4-bit trong phn 1.2 trn phn mm Quartus II

1.4 Hng dn thc hnh

1. To mt project mi, t tn:

E/CE118_lab/lab3_MSSV

2. Thc thi thit k ALU 4-bit vi cc chc nng trong phn 1.2 v m phng trn phn mm
LogiSim
3. Thit k v kim chng hot ng ca ALU 4-bit trn phn mm Quartus II v thc thi
trn KIT DE2.

ThS. Nguyn Thanh Sang-H L Hoi Trung

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Thc hnh: Thit k Lun l S (CE118)

Gii thch hin tng Trn s hc

ThS. Nguyn Thanh Sang-H L Hoi Trung

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