library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity contador is port
(
CLK: in std_logic ;
Q: out std_logic_vector(3 downto 0);
Y: out std_logic_vector(16 downto 0)
);
attribute LOC: string;
attribute LOC of CLK: signal is "P01";
attribute LOC of Q: signal is "P16:P15:p14";
attribute LOC of Y: signal is "P17:P18:P19:P20:P21:P22:P23";
end;
architecture functional of contador is
signal D: std_logic_vector(6 downto 0);
signal E: std_logic_vector(15 downto 0);
begin
G D(0) <= ( Q(0) OR Q(1) OR Q(2) );
F D(1) <= ( (NOT (Q(2)) AND (NOT(Q(3)) ) OR ( Q(1) AND (NOT(Q(2))) ) OR ( Q(1) A
ND (NOT(Q(3)) ) OR Q(0) );
E D(2) <= ( ( Q(2) AND (NOT(Q(3))) ) OR ( NOT(Q(1)) AND (NOT(Q(3))) ));
D D(3) <= ( (NOT(Q(1)) AND Q(2)) OR (Q(1) AND (NOT(Q(2))) AND Q(3)) OR ( Q(2) AN
D (NOT(Q(3))) ) OR ( NOT(Q(1)) AND (NOT(Q(3))) ));
C D(4) <= ( Q(1) OR Q(3) OR (NOT(Q(2))) );
B D(5) <= ( ( NOT(Q(2)) AND (NOT(Q(3)))) OR ( Q(2) AND Q(3) ) OR ( NOT(Q(1))) );
A D(6) <= ( ( NOT(Q(1)) NOT(Q(3)) ) OR ( Q(1) AND Q(3) ) OR ( Q(2) OR Q(0) ));
process(CLK)
begin
if(CLK' event and CLK='1')then
Q <= D;
end if;
end process;
E <= Q(1)&Q(0)&Q(2)&Q(3);;
with E select
Y <=

end functional;

"0111111"
"0000110"
"1011011"
"1001111"
"1100110"
"1101101"
"1111101"
"1000111"
"1111111"
"1100111"

when
when
when
when
when
when
when
when
when
when

"0000",0
"0001",1
"0010",2
"0011",3
"0100",4
"0101",5
"0110",6
"0111",7
"1000",8
"1001",9