Question 1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity q1 is
Port ( rst : in STD_LOGIC;
set : in STD_LOGIC;
qa : inout STD_LOGIC;
qb : inout STD_LOGIC);
end q1;
architecture Behavioral of q1 is
begin
qa <= rst NOR qb;
qb <= set NOR qa;
end Behavioral;

Question 2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity q2 is
Port ( X1 : in STD_LOGIC;
X2 : in STD_LOGIC;
X3 : in STD_LOGIC;
X4 : in STD_LOGIC;
f1 : out STD_LOGIC;
f2 : out STD_LOGIC);
end q2;
architecture Behavioral of q2 is
begin
f1 <= (X1 AND (NOT X3)) OR (X2 AND (NOT X3)) OR ((NOT X3) AND (NOT
X4)) OR (X1 AND X2) OR (X1 AND (NOT X4));
f2 <= (X1 OR (NOT X3)) AND (X1 OR X2 OR (NOT X4)) AND (X2 OR (NOT X3)
OR (NOT X4));
end Behavioral;

Question 3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity q3 is
Port ( X1 : in STD_LOGIC;
X2 : in STD_LOGIC;
X3 : in STD_LOGIC;
X4 : in STD_LOGIC;
f1 : out STD_LOGIC;
f2 : out STD_LOGIC);
end q3;
architecture Behavioral of q3 is
begin
f1 <= ((X1 AND X3) OR ((NOT X1) AND (NOT X3))) OR ((X2 AND X4)
OR ((NOT X2) AND (NOT X4)));

f2 <= (X1 AND X2 AND (NOT X3) AND (NOT X4)) OR ((NOT X1) AND
(NOT X2) AND X3 AND X4) OR (X1 AND (NOT X2) AND (NOT X2) AND X4) OR
((NOT X1) AND X2 AND X3 AND (NOT X4));
end Behavioral;

Question 4
a. c <= B"0000"; -- Binary base explicitly specified
c =0000
b. d <= X"AF67"; -- Hexadecimal base
A: 1010
F: 1111
6: 0110
7: 0111
d = 1010 1111 0110 0111
c. e <= O"723"; -- Octal base
7: 111
2: 010
3: 011
d = 111 010 011