Entity alu is

Port( clk: in STD_LOGIC;

Sel: in STD_LOGIC_VECTOR (2 DOWNTO 0);
A, B: in STD_LOGIC_VECTOR (3 DOWNTO 0);
F: out STD_LOGIC_VECTOR (3 DOWNTO 0);
Z, c: out STD_LOGIC);
End alu;
Architecture Behavioral of alu is
Signal temp, sa, sb; STD_LOGIC_VETOR (4 DOWNTO 0);
Begin
S1: process(clk, F)
Begin
If (rising_edge(clk)) then
Case S is
When 000 =>
sa<= 0&A;
sb<= 0&B;
temp <= sa + sb;
if (temp(4) = 1) then
c<=1;
else
c<=0;
end if;
F<= temp (3 DOWNTO 0);
When 001 =>
If (A>=B) then
F<= A-B;
C<=0;
Else
F<= B-A;
C<=1;
End if;

When 010 =>

If (A>=1) then
F<= A-1;
C<=0;
Else
F<= 1-A;
C<=1;
End if;
When 011 =>
sa<= 0&A;
temp<= sa +1;
if (temp(4) = 1) then
c<=1;
else
c<=0;
end if;
F<= temp (3 DOWNTO 0);
When 100 =>
F<= A and B;
When 101 =>
F<= A or B;
When 110 =>
F<= not A;
When 111 =>
F<= A xor B;
When others=>
NULL;
End case;
If (F=0000) then
Z<=1;
Else
Z<=0;

End if;
End if;
End process;
End behavioral;