Professional Documents
Culture Documents
H8DA8-2
H8DAE-2
USERS MANUAL
Revision 1.0b
The information in this Users Manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
makes no commitment to update or to keep current the information in this manual, or to notify any
person or organization of the updates. Please Note: For the most up-to-date version of this
manual, please see our web site at www.supermicro.com.
Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product
described in this manual at any time and without notice. This product, including software, if any,
and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or
reduced to any medium or machine without prior written consent.
IN NO EVENT WILL SUPERMICRO BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL,
SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO
USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. IN PARTICULAR, SUPERMICRO SHALL NOT HAVE LIABILITY FOR ANY
HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING THE
COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING OR RECOVERING SUCH
HARDWARE, SOFTWARE, OR DATA.
Any disputes arising between manufacturer and customer shall be governed by the laws of Santa
Clara County in the State of California, USA. The State of California, County of Santa Clara shall
be the exclusive venue for the resolution of any such disputes. Super Micro's total liability for
all claims will not exceed the price paid for the hardware product.
FCC Statement: This equipment has been tested and found to comply with the limits for a Class
A digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the manufacturers instruction manual, may cause harmful
interference with radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case you will be required to correct the interference at your
own expense.
California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate
warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate
Preface
Preface
About This Manual
This manual is written for system integrators, PC technicians and
knowledgeable PC users. It provides information for the installation and use of the
H8DA8-2/H8DAE-2 serverboard. The H8DA8-2/H8DAE-2 is based on the nVidia
MCP55 Pro/IO-55 chipset and supports single or dual AMD Socket F type processors and up to 64 GB of DDR2-667/533/400 registered ECC SDRAM.
Please refer to the serverboard specications pages on our web site for updates on
supported processors (http://www.supermicro.com/aplus/). This product is intended
to be professionally installed.
Manual Organization
Chapter 1 includes a checklist of what should be included in your serverboard
box, describes the features, specications and performance of the serverboard and
provides detailed information about the chipset.
Chapter 2 begins with instructions on handling static-sensitive devices. Read this
chapter when installing the processor(s) and memory modules and when installing
the serverboard in a chassis. Also refer to this chapter to connect the oppy and
hard disk drives, the parallel and serial ports, the mouse and keyboard and the
twisted wires for the power and reset buttons and the system LEDs.
If you encounter any problems, see Chapter 3, which describes troubleshooting
procedures for the video, the memory and the setup conguration stored in CMOS.
For quick reference, a general FAQ (Frequently Asked Questions) section is provided. Instructions are also included for contacting technical support. In addition,
you can visit our web site for more detailed information.
Chapter 4 includes an introduction to BIOS and provides detailed information on
running the CMOS Setup utility.
Appendix A provides BIOS Error Beep Code Messages.
Appendix B lists BIOS POST Checkpoint Codes.
iii
Table of Contents
Preface
About This Manual ...................................................................................................... iii
Manual Organization ................................................................................................... iii
Chapter 1: Introduction
1-1
1-2
1-3
1-4
1-5
1-6
Chapter 2: Installation
2-1
2-2
2-3
2-4
2-5
2-6
iv
Table of Contents
2-8
2-9
Floppy, IDE, Parallel Port, SCSI and SATA Drive Connections ................... 2-23
Chapter 3: Troubleshooting
3-1
3-2
3-3
3-4
Chapter 4: BIOS
4-1
4-2
4-3
4-4
4-5
4-6
Appendices:
Appendix A: BIOS Error Beep Codes
Appendix B: BIOS POST Checkpoint Codes
vi
Chapter 1: Introduction
Chapter 1
Introduction
1-1
Overview
Checklist
Two (2) heatsink retention modules with four (4) screws (BKT-0012L)
1-1
Contacting Supermicro
Headquarters
Address:
Tel:
Fax:
Email:
Web Site:
Europe
Address:
Tel:
Fax:
Email:
Asia-Pacic
Address:
1-2
Chapter 1: Introduction
Note:
H8DA8-2 is pictured. The H8DAE-2 shares the same layout but with no SCSI components, connectors or jumpers.
1-3
CPU2 Fan/FAN8
JPWF
JPI2C
DIMMA 1B
J3P
JAR
FAN5
FAN6
COM1
JPW2
JPW1
J32
Kb/Mse
FAN1
DIMMA 1A
DIMMA 2B
DIMMA 2A
Parallel
J6
Port
JF1
CPU2
FAN2
COM2
USB0/1/2/3
FAN3
DP4
JLAN1/2
CPU1
DIMMB 2A
DIMMB 2B
DIMMB 1A
Audio
Jacks
DIMMB 1B
CPU FAN1/FAN7
JCF1
JWF1
SIM-LP
JI2C1
JI2C2
IO-55
JFDD1
MCP55 Pro
Battery
JWD
JPA3
JBT1
JPUSB
DA1
DA2
Speaker
JPA2
FAN4
JD1
JB2
JWOR
JL1
JOH1
SGPIO1
SATA5
USB4/5
SATA4
USB6/7
SATA3
1394_1
SATA2
JWOL 1394_2
Audio_FP
CD1
JSMB
SGPIO2
BIOS
SATA0
SUPER
NEC
uPD720400
JA1
H8DA8-2
IDE#1
Notes:
1. Jumpers not indicated are for test purposes only.
2. The H8DAE-2 has the same layout as the H8DA8-2 but with no SCSI components,
connectors or jumpers.
1-4
Chapter 1: Introduction
Description
Default Setting
J3P
Closed (Enabled)
JBT1
JCF1
CMOS Clear
Compact Flash Master/Slave
JD1
Onboard Speaker
JI C1/2
I C to PCI Enable/Disable
Closed (Enabled)
JPA1
SCSI Enable/Disable
JPA2/JPA3
JPI1
Open (Enabled)
Pins 1-2 (Enabled)
JPUSB
JPX1A/JPX2A
JWD
Connectors
Description
1394_1/1394_2
Audio_FP
CD1
COM1, COM2
FAN 1-8
IDE#1
J32
JA1/JB2
JAR
J137
JD1
JF1
JFDD1
JL1
JLAN1/2
JOH1
JPI2C
JPW1
JPW2
JPWF
JSMB
JWF1
JWOL, JWOR
SATA0 ~ SATA5
SGPIO1/SGPIO2
SIM1U
USB0/1/2/3
USB4/5, USB6/7
1-5
Serverboard Features
CPU
Memory
Eight dual/single channel DIMM slots supporting up to 64 GB of DDR2667/533/400 registered ECC SDRAM
Note: Memory capacities are halved for single CPU systems. Refer to Section 2-4 before installing.
Chipset
IO-55
NEC uPD720400
Expansion Slots
Two (2) PCI-Express x16
One (1) PCI-Express x8
DMI 2.3, PCI 2.2, ACPI 2.0, SMBIOS 2.3, Plug and Play (PnP)
PC Health Monitoring
Onboard voltage monitors for two CPU cores, Hyper Transport (1.2V), two
memory banks (1.8V), chipset (1.5V)
Watch Dog
Note: the H8DA8-2/H8DAE-2 requires a power supply with >3 amps current supplied by the 5V standby voltage.
1-6
Chapter 1: Introduction
ACPI Features
Microsoft OnNow
Onboard I/O
On-chip SATA controller supporting six (6) SATA ports (RAID 0, 1, 0+1 and 5)
Adaptec AIC-7902W U320 SCSI controller (H8DA8-2 only, RAID 0, 1 and 10)
On-chip (nVidia MCP55) Ethernet controller supports two Gigabit LAN ports
Other
Wake-on-Ring (JWOR)
Wake-on-LAN (JWOL)
CD Utilities
Dimensions
Extended ATX form factor, 12" x 13.05" (305 x 332 mm)
1-7
DDR2-667/533/400
DIMM 1A
DIMM 1B
TM
AMD Opteron
Processor (CPU2)
DIMM 2A
DIMM 2B
16 x 16 HT link (1 GHz)
DIMM 1A
DIMM 1B
AMD Opteron
Processor (CPU1)
DIMM 2A
DIMM 2B
16 x 16 HT link (1 GHz)
16 x 16 HT link (1 GHz)
ALC-883 Audio
SATA Ports (6)
IDE (ATA133)
PCI-X Ch B
DDR2-667/533/400
TM
NEC
uPD720400
nVidia IO-55
nVidia MCP55Pro
USB Ports (8)
GLAN Ports (2)
TI-TSB43AB22A
IEEE 1394
LPC
S I/O
BIOS
IPMI
Kybd/
Mouse
Serial Ports
(2)
Parallel
Port
1-8
Chapter 1: Introduction
1-2
Chipset Overview
IO-55
This hub connects directly to CPU1 via a 16 x 16 1 GHz Hyper Transport link. The
IO-55 includes an interface for a PCI-Express x16 slot and interfaces with the NEC
uPD720400.
NEC uPD720400
This I/O bridge chip provides one PCI-Express x8 upstream port and two PCI-X
domains. Each bridge supports PCI masters that include clock, request and grant
signals. This hub connects to the IO-55 and through that to CPU1. It also interfaces
directly with the Adaptec SCSI controller.
HyperTransport Technology
HyperTransport technology is a high-speed, low latency point to point link that was
designed to increase the communication speed by a factor of up to 48x between
integrated circuits. This is done partly by reducing the number of buses in the
chipset to reduce bottlenecks and by enabling a more efcient use of memory in
multi-processor systems. The end result is a signicant increase in bandwidth
within the chipset.
1-9
1-3
PC Health Monitoring
This section describes the PC health monitoring features of the H8DA8-2/H8DAE2. The serverboard has an onboard System Hardware Monitor chip that supports
PC health monitoring.
1-10
Chapter 1: Introduction
1-4
This section describes the features of your serverboard that deal with power and
power settings.
Microsoft OnNow
The OnNow design initiative is a comprehensive, system-wide approach to system
and device power control. OnNow is a term for a PC that is always on but appears
to be off and responds immediately to user or other requests.
Wake-On-LAN (JWOL)
Wake-On-LAN is dened as the ability of a management application to remotely
power up a computer that is powered off. Remote PC setup, up-dates and access
tracking can occur after hours and on weekends so that daily LAN trafc is kept
to a minimum and users are not interrupted. The serverboard has a 3-pin header
(JWOL) to connect to the 3-pin header on a Network Interface Card (NIC) that has
WOL capability. Wake-On-LAN must be enabled in BIOS. Note that Wake-On-LAN
can only be used with an ATX 2.01 (or above) compliant power supply.
1-11
1-5
Power Supply
As with all computer products, a stable power source is necessary for proper and
reliable operation. It is even more important for processors that have high CPU
clock rates.
The H8DA8-2/H8DAE-2 accommodates 12V ATX power supplies. Although most
power supplies generally meet the specications required by the CPU, some are
inadequate. Important: a 3A or greater current supply on the 5V Standby rail is
required.
It is strongly recommended that you use a high quality power supply that meets
12V ATX power supply Specication 1.1 or above. Additionally, in areas where
noisy power transmission is present, you may choose to install a line lter to shield
the computer from noise. It is recommended that you also install a power surge
protector to help avoid problems caused by power surges.
Warning: To prevent the possibility of explosion, do not use the wrong type of
onboard CMOS battery or install it upside down.
1-12
Chapter 1: Introduction
1-6
Super I/O
The disk drive adapter functions of the Super I/O chip include a oppy disk drive
controller that is compatible with industry standard 82077/765, a data separator,
write pre-compensation circuitry, decode logic, data rate selection, a clock generator, drive interface control logic and interrupt and DMA logic. The wide range of
functions integrated onto the Super I/O greatly reduces the number of components
required for interfacing with oppy disk drives. The Super I/O supports two 360
K, 720 K, 1.2 M, 1.44 M or 2.88 M disk drives and data transfer rates of 250 Kb/s,
500 Kb/s or 1 Mb/s.
It also provides two high-speed, 16550 compatible serial communication ports
(UARTs), one of which supports serial infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete
modem control capability and a processor interrupt system. Both UARTs provide
legacy speed with baud rate of up to 115.2 Kbps as well as an advanced speed
with baud rates of 250 K, 500 K, or 1 Mb/s, which support higher speed modems.
The Super I/O supports one PC-compatible printer port (SPP), Bi-directional Printer
Port (BPP) , Enhanced Parallel Port (EPP) or Extended Capabilities Port (ECP).
The Super I/O provides functions that comply with ACPI (Advanced Conguration
and Power Interface), which includes support of legacy and ACPI power management through a SMI or SCI function pin. It also features auto power management
to reduce power consumption.
The IRQs, DMAs and I/O space resources of the Super I/O can be exibly adjusted
to meet ISA PnP requirements, which support ACPI.
1-13
Notes
1-14
Chapter 2: Installation
Chapter 2
Installation
2-1
Static-Sensitive Devices
Precautions
Touch a grounded metal object before removing the board from the antistatic
bag.
Handle the board by its edges only; do not touch its components, peripheral
chips, memory modules or gold contacts.
Put the serverboard and peripherals back into their antistatic bags when not in
use.
For grounding purposes, make sure your computer chassis provides excellent
conductivity between the power supply, the case, the mounting fasteners and
the serverboard.
Use only the correct type of CMOS onboard battery as specied by the manufacturer. Do not install the CMOS onboard battery upside down, which may result
in a possible explosion.
Unpacking
The serverboard is shipped in antistatic packaging to avoid static damage. When
unpacking the board, make sure the person handling it is static protected.
Installation Procedures
Follow the procedures as listed below to install the serverboard into a chassis:
1.
2.
3.
4.
2-1
2-2
sor. Always connect the power cord last and always remove it before adding, removing or changing any hardware components.
Triangles
2-2
Chapter 2: Installation
2-3
2-4
Chapter 2: Installation
2-3
2-4
Installing Memory
CAUTION
Exercise extreme care when installing or removing memory modules
to prevent any possible damage.
1. Insert each memory module vertically into its slot, paying attention to the notch
along the bottom of the module to prevent inserting the module incorrectly (see
Figure 2-2). See support information below.
2. Gently press down on the memory module until it snaps into place.
Note: each processor has its own built-in memory controller, so the CPU2 DIMMs
cannot be addressed if only a single CPU is installed. 128 MB, 256 MB, 512 MB,
1 GB, 2 GB and 4 GB memory modules are supported. It is highly recommended
that you remove the power cord from the system before installing or changing any
memory modules.
2-5
Support
The H8DA8-2/H8DAE-2 supports single or dual-channel, DDR2-667/533/400 registered ECC SDRAM.
Both interleaved and non-interleaved memory are supported, so you may populate
any number of DIMM slots (see note on previous page and charts on following
page). The CPU2 DIMM slots can only be accessed when two CPUs are installed
(however, the CPU2 DIMM slots are not required to be populated when two CPUs
are installed).
Populating two adjacent slots at a time with memory modules of the same size and
type will result in interleaved (128-bit) memory, which is faster than non-interleaved
(64-bit) memory. See charts on following page.
Optimizing memory performance
If two processors are installed, it is better to stagger pairs of DIMMs across both
sets of CPU DIMM slots, e.g. rst populate CPU1 slots 1A and 1B, then CPU2 slots
1A, and 1B, then the next two CPU1 slots, etc. This balances the load over both
CPUs to optimize performance.
Maximum memory: 64 GB of DDR2-667/533/400 registered ECC SDRAM - if only
one CPU is installed, maximum supported memory is halved (32 GB).
Notch
To Install:
Insert module vertically
and press down until it
snaps into place. The
release tabs should
close - if they do not
you should close them
yourself.
Release
Tab
Notch
Note: Notch
should align
with its
receptive point
on the slot
Release
Tab
Note the notch in the slot and on the bottom of the DIMM.
These prevent the DIMM from being installed incorrectly.
To Remove:
Use your thumbs to
gently push each release tab outward to
release the DIMM from
the slot.
2-6
Chapter 2: Installation
CPU1
DIMM1B
CPU1
DIMM2A
CPU1
DIMM2B
CPU2
DIMM1A
CPU2
DIMM1B
CPU2
DIMM2A
CPU2
DIMM2B
Notes: X indicates a populated DIMM slot. If adding at least four DIMMs (with two CPUs
installed), the congurations with DIMMs spread over both CPUs (and not like the conguration in row 5) will result in optimized performance. Note that the rst two DIMMs
must be installed in the CPU1 memory slots.
CPU1
DIMM1B
CPU1
DIMM2A
CPU1
DIMM2B
CPU2
DIMM1A
CPU2
DIMM1B
CPU2
DIMM2A
X
X
X
X
X
2-7
CPU2
DIMM2B
2-5
The I/O ports are color coded in conformance with the PC99 specication to make
setting up your system easier. See Figure 2-3 below for the colors and locations
of the various I/O ports.
Figure 2-3. I/O Port Locations and Denitions
19
Ground
NMI
x (key)
x (key)
Power LED
Vcc
HDD LED
Vcc
NIC1
Vcc
NIC2
Vcc
Vcc
Vcc
Ground
Reset
Ground
Power
2
2-8
Chapter 2: Installation
2-6
Connecting Cables
Pin#
Denition
13
+3.3V
+3.3V
14
-12V
+3.3V
15
COM
COM
16
PS_ON
+5V
17
COM
COM
18
COM
+5V
19
COM
COM
20
Res (NC)
PWR_OK
21
+5V
5VSB
22
+5V
10
+12V
23
+5V
11
+12V
24
COM
12
+3.3V
The primary ATX power supply connector (JPW1) meets the SSI (Superset ATX) 24-pin specication. Refer to
the table on the right for the pin deni-
Pin #
Denition
Power LED
Processor Power
Connector
Pin Denitions (JPW2)
Pins
Denition
1 through 4
Ground
5 through 8
+12V
Required Connection
Auxiliary Power
Connector
Pin Denitions (J32)
Pins
Denition
1&2
Ground
3&4
+12V
Required Connection
Power LED
Pin Denitions (JF1)
2-9
Pin#
Denition
15
Vcc
16
Control
HDD LED
HDD LED
Pin Denitions (JF1)
Pin#
Denition
13
Vcc
14
HD Active
NIC1 LED
NIC1 LED
Pin Denitions (JF1)
Pin#
Denition
11
Vcc
12
NIC1 Active
NIC2 LED
NIC2 LED
Pin Denitions (JF1)
Pin#
Denition
Vcc
10
NIC2 Active
2-10
OH/Fan Fail
LED Status
Pin#
Denition
State
Indication
Vcc
Solid
Overheat
Control
Blinking
Fan fail
Chapter 2: Installation
Pin#
Denition
Vcc
Control
Reset Button
Reset Button
Pin Denitions (JF1)
Pin#
Denition
Reset
Ground
Power Button
The Power Button connection is
located on pins 1 and 2 of JF1. Momentarily contacting both pins will
power on/off the system. This button
can also be congured to function
as a suspend button (see the Power
Button Mode setting in BIOS). To turn
off the power when set to suspend
mode, depress the button for at least
4 seconds. Refer to the table on the
right for pin denitions.
Power Button
Pin Denitions (JF1)
Pin#
Denition
PW_ON
Ground
USB0
Pin # Denition
2-11
USB1
Pin # Denition
+5V
+5V
PO-
PO-
PO+
PO+
Ground
Ground
USB Headers
USB2
Pin #
Denition
USB3/4
Pin #
Denition
+5V
+5V
PO-
PO-
PO+
PO+
Ground
Ground
Key
No connection
Serial Ports
Pin #
Denition
Pin #
Denition
DCD
DSR
RXD
RTS
TXD
CTS
DTR
RI
Ground
10
NC
Fan Headers
The H8DA8-2/H8DAE-2 has eight fan
headers, which are designated FAN1
through FAN8. Fans are Pulse Width
Modulated (PWM) and their speed is
controlled via Thermal Management
with a BIOS setting. See the table on
the right for pin denitions.
Note: when using active heatsinks
(those with fans), connect the heatsink
fan for CPU1 to the FAN7 header and
the heatsink fan for CPU2 to the FAN8
header.
Fan Header
Pin Denitions
(FAN1-8)
Pin#
Denition
Ground (Black)
+12V (Red)
Tachometer
PWM Control
2-12
Chapter 2: Installation
Power LED/Speaker
Pin#
Denition
+Vcc
Control
Control
Speaker Connector
Pin Denitions (JD1)
Pin#
Denition
No connection
jumper.
Buzzer signal
Speaker data
Overheat LED
Pin#
Denition
Data
NC
Ground
VCC
Clock
NC
Overheat LED
Pin Denitions (JOH1)
Pin#
Denition
3.3V
OH Active
CD1 Header
CD1
Pin Denitions
2-13
Pin#
Denition
Right Signal
Ground
Ground
Left Signal
Wake-On-LAN
Wake-On-LAN
Pin Denitions
(JWOL)
Pin#
Denition
+5V Standby
Ground
Wake-up
Wake-On-Ring
The Wake-On-Ring header is designated JWOR. This function allows
your computer to receive and "wakeup" by an incoming call to the modem
when in suspend state. See the table
on the right for pin denitions. You
must have a Wake-On-Ring card and
cable to use this feature.
Wake-On-Ring
Pin Denitions
(JWOR)
Pin#
Denition
Ground (Black)
Wake-up
I2C Header
Pin Denitions (JPI2C)
SMBus Header
Pin#
Denition
Clock
Data
PWR Fail
Gnd
+3.3V
SMBus Header
Pin Denitions (JSMB)
2-14
Pin#
Denition
Data
Ground
Clock
No Connection
Chapter 2: Installation
Denition
pin denitions.
Connect JAR to the alarm reset button on your chassis (if available) or to
a microswitch to allow you to turn off
the alarm that sounds when a power
supply module fails. See the table on
the right for pin denitions.
Pin#
Denition
Ground
Reset Signal
Compact Flash
Power Header
Pin Denitions (JWF1)
Chassis Intrusion
Pin#
Denition
+5V
Ground
Signal
Chassis Intrusion
Pin Denitions (JL1)
2-15
Pin#
Denition
Battery voltage
Intrusion signal
Firewire Headers
Pin #
Denition
Pin #
Denition
TPA+
TPA-
Ground
Ground
TPB+
TPB-
VP
VP
Key
10
S-Ground
SGPIO
SGPIO1 and SGPIO2 (Serial General
Purpose Input/Output) provide a bus
between the SATA controller and
the SATA drive backplane to provide
SATA enclosure management functions. Connect the appropriate cables
from the backplane to the SGPIO1
and SGPIO2 header(s) to utilize
SATA management functions on your
system.
SGPIO Header
Pin Denitions (SGPIO1, SGPIO2)
Pin#
Denition
Pin #
Denition
NC
NC
Ground
Data
Load
Ground
NC
NC
Pin#
Denition
Ground
Key
10
2-16
Chapter 2: Installation
Denition
Ground
Key
10
HD Audio
HD (High Denition) audio is provided with an onboard Realtek ALC883 audio chip.
The H8DA8-2/H8DAE-2 features 6-channel (5.1) sound for front L&R, rear L&R,
center and subwoofer speakers with the use of a mic or line-in device. Without
the use of a mic or line-in device, 8-channel sound (7.1) may be used. Sound is
output through the Line In, Line Out and MIC jacks (see below). There is also a
CD1 header on the board that can be used for audio.
Refer to the diagrams below for the port denitions when employing 5.1 or 7.1
sound on your system.
Audio Jacks: 5.1 Sound
2-17
2-7
Jumper Settings
Explanation of
Jumpers
To modify the operation of the
serverboard, jumpers can be used to
Connector
Pins
Jumper
Setting
CMOS Clear
JBT1 is used to clear CMOS and will also clear any passwords. Instead of pins,
this jumper consists of contact pads to prevent accidentally clearing the contents
of CMOS.
To clear CMOS,
1) First power down the system and unplug the power cord(s).
2) With the power disconnected, short the CMOS pads with a metal object such as
a small screwdriver for at least four seconds.
3) Remove the screwdriver (or shorting device).
4) Reconnect the power cord(s) and power on the system.
Notes:
Do not use the PW_ON connector to clear CMOS.
The onboard battery does not need to be removed when clearing CMOS, however
you must short JBT1 for at least four seconds.
2-18
Chapter 2: Installation
Jumper Setting
Denition
Open
Disabled
Closed
Enabled
Denition
Closed
Enabled
Open
Disabled
Watch Dog
JWD controls Watch Dog, a system
monitor that takes action when a software application freezes the system.
Jumping pins 1-2 will cause WD to
reset the system if an application is
hung up. Jumping pins 2-3 will generate a non-maskable interrupt signal
for the application that is hung up.
See the table on the right for jumper
settings. Watch Dog can also be
enabled via BIOS.
2-19
Watch Dog
Jumper Settings (JWD)
Jumper Setting
Denition
Pins 1-2
Reset
Pins 2-3
NMI
Open
Disabled
Denition
6 and 7
4 and 7
Note: Pins 4-7 are used only for the onboard speaker.
Jumper Setting
Denition
Open
Auto
Pins 1-2
PCI-X 66 MHz
Pins 2-3
PCI 66 MHz
SCSI Enable/Disable
Jumper Settings (JPA1)
Jumper JPA1 is used to enable or disable the onboard SCSI controller. The
default setting is on pins 1-2 to enable
SCSI. See the table on right for jumper
settings.
2-20
Enabled
Pins 2-3
Disabled
Chapter 2: Installation
Jumper Setting
Denition
Open
Enabled
Closed
Disabled
Standard Power
Pins 2-3
Dual Power
IEEE Enable/Disable
Jumper Settings (JPI1)
Jumper JPI1 is used to enable or disable the onboard IEEE (Firewire) headers. See the table on right for jumper
Enabled
Pins 2-3
Disabled
settings.
2-21
Compact Flash
Master/Slave
Jumper Settings (JCF1)
Jumper Setting
Denition
Closed
Master
Open
Slave
2-8
Onboard Indicators
JLAN1/JLAN2 LEDs
JLAN LED
(Connection Speed Indicator)
On
LED Color
Denition
Off
10/100 MHz
Amber
1 GHz
System Status
On
Off
No power connected
Flashing
2-22
System Status
On
Off
Chapter 2: Installation
2-9
Use the following information to connect the oppy and hard disk drive cables.
A single oppy disk drive ribbon cable has 34 wires and two connectors to provide
for two oppy disk drives. The connector with twisted wires always connects to
drive A, and the connector that does not have twisted wires always connects to
drive B.
The 80-wire ATA133 IDE hard disk drive cable that came with your system has
two connectors to support two drives. This special cable should be used to take
advantage of the speed this new technology offers. The blue connector connects
to the onboard IDE connector interface and the other connector(s) to your hard
drive(s). Consult the documentation that came with your disk drive for details
on actual jumper locations and settings for the hard disk drive.
Floppy Connector
The oppy connector is located
beside the IDE connector. See
the table on the right for pin
denitions.
Denition
GND
FDHDIN
GND
Reserved
Key
FDEDIN
GND
Index-
GND
10
Motor Enable
11
GND
12
Drive Select B-
13
GND
14
Drive Select A-
15
GND
16
Motor Enable
17
GND
18
DIR-
19
GND
20
STEP-
21
GND
22
Write Data-
23
GND
24
Write Gate-
25
GND
26
Track 00-
27
GND
28
Write Protect-
29
GND
30
Read Data-
31
GND
32
Side 1 Select-
33
GND
34
Diskette
2-23
Pin #
Denition
IDE Connector
Pin#
Denition
Reset IDE
Ground
Host Data 7
Host Data 8
Host Data 6
Host Data 9
Host Data 5
Host Data 10
Host Data 4
10
Host Data 11
11
Host Data 3
12
Host Data 12
13
Host Data 2
14
Host Data 13
15
Host Data 1
16
Host Data 14
17
Host Data 0
18
Host Data 15
19
Ground
20
Key
21
DRQ3
22
Ground
23
I/O Write
24
Ground
25
I/O Read
26
Ground
27
IOCHRDY
28
BALE
29
DACK3
30
Ground
31
IRQ14
32
IOCS16
33
Addr1
34
Ground
35
Addr0
36
Addr2
37
Chip Select 0
38
Chip Select 1
39
Activity
40
Ground
2-24
Pin #
Denition
Chapter 2: Installation
Parallel Port
Connector
Denition
Strobe-
Auto Feed-
Data Bit 0
Error-
(printer) port.
Data Bit 1
Init-
Data Bit 2
SLCT IN-
Data Bit 3
10
GND
11
Data Bit 4
12
GND
13
Data Bit 5
14
GND
15
Data Bit 6
16
GND
17
Data Bit 7
18
GND
19
ACK
20
GND
21
BUSY
22
Write Data
23
PE
24
Write Gate
25
SLCT
26
NC
SATA Ports
Pin #
Denition
SATA Ports
Pin Denitions (SATA0-SATA5)
Pin #
2-25
Denition
Ground
TXP
TXN
Ground
RXN
RXP
Ground
SCSI Connectors
(H8DA8-2 only)
Denition
Pin #
Denition
+DB (12)
35
-DB (12)
+DB (13)
36
-DB (13)
+DB (14)
37
-DB (14)
+DB (15)
38
-DB (15)
+DB (P1)
39
-DB (P1)
+DB (0)
40
-DB (0)
+DB (1)
41
-DB (1)
+DB (2)
42
-DB (2)
+DB (3)
43
-DB (3)
10
+DB (4)
44
-DB (4)
11
+DB (5)
45
-DB (5)
12
+DB (6)
46
-DB (6)
13
+DB (7)
47
-DB (7)
14
+DB (P)
48
-DB (P)
15
Ground
49
Ground
16
DIFFSENS
50
Ground
17
TERMPWR
51
TERMPWR
18
TERMPWR
52
TERMPWR
19
Reserved
53
Reserved
20
Ground
54
Ground
21
+ATN
55
-ATN
22
Ground
56
Ground
23
+BSY
57
-BSY
24
+ACK
58
-ACK
25
+RST
59
-RST
26
+MSG
60
-MSG
27
+SEL
61
-SEL
28
+C/D
62
-C/D
29
+REQ
63
-REQ
30
+I/O
64
-I/O
31
+DB (8)
65
-DB (8)
32
+DB (9)
66
-DB (9)
33
+DB (10)
67
-DB (10)
34
+DB (11)
68
-DB (11)
2-26
Chapter 2: Installation
2-27
2. Use the arrow keys to move to Advanced > Floppy/IDE/SATA Conguration >
nVidia RAID Setup and press the <Enter> key. Once in the submenu, enable the
"nVidia RAID Function" setting, which will cause the SATA0/1/2 Primary/Secondary
settings to appear. Enable the SATA devices and channels you will be using.
3. Hit the <F10> key to "Save Changes and Exit", then hit <Enter> to verify.
4. After exiting the BIOS Setup Utility, the system will reboot. When prompted
during the startup, press the <F10> key when prompted to run the nVidia RAID
Utility program.
2-28
Chapter 2: Installation
2-29
Click the icons showing a hand writing on paper to view the readme les for each
item. Click the tabs to the right of these in order from top to bottom to install each
item one at a time. After installing each item, you must reboot the system
before moving on to the next item on the list. You should install everything here
except for the SUPER Doctor utility, which is optional. The bottom icon with a CD
on it allows you to view the entire contents of the CD.
2-30
Chapter 3: Troubleshooting
Chapter 3
Troubleshooting
3-1
Troubleshooting Procedures
Use the following procedures to troubleshoot your system. If you have followed all
of the procedures below and still need assistance, refer to the Technical Support
Procedures and/or Returning Merchandise for Service section(s) in this chapter.
Always disconnect the AC power cord before adding, changing or installing any
hardware components.
Before Power On
1. Check that the onboard power LED is lit (DP4 on the serverboard).
2. Make sure that the main ATX power connector at JPW1, the 8-pin connector at
JPW2 and the 4-pin connecor at J32 are all connected to your power supply.
3. Make sure that no short circuits exist between the serverboard and chassis.
4. Disconnect all ribbon/wire cables from the serverboard, including those for the
keyboard and mouse.
5. Remove all add-on cards.
6. Install a CPU and heatsink (making sure it is fully seated) and connect the internal (chassis) speaker and the power LED to the serverboard. Check all jumper
settings as well.
7. Use the correct type of onboard CMOS battery as recommended by the manufacturer. To avoid possible explosion, do not install the CMOS battery upside down.
8. Note that the 5VSB supplied from your power supply must provide >3 amps.
No Power
1. Make sure that no short circuits exist between the serverboard and the chassis.
2. Verify that all jumpers are set to their default positions.
3. Check that the 115V/230V switch on the power supply is properly set.
4. Turn the power switch on and off to test the system.
5. The battery on your serverboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.
No Video
1. If the power is on but you have no video, remove all add-on cards and cables.
2. Use the speaker to determine if any beep codes exist. Refer to Appendix A for
details on beep codes.
3-1
NOTE
If you are a system integrator, VAR or OEM, a POST diagnostics
card is recommended. For I/O port 80h codes, refer to App. B.
Memory Errors
1. Make sure that the DIMM modules are properly and fully installed.
2. You should be using registered ECC DDR-2 memory (see next page). Also, it
is recommended that you use the same memory type and speed for all DIMMs in
the system. See Section 2-4 for memory details and limitations.
3. Check for bad DIMM modules or slots by swapping modules between slots and
noting the results.
4. Check the power supply voltage 115V/230V switch.
3-2
Before contacting Technical Support, please take the following steps. Also, note
that as a serverboard manufacturer, we do not sell directly to end-users, so it is
best to rst check with your distributor or reseller for troubleshooting services. They
should know of any possible problem(s) with the specic system conguration that
was sold to you.
1. Please review the Troubleshooting Procedures and 'Frequently Asked Questions'
(FAQs) sections in this chapter or see the FAQs on our web site before contacting
Technical Support.
2. BIOS upgrades can be downloaded from our web site.
Note: Not all BIOS can be ashed depending on the modications to the boot block
code.
3-2
Chapter 3: Troubleshooting
3. If you still cannot resolve the problem, include the following information when
contacting us for technical support:
BIOS release date/version (this can be seen on the initial display when your
system rst boots up)
System conguration
3-3
3-3
Question: Why can't I turn off the power using the momentary power on/off
switch?
Answer: The instant power off function is controlled in BIOS by the Power Button Mode setting. When the On/Off feature is enabled, the serverboard will have
instant off capabilities as long as the BIOS has control of the system. When the
Standby or Suspend feature is enabled or when the BIOS is not in control such
as during memory count (the rst screen that appears when the system is turned
on), the momentary on/off switch must be held for more than four seconds to shut
down the system. This feature is required to implement the ACPI features on the
serverboard.
Question: How do I connect the ATA133 cable to my IDE device(s)?
Answer: The 80-wire/40-pin high-density ATA133 IDE cable that came with your
system has two connectors to support two drives. This special cable must be used
to take advantage of the speed the ATA133 technology offers. Connect the blue
connector to the onboard IDE header and the other connector(s) to your hard
drive(s). Consult the documentation that came with your disk drive for details on
actual jumper locations and settings.
3-4
A receipt or copy of your invoice marked with the date of purchase is required before any warranty service will be rendered. You can obtain service by calling your
vendor for a Returned Merchandise Authorization (RMA) number. When returning
to the manufacturer, the RMA number should be prominently displayed on the
outside of the shipping carton, and mailed prepaid or hand-carried. Shipping and
handling charges will be applied for all orders that must be mailed when service
is complete.
For faster service, RMA authorizations may be requested online (http://www.
supermicro.com/support/rma/).
This warranty only covers normal consumer use and does not cover damages incurred in shipping or from failure due to the alteration, misuse, abuse or improper
maintenance of products.
During the warranty period, contact your distributor rst for any product problems.
3-4
Chapter 4: BIOS
Chapter 4
BIOS
4-1
Introduction
This chapter describes the AMIBIOS Setup utility for the H8DA8-8/H8DAE-2.
The AMI ROM BIOS is stored in a ash chip and can be easily upgraded using a
oppy disk-based program.
Note: Due to periodic changes to the BIOS, some settings may have been added or
deleted and might not yet be recorded in this manual. Please refer to the Manual
Download area of our web site for any changes to BIOS that may not be reected
in this manual.
4-1
4-2
Main Menu
When you rst enter AMI BIOS Setup Utility, you will see the Main Menu screen.
You can always return to the Main Menu by selecting the Main tab on the top of
the screen with the arrow keys.
The Main Menu screen provides you with a system overview, which includes the
version, built date and ID of the AMIBIOS, the type, speed and number of the
processors in the system and the amount of memory installed in the system.
4-3
Quiet Boot
If Disabled, normal POST messages will be displayed on boot-up. If Enabled,
this display the OEM logo instead of POST messages.
OS Installation
Change this setting if using a Linux operating system. The available options
are Other and Linux.
ACPI Mode
Use this setting to determine whether ACPI mode will be used. The options
are Yes and No.
Suspend Mode
This setting is used to select the ACPI state used for system suspend. The
options are S1 (POS), S3 (STR) and Auto.
4-2
Chapter 4: BIOS
Headless Mode
Use this setting to Enable or Disable headless operation mode through
ACPI.
4-3
MPS Revision
This setting allows the user to select the MPS revision level. The options are
1.1 and 1.4.
Floppy/IDE/SATA Conguration
Floppy A
Move the cursor to these elds via up and down <arrow> keys to select the oppy
type. The options are Disabled, 360 KB 5 1/4", 1.2 MB 5 1/4", 720 KB 3", 1.44
MB 3, and 2.88 MB 3".
4-4
Chapter 4: BIOS
Type
Select the type of device connected to the system. The options are Not Installed,
Auto, CDROM and ARMD.
LBA/Large Mode
LBA (Logical Block Addressing) is a method of addressing data on a disk drive.
The options are Disabled and Auto.
PIO Mode
PIO (Programmable I/O) mode programs timing cycles between the IDE drive
and the programmable IDE controller. As the PIO mode increases, the cycle time
decreases. The options are Auto, 0, 1, 2, 3, and 4. Select Auto to allow AMI
BIOS to auto detect the PIO mode. Use this value if the IDE disk drive support
cannot be determined. Select 0 to allow AMI BIOS to use PIO mode 0. It has a
data transfer rate of 3.3 MBs. Select 1 to allow AMI BIOS to use PIO mode 1.
It has a data transfer rate of 5.2 MBs. Select 2 to allow AMI BIOS to use PIO
mode 2. It has a data transfer rate of 8.3 MBs. Select 3 to allow AMI BIOS to
use PIO mode 3. It has a data transfer rate of 11.1 MBs. Select 4 to allow AMI
BIOS to use PIO mode 4. It has a data transfer rate of 16.6 MBs. This setting
generally works with all hard disk drives manufactured after 1999. For other disk
drives, such as IDE CD-ROM drives, check the specications of the drive.
4-5
DMA Mode
Selects the DAM Mode.
S.M.A.R.T.
Self-Monitoring Analysis and Reporting Technology (SMART) can help predict
impending drive failures. Select "Auto" to allow BIOS to auto detect hard disk
drive support. Select "Disabled" to prevent AMI BIOS from using the S.M.A.R.T.
Select "Enabled" to allow AMI BIOS to use the S.M.A.R.T. to support hard drive
disk. The options are Disabled, Enabled, and Auto.
LBA/Large Mode
LBA (Logical Block Addressing) is a method of addressing data on a disk drive.
The options are Disabled and Auto.
PIO Mode
PIO (Programmable I/O) mode programs timing cycles between the IDE drive
and the programmable IDE controller. As the PIO mode increases, the cycle time
4-6
Chapter 4: BIOS
decreases. The options are Auto, 0, 1, 2, 3, and 4. Select Auto to allow AMI
BIOS to auto detect the PIO mode. Use this value if the IDE disk drive support
cannot be determined. Select 0 to allow AMI BIOS to use PIO mode 0. It has a
data transfer rate of 3.3 MBs. Select 1 to allow AMI BIOS to use PIO mode 1.
It has a data transfer rate of 5.2 MBs. Select 2 to allow AMI BIOS to use PIO
mode 2. It has a data transfer rate of 8.3 MBs. Select 3 to allow AMI BIOS to
use PIO mode 3. It has a data transfer rate of 11.1 MBs. Select 4 to allow AMI
BIOS to use PIO mode 4. It has a data transfer rate of 16.6 MBs. This setting
generally works with all hard disk drives manufactured after 1999. For other disk
drives, such as IDE CD-ROM drives, check the specications of the drive.
DMA Mode
Selects the DAM Mode. Options are SWDMA0, SWDMA1, SWDMA2,
MWDMA0. MDWDMA1, MWDMA2, UDMA0. UDMA1, UDMA2, UDMA3,
UDMA4 and UDMA5. (SWDMA=Single Word DMA, MWDMA=Multi Word DMA,
UDMA=UltraDMA.)
S.M.A.R.T.
Self-Monitoring Analysis and Reporting Technology (SMART) can help predict
impending drive failures. Select "Auto" to allow BIOS to auto detect hard disk
drive support. Select "Disabled" to prevent AMI BIOS from using the S.M.A.R.T.
Select "Enabled" to allow AMI BIOS to use the S.M.A.R.T. to support hard drive
disk. The options are Disabled, Enabled, and Auto.
4-7
PCI/PnP Conguration
Clear NVRAM
Select Yes to clear NVRAM during boot-up. The options are Yes and No.
Palette Snooping
Select "Enabled" to inform the PCI devices that an ISA graphics device is installed
in the system in order for the graphics card to function properly. The options are
Enabled and Disabled.
4-8
Chapter 4: BIOS
NorthBridge Conguration
Memory Conguration
Memclock Mode
This setting determines how the memory clock is set. Auto has the memory
clock by code and Limit allows the user to set a standard value.
Bank Interleaving
Select Auto to automatically enable interleaving-memory scheme when this
function is supported by the processor. The options are Auto and Disabled.
CS Sparing Enable
Use this setting to Enable or Disable CS Sparing.
ECC Conguration
DRAM ECC Enable
DRAM ECC allows hardware to report and correct memory errors automatically. Options are Enabled and Disabled.
4-9
DRAM BG Scrub
Corrects memory errors so later reads are correct. Options are Disabled and various times in nanoseconds and microseconds.
L2 Cache BG Scrub
Allows L2 cache RAM to be corrected when idle. Options are Disabled and
various times in nanoseconds and microseconds.
Alternate VID
Specify the alternate VID while in low power states. Options are Auto and various voltages from .8V to 1.15V in increments of .025V.
SouthBridge/MCP55 Conguration
USB 1.1 Controller
Enable or disable the USB 1.1 controller.
MAC0 LAN0
Settings are Auto and Disabled for MAC0 LAN0.
4-10
Chapter 4: BIOS
MAC1 LAN1
Settings are Auto and Disabled for MAC1 LAN1.
MTRR Mapping
This determines the method used for programming CPU MTRRs when 4 GB or more
memory is present. The options are Continuous, which makes the PCI hole noncacheable, and Discrete, which places the PCI hole below the 4 GB boundary.
Thermal Throttling
Used to Enable or Disable thermal to generate a power management event.
Power Now
This setting is used to Enable or Disable the AMD Power Now feature.
4-11
4-12
Chapter 4: BIOS
Console Redirection
Remote Access
Allows you to Enable or Disable remote access. If enabled, the settings below
will appear.
Flow Control
Selects the ow control to be used for console redirection. Options are None,
Hardware and Software.
Terminal Type
Selects the type of the target terminal. Options are ANSI, VT100 and VTUTF8.
4-13
Hardware Monitor
CPU Overheat Alarm
Use the "+" and "-" keys to set the CPU temperature threshold to between 65o
and 90o C. When this threshold is exceeded, the overheat LED on the chassis will light up and an alarm will sound. The LED and alarm will turn off once
the CPU temperature has dropped to 5 degrees below the threshold set. The
default setting is 72o C.
Other items in the submenu are systems monitor displays for the following information:
CPU1 Temperature, CPU2 Temperature (for 2U systems), System Temperature,
VCoreA, VCoreB (for 2U systems), HT Voltage, CPU1 Mem VTT, CPU2 Mem
VTT, CPU1 Mem, CPU2 Mem, VDD, 1.5V, MCP55 VCcore, 3.3V, 12V, -12V, 5V
VSB and VBAT.
4-14
Chapter 4: BIOS
IPMI Conguration
Pressing the Enter key will open the event log. Use the "+" and "-" keys to
navigate through the system event log.
IP Address
Use the "+" and "-" keys to select the parameter. The IP address and current
IP address in the BMC are shown.
MAC Address
Use the "+" and "-" keys to select the parameter. The MAC address and current MAC address in the BMC are shown.
Subnet Address
Use the "+" and "-" keys to select the parameter. The subnet address and
current subnet address in the BMC are shown.
4-15
Startup Delay
Use this setting to Enable or Disable the startup delay.
4-4
Boot Menu
This feature allows the user to prioritize the boot sequence from the available devices. The devices to set are:
1st Boot Device
2nd Boot Device
3rd Boot Device
4th Boot Device
This feature allows the user to specify the boot sequence from available hard disk
drives.
1st Drive
Species the boot sequence for the 1st Hard Drive.
Removable Drives
This feature allows the user to specify the Boot sequence from available removable drives.
1st Drive
Species the boot sequence for the 1st Removable Drive. The options are 1st
Floppy Drive and Disabled.
4-16
Chapter 4: BIOS
CD/DVD Drives
This feature allows the user to specify the Boot sequence from available CD/DVD
drives.
4-5
Security Menu
AMI BIOS provides a Supervisor and a User password. If you use both passwords,
the Supervisor password must be set rst.
4-17
4-6
Exit Menu
Select the Exit tab from AMI BIOS Setup Utility screen to enter the Exit BIOS Setup
screen.
Discard Changes
Select this option and press <Enter> to discard all the changes and return to AMI
BIOS Utility Program.
4-18
Appendix A
BIOS Error Beep Codes
During the POST (Power-On Self-Test) routines, which are performed each time
the system is powered on, errors may occur.
Non-fatal errors are those which, in most cases, allow the system to continue the
boot-up process. The error messages normally appear on the screen.
Fatal errors are those which will not allow the system to continue the boot-up procedure. If a fatal error occurs, you should consult with your system manufacturer
for possible repairs.
These fatal errors are usually communicated through a series of audible beeps.
The numbers on the fatal error list, on the following page, correspond to the number
of beeps for the corresponding error. All errors listed, with the exception of Beep
Code 8, are fatal errors.
POST codes may be read on the debug LEDs located beside the LAN port on the
serverboard backplane. See the description of the Debug LEDs (LED1 and LED2)
in Chapter 5.
A-1
Beep Code
Error Message
Description
1 beep
Refresh
5 short, 1 long
Memory error
No memory detected in
system
8 beeps
Video error
A-1
Notes
A-2
Appendix B
BIOS POST Checkpoint Codes
When AMIBIOS performs the Power On Self Test, it writes checkpoint codes to I/O
port 0080h. If the computer cannot complete the boot process, diagnostic equipment
can be attached to the computer to read I/O port 0080h.
B-1
Code Description
D0h
The NMI is disabled. Power on delay is starting. Next, the initialization code checksum will be veried.
D1h
Initializing the DMA controller, performing the keyboard controller BAT test, starting
memory refresh and entering 4 GB at mode next.
D3h
D4h
Returning to real mode. Executing any OEM patches and setting the Stack next.
D5h
B-1
B-2
Checkpoint
Code Description
E0h
The onboard oppy controller if available is initialized. Next, beginning the base
512 KB memory test.
E1h
E2h
E6h
Enabling the oppy drive controller and Timer IRQs. Enabling internal cache memory.
Edh
Eeh
Looking for a oppy diskette in drive A:. Reading the rst sector of the diskette.
Efh
A read error occurred while reading the oppy drive in drive A:.
F0h
F1h
F2h
Next, reading and analyzing the oppy diskette FAT to nd the clusters occupied
by the AMIBOOT.ROM le.
F3h
F4h
F5h
FBh
FCh
FDh
FFh
Flash ROM programming was successful. Next, restarting the system BIOS.
B-2
B-3
Checkpoint
Code Description
03h
The NMI is disabled. Next, checking for a soft reset or a power on condition.
05h
The BIOS stack has been built. Next, disabling cache memory.
06h
07h
08h
0Ah
The CMOS checksum calculation is done. Initializing the CMOS status register for
date and time next.
0Bh
The CMOS status register is initialized. Next, performing any required initialization
before the keyboard BAT command is issued.
0Ch
The keyboard controller input buffer is free. Next, issuing the BAT command to the
keyboard controller.
0Eh
The keyboard controller BAT command result has been veried. Next, performing
any necessary initialization after the keyboard controller BAT command test.
0Fh
The initialization after the keyboard controller BAT command test is done. The keyboard command byte is written next.
10h
The keyboard controller command byte is written. Next, issuing the Pin 23 and 24
blocking and unblocking command.
11h
Next, checking if <End or <Ins> keys were pressed during power on. Initializing
CMOS RAM if the Initialize CMOS RAM in every boot AMIBIOS POST option was
set in AMIBCP or the <End> key was pressed.
12h
13h
The video display has been disabled. Port B has been initialized. Next, initializing
the chipset.
14h
19h
1Ah
The memory refresh line is toggling. Checking the 15 second on/off time next.
2Bh
Passing control to the video ROM to perform any required conguration before the
video ROM test.
2Ch
All necessary processing before passing control to the video ROM is done. Looking for the video ROM next and passing control to it.
2Dh
The video ROM has returned control to BIOS POST. Performing any required processing after the video ROM had control
23h
Reading the 8042 input port and disabling the MEGAKEY Green PC feature next.
Making the BIOS code segment writable and performing any necessary conguration before initializing the interrupt vectors.
24h
The conguration required before interrupt vector initialization has completed. Interrupt vector initialization is about to begin.
B-3
Checkpoint
Code Description
25h
Interrupt vector initialization is done. Clearing the password if the POST DIAG
switch is on.
27h
28h
Initialization before setting the video mode is complete. Conguring the monochrome mode and color mode settings next.
2Ah
Bus initialization system, static, output devices will be done next, if present. See the
last page for additional information.
2Eh
2Fh
The EGA/VGA controller was not found. The display memory read/write test is
about to begin.
30h
The display memory read/write test passed. Look for retrace checking next.
31h
The display memory read/write test or retrace checking failed. Performing the alternate display memory read/write test next.
32h
The alternate display memory read/write test passed. Looking for alternate display
retrace checking next.
34h
37h
38h
Initializing the bus input, IPL, general devices next, if present. See the last page of
this chapter for additional information.
39h
Displaying bus initialization error messages. See the last page of this chapter for
additional information.
3Ah
The new cursor position has been read and saved. Displaying the Hit <DEL> message next.
3Bh
The Hit <DEL> message is displayed. The protected mode memory test is about
to start.
40h
42h
The descriptor tables are prepared. Entering protected mode for the memory test
next.
43h
44h
Interrupts enabled if the diagnostics switch is on. Initializing data to check memory
wraparound at 0:0 next.
45h
Data initialized. Checking for memory wraparound at 0:0 and nding the total system memory size next.
46h
The memory wraparound test is done. Memory size calculation has been done.
Writing patterns to test memory next.
47h
The memory pattern has been written to extended memory. Writing patterns to the
base 640 KB memory next.
48h
49h
4Bh
The amount of memory above 1 MB has been found and veried. Checking for a
soft reset and clearing the memory below 1 MB for the soft reset next. If this is a
power on situation, going to checkpoint 4Eh next.
B-4
Checkpoint
Code Description
4Ch
The memory below 1 MB has been cleared via a soft reset. Clearing the memory
above 1 MB next.
4Dh
The memory above 1 MB has been cleared via a soft reset. Saving the memory size
next. Going to checkpoint 52h next.
4Eh
The memory test started, but not as the result of a soft reset. Displaying the rst
64 KB memory size next.
4Fh
The memory size display has started. The display is updated during the memory
test. Performing the sequential and random memory test next.
50h
The memory below 1 MB has been tested and initialized. Adjusting the displayed
memory size for relocation and shadowing next.
51h
The memory size display was adjusted for relocation and shadowing.
52h
The memory above 1 MB has been tested and initialized. Saving the memory size
information next.
53h
The memory size information and the CPU registers are saved. Entering real mode
next.
54h
Shutdown was successful. The CPU is in real mode. Disabling the Gate A20 line,
parity, and the NMI next.
57h
The A20 address line, parity, and the NMI are disabled. Adjusting the memory size
depending on relocation and shadowing next.
58h
The memory size was adjusted for relocation and shadowing. Clearing the Hit
<DEL> message next.
59h
The Hit <DEL> message is cleared. The <WAIT...> message is displayed. Starting
the DMA and interrupt controller test next.
60h
The DMA page register test passed. Performing the DMA Controller 1 base register
test next.
62h
The DMA controller 1 base register test passed. Performing the DMA controller 2
base register test next.
65h
The DMA controller 2 base register test passed. Programming DMA controllers 1
and 2 next.
66h
67h
7Fh
80h
The keyboard test has started. Clearing the output buffer and checking for stuck
keys. Issuing the keyboard reset command next.
81h
A keyboard reset error or stuck key was found. Issuing the keyboard controller
interface test command next.
82h
The keyboard controller interface test completed. Writing the command byte and
initializing the circular buffer next.
83h
The command byte was written and global data initialization has completed. Checking for a locked key next.
84h
Locked key checking is over. Checking for a memory size mismatch with CMOS
RAM data next.
85h
The memory size check is done. Displaying a soft error and checking for a password
or bypassing WINBIOS Setup next.
B-5
Checkpoint
Code Description
86h
The password was checked. Performing any required programming before WINBIOS Setup next.
87h
88h
Returned from WINBIOS Setup and cleared the screen. Performing any necessary
programming after WINBIOS Setup next.
89h
The programming after WINBIOS Setup has completed. Displaying the power on
screen message next.
8Ch
8Dh
The WINBIOS Setup options are programmed. Resetting the hard disk controller
next.
8Fh
The hard disk controller has been reset. Conguring the oppy drive controller
next.
91h
The oppy drive controller has been congured. Conguring the hard disk drive
controller next.
95h
Initializing the bus option ROMs from C800 next. See the last page of this chapter
for additional information.
96h
97h
Initialization before the C800 adaptor ROM gains control has completed. The adaptor ROM check is next.
98h
The adaptor ROM had control and has now returned control to BIOS POST. Performing any required processing after the option ROM returned control.
99h
Any initialization required after the option ROM test has completed. Conguring the
timer data area and printer base address next.
9Ah
Set the timer and printer base addresses. Setting the RS-232 base address next.
9Bh
Returned after setting the RS-232 base address. Performing any required initialization before the Coprocessor test next.
9Ch
Required initialization before the Coprocessor test is over. Initializing the Coprocessor next.
9Dh
Coprocessor initialized. Performing any required initialization after the Coprocessor test next.
9Eh
Initialization after the Coprocessor test is complete. Checking the extended keyboard,
keyboard ID, and Num Lock key next. Issuing the keyboard ID command next.
A2h
A3h
The soft error display has completed. Setting the keyboard typematic rate next.
A4h
The keyboard typematic rate is set. Programming the memory wait states next.
A5h
Memory wait state programming is over. Clearing the screen and enabling parity
and the NMI next.
A7h
NMI and parity enabled. Performing any initialization required before passing control
to the adaptor ROM at E000 next.
A8h
Initialization before passing control to the adaptor ROM at E000h completed. Passing
control to the adaptor ROM at E000h next.
B-6
Checkpoint
Code Description
A9h
Returned from adaptor ROM at E000h control. Performing any initialization required
after the E000 option ROM had control next.
Aah
Initialization after E000 option ROM control has completed. Displaying the system
conguration next.
Abh
Uncompressing the DMI data and executing DMI POST initialization next.
B0h
B1h
00h
Code copying to specic areas is done. Passing control to INT 19h boot loader
next.
B-7
Notes
B-8